Abstract: Methods and arrangements are provided for minimizing delay in a high-speed tap arrangement are disclosed and include hardware and software arrangements and methods for quickly switching the transmission path for data between a primary data path and a bypass data path. The switching is accomplished rapidly using set of powered analog switches and a relay to minimize packets loss in the event of power loss. Further, when power is restored, software and hardware methods and arrangements disclosed herein permit the data path to be promptly restored resulting in the restoration of tapping ability quickly after power is restored.

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Abstract: A method for controlling an SCR-type switch, comprising applying to the switch gate several periods of an unrectified high-frequency voltage, the power of one HF halfwave being insufficient to start the SCR-type switch.

Abstract: A vertical SCR switch to be controlled by a high-frequency signal having at least four main alternated layers. The switch includes a gate terminal and a gate reference terminal connected via integrated capacitors to corresponding areas. In the case of a thyristor, having on its front surface side a main P-type semiconductor area formed in an N-type gate semiconductor area, a first portion of the main area being connected to one of the main areas, a second portion of the main area is connected to one of the control terminals via a first integrated capacitor, and a portion of the gate area being connected to the other of the control terminals via a second integrated capacitor.

Abstract: Plug-in electrical switching devices which allow a load device to be electrically connected to and disconnected from an electrical power source at either: (a) a switched outlet electrically coupled between the power source and the load and (b) a location in the vicinity of the load.

Abstract: A power driver circuit for turning a semiconductor switching device on and off in response to receipt of a control signal includes a trigger circuit that turns on a latching switch at a speed that is independent of the rate of change of the control signal. The trigger circuit is responsive to the control signal to apply a current from the semiconductor switching device to the latching switch. A high speed SCR may be used as the latching switch and may be triggered by a small trigger current from the gate of the semiconductor switching device fed to both the anode and cathode gates of the SCR. High speed diodes may also be used to increase the speed of the circuit. The power driver circuit improves the efficiency of the semiconductor switching device by decreasing the time the switching device spends in transition its two steady states.