Abstract: A combining network for an array of SPAD devices includes: synchronous sampling circuits, wherein each synchronous sampling circuit is coupled to an output of a corresponding SPAD device and is configured to generate a pulse or an edge each time an event is detected; and a summation circuit coupled to an output of each of the synchronous sampling circuits and configured to count a number of pulses or edges to generate a binary output value.

Abstract: Adaptive RF filters based on modulated resonators are provided. The filter architecture is based on time-interleaved commutation of passive RF resonators. The architecture can behave as a two-port filter network, with a fully tunable instantaneous filter bandwidth. The filters are applicable as miniaturized, environment-aware RF signal processing components and can be used in mobile communications.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: Techniques for wired and wireless charging of electronic devices are provided. An example of a method for charging a device according to the disclosure includes receiving a signal from a power source with an electronic circuit, such that the electronic circuit includes a synchronous rectifier comprising a first phase leg and a second phase leg, utilizing the first phase leg to implement synchronous rectification and the second phase leg to implement a single phase buck converter when the signal is a wireless signal received from the power source, utilizing the first phase leg and the second phase leg to implement a multi-phase buck converter when the signal is received from a wired power source, and providing an output signal with the electronic circuit.

Abstract: Embodiments for characterizing ear canal acoustic impedance and reflectance by pole-zero fitting are disclosed. Embodiments include transmitting an acoustic signal into an ear canal by a transducer having an acoustic source pressure. Further embodiments, measure complex cavity pressure, P(f), response based on the transmitted acoustic signal reflected by eardrum using an acoustic measurement device. Additional, such embodiments, calculate complex acoustic reflectance (CAR) based on the P(f). Other embodiments determine number of poles and zeroes of CAR pole-zero model to reduce residual error between the CAR pole-zero model and CAR data stored in memory within a threshold. Also, embodiments verify the residual error of CAR pole-zero model compared to the CAR data is within the threshold. Further, embodiments factor the CAR pole-zero model into an all pass component and a minimum phase component. Additional embodiments determine ear drum impedance by removing the all phase component of the CAR pole-zero model.

Abstract: A signal identification device identifies the carrier mode applied to a received signal that has control information embedded therein by extracting the control information from the received signal, generating multiple reference signals, each of the reference signals corresponding to one of multiple formulations of control information for one or more carrier transmission modes, performing a correlation operation on the control information against each of the reference signals, and determining the carrier mode based on results of the correlation operations.

Abstract: A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: Provided is a discharge lamp lighting device, which can control a load precisely while improving the practicability. When the difference of a count number (Nn) becomes a predetermined threshold value or less, a predictor circuit (35) predicts the timing, at which a current value (iQ1) becomes a peak value, on the basis of the rate of change of the difference. A switch selecting circuit (38), which is driven with a clock frequency higher than the sampling frequency of a first converter unit (32), turns off a field effect transistor (Q1) at the turn-off timing, and turns on a field effect transistor (Q2). A plurality of A/D converters (37a) are subjected to a multi-rate control, thereby to correct the threshold value of the predictor circuit (35) on the basis of the peak value of a lamp current (iOUT).

Abstract: A 4× over-sampling data recovery system consists of a charge pump PLL, a 4× over-sampler, a data regenerator and a digital PLL. The charge pump PLL receives a clock signal and generates a plurality of multiplicative clock signals in response to the clock signal. The 4× over-sampler samples a serial data to generate a M-bit signal according to the plurality of multiplicative clock signals, wherein each bit in the serial data is sampled for four times. The data regenerator sequentially receives and combines two M-bit signals to generate a (M+N)-bit signal. The digital PLL divides the (M+N)-bit signal into (N+1) groups of M-bit data and selects a designated M-bit data from the (N+1) groups of M-bit data to generate a P-bit recovery data.

Abstract: Methods and apparatuses for reducing noise in frequency to digital converters (FDCs). An FDC apparatus includes a first FDC, a second FDC and a combiner. The first and second FDCs are configured to independently sample an input signal according to a sample clock to generate first and second digital signals, each representing the instantaneous frequency of the input signal. The combiner is configured to form a resultant digital signal from the first and second digital signals. The first and second FDCs are designed and combined in the noise-canceling FDC apparatus so that the first and second signals they generate have correlated noise profiles in a frequency range of interest. When combined by the combiner to form the resultant digital signal, the resultant digital signal has a signal power to noise power ratio greater than the signal power to noise power ratios characterizing the first and second digital signals of the individual first and second FDCs.

Abstract: Method for decoding a signal sent over a bandwidth-expanding communication system, where both channel estimation and signal detection are carried out on a set of samples generated by sampling the received signal at a sub-Nyquist rate, thus allowing for a significant reduction of the complexity of the sampling device of receivers using said method, as well as a significant reduction of their computational requirements.

Abstract: A gated peak detector produces phase-independent, magnitude-only samples of an RF signal. Gate duration can span as few as two RF cycles or thousands of RF cycles. Response is linearly proportional to RF amplitude while being independent of RF phase and frequency. A quadrature implementation is disclosed. The RF magnitude sampler can finely resolve interferometric patterns produced by narrowband holographic pulse radar.

Abstract: A frequency generating arrangement for generation of at least two predetermined frequencies is introduced. The arrangement comprises a phase locked loop circuit with at least two control value storage units and at least one controlled oscillator unit, wherein the control value storage units being configured to selectively output a control signal to the at least one voltage controlled oscillator unit, causing generation of one of the at least two predetermined frequencies. Frequency generating system for generation of ultra-fast hopping-frequency sequences comprises at least a first and a second frequency generating arrangement and further a controlling unit and a multiplexer unit for selectively connecting only one of the outputs of the two frequency generating arrangements with an output of the system.

Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.

Abstract: A stream of data may flow over a fiber or other medium without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Embodiments describe clock and data recovery (CDR) circuits which may sample a data signal at a plurality of sampling points to partition a clock cycle into four phase regions P1, P2, P3, and P4 which may be represented on a phase plane being divided into four quadrants. A relative phase between a data signal transition edge and a clock phase may be represented by a phasor on the phase plane. The clock phase and frequency may be adjusted by determining the instantaneous location of the phasor and the direction of phasor rotation in the phase plane.

Abstract: The invention relates to an automation device, in which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The device has a microcontroller (110), which is assigned at least one clock generator (120) and one memory unit (150), and which is connected at least to one data source (140), which is designed to output a data bit-stream to be transmitted. A sequential sequence of equidistant samples of a sinusoidal time profile is stored in the memory unit (150), such that it can be called up, in such a manner that the samples can be output using either the clock of the first clock generator or the clock of the second clock generator, depending on the data bit-stream.

Abstract: A frequency switching method is used to make switching among a plurality of frequency signal sources each providing a specific frequency range covering multiple bands. The method includes steps of providing a target frequency data; selecting one of the frequency signal sources to output a first clock signal; generating a first frequency data according to the clock signal of the first frequency to compare with the target frequency data; outputting a second clock signal with the highest band of another one of the frequency signal sources possessing a frequency range higher than that of the selected frequency signal source when the target frequency data is greater than the first frequency data; and outputting the second clock signal with the lowest band of the selected frequency signal source when the target frequency data is smaller than the first frequency data.

Abstract: A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning phase of the input signal at the start of the period, which includes generating a first reference signal having a first reference signal frequency and a first reference signal phase synchronized with the start of the period, and detecting a first time interval required for the input signal phase to have a first specified relationship to the first reference signal phase. The technique includes similarly determining a relative ending phase of the input signal at the end of the period. The technique includes determining an input signal temporal characteristic from the number of transitions and the relative beginning phase and the relative ending phase.

Abstract: In a phase sync circuit (40) which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit (40) of a dual loop configuration including both a phase comparison circuit (81) and a frequency comparison circuit (10), a phase sync circuit (40) capable of achieving both broadening of the capture range and extraction of a high-quality clock signal without requiring any reference clock signal is provided. A clock signal Ca, another clock signal Cb having a phase delayed by an approximately ¼ period from the clock signal Ca and the data signal D are input to the frequency comparison circuit (10) to output a logical value according to the high-low relationship between the frequency of the clock signal and the bit rate of the data signal D.

Abstract: A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal, (B) determining a first value indicating a position of the first edge, (C) adding the first value to a second value, wherein the second value indicates a position of a second edge of the data signal and (D) adjusting the clock signal based on the result of step (C).

Abstract: A system and method for accurately measuring a pulse run length in a high frequency (HF) data signal while utilizing a low analog-to-digital conversion (ADC) sampling rate. Four bits are added to the most significant end of an oscillator's accumulator register so that the oscillator generates a sawtooth clock waveform ranging in phase from zero (0) to 32&pgr; radians. An interpolator detects a first zero-crossing transition of the HF data signal at the leading edge of the pulse run length, and a phase detector measures a first phase increment at that time. The MSBs of the accumulator register is then initialized to place the measured first phase increment in a range between zero (0) and 2&pgr; radians. The accumulator register then accumulates phase increments until the interpolator detects a second zero-crossing transition of the HF data signal at the trailing edge of the pulse run length, and the phase detector measures a second phase increment when the second zero-crossing transition is detected.

Abstract: A bi-directional semiconductor light source is formed that provides emission in response to either a positive or negative bias voltage. In a preferred embodiment with an asymmetric injector region in a cascade structure, the device will emit at a first wavelength (&lgr;−) under a negative bias and a second wavelength (&lgr;+) under a positive bias. In other embodiments, the utilization of an asymmetric injector region can be used to provide a light source with two different power levels, or operating voltages, as a function of the bias polarity.

Abstract: A method and apparatus for detecting a sinusoidal signal samples a received signal. An error signal generator receives at its inputs two previous samples of the signal and a current sample of the signal and generates an error signal based on these previous and current samples. A comparison circuit compares the generated error signal for the current sample to an error threshold value and generates a threshold comparison signal that indicates whether the generated error signal is below the error threshold value. A determination circuit then determines whether the received signal is a sinusoidal signal based on the threshold comparison signals that are generated for a plurality of samples.

Abstract: The present invention, generally speaking, provides a very simple, all-digital method and apparatus for determining the ratio of frequencies of two signals. One of the signal may be a known reference frequency, allowing the instantaneous frequency of an unknown input signal to be readily determined. A frequency sampling technique is employed that produces a stream of digital bits which contains information regarding the ratio of frequencies. From the stream of digital bits is formed a digital word indicative of the ratio of frequencies. The digital word may be formed using a digital filter. Advantageously, an extensive body of digital filtering techniques applicable to Sigma-Delta (sometimes referred to as Delta-Sigma) A/D converters may be applied directly to the digital stream. By using an appropriately-chosen weighting function, high accuracy may be obtained.

Abstract: A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.

Abstract: A clock frequency detector is provided having a precise trip frequency which is insensitive to power supply variations. In one embodiment, the clock frequency detector employs a current source to discharge a capacitor at a constant rate and a gated current source to charge the capacitor at a frequency-dependent rate. If the charge rate exceeds the discharge rate, the capacitor will charge and an output signal is asserted. The gated current source is controlled by an edge-triggered pulse generator which generates pulses of a precise width in response to edges in the input clock signal. To create these pulses, the pulse generator produces an inverted clock signal with delayed transitions and combined this signal with the clock signal. The delayed transitions are created using a capacitor which is charged by a current source. The capacitor is provided with a shunt transistor which drains the charge from the capacitor whenever the clock signal is asserted.

Abstract: A switched capacitance circuit, using a switched operational amplifier structure as an input switch of the switched capacitance, is provided with a new biasing circuit. An additional switched capacitor, switched alternately to power supply and to ground, is connected to the output side of the primary switched capacitor. Precision is retained while ensuring a rail-to-rail dynamic range, without requiring boosted control phases. Special arrangements may be implemented for controlling the amplitude of switching spikes when so required. A fully differential embodiment is also feasible with additional advantages.

Abstract: A speed governor for an integrated circuit which prevents the operation of the integrated circuit above a selected frequency. The speed governor generates a frequency reference and compares the frequency reference to the frequency of the external clock signal that clocks the integrated circuit. As a result of the comparison, if the frequency of the input clock signal is greater than the frequency reference then operation of the integrated circuit is disrupted.

Abstract: An improved switching power supply includes a variable frequency switching circuit. The frequency of the switching circuit is varied to minimize interaction between generated power supply noise and an electronics device powered by the power supply. The operating frequency or frequencies of the powered electronics device are monitored to allow continuous real time control over the switching circuit frequency to be provided.

Abstract: A digital resampling system is provided for converting a first digital signal to a second digital signal, where both signals represent the same analog signal but sampled at two different clock rates which are not phase-locked together. A filter is clocked by the first clock and outputs filtered samples at the first clock rate, optionally omitting samples which will not be used. A phase indicator determines the relative phase position of the first and second clocks and indicates an integer phase value and a fractional phase value which together indicate where a tick of the second clock falls among the ticks of the first clock. The integer phase value identifies a clock cycle of the first clock in which a tick of the second clock occurs, and the fractional phase value represents a fraction identifying a position of the tick of the second clock within the clock cycle of the first clock. A sample selector selects M filtered samples from those provided by the non-decimating filter based on the integer phase value.

Abstract: In a narrow-band filter for filtering an input signal having a predetermined frequency and comprising first through n-th low-pass filters (13-1 to 13-n) which are connected in parallel to one another, a switching circuit time divisionally connects the first through the n-th low-pass filters between input and output terminals (11, 12). The first through the n-th low-pass filters, thereby, time divisionally filters the input signal for first through n-th filtering durations, respectively. A control circuit (30) is supplied with a frequency designation signal designating the predetermined frequency and controls the switching circuit to change at least one of the first through the n-th filtering durations in accordance with the frequency designation signal.

Abstract: A time measurement system for measuring time accurately with an inaccurate clock, in which two clock oscillators are compared and the momentary error of the slower clock oscillator is measured. When the error change rate of the slower clock oscillator is slow enough the fast clock oscillator can be switched off for longer time intervals. With the help of this apparatus and method of operation power can be saved in portable equipment which requires accurate time measurement.