Abstract: A high-voltage bidirectional switch, including a high-voltage bidirectional switching element, and circuitry for making the switching element bistable and controllable by, at most, two low-voltage pulse signals.

Abstract: The present invention teaches a dimmer which incorporates an alternating current (AC) trigger which exhibits asymmetrical electrical characteristics. This eliminates the undesirable snap on hysteresis effect associated with conventional dimmers utilizing symmetrical AC triggers such as diacs and silicon bilateral switches (SBS). One embodiment of the present invention utilizes a zener diode to create the asymmetry. During one polarity of the AC source, the breakover voltage of the trigger is increased, forcing the trigger to breakover at a time later in the AC cycle than it would otherwise have with a symmetric trigger. This compensates for charge dumping of the phase control capacitor into the gate of the triac which would otherwise cause the snap on hysteresis effect.

Abstract: A circuit for controlling operation of a load, such as an alarm circuit in a fire protection system, in which operation of the load is delayed for an adjustable time period. The load control circuit includes a DIAC for generating a first trigger signal, an SCR which generates a second trigger signal, and a switch, preferably a TRIAC, which provides a supply voltage to the load upon receipt of the second trigger signal. A variable resistor is provided to adjust the time required to generate the first trigger signal.

Abstract: A circuit arrangement for limiting the current to be switched of an electrical load, with the power input of the electrical load being controlled by means of a Triac, said Triac being connected in series with the electrical load, with a Diac being connected to the gate terminal of the Triac, said Diac being connected in series with a resistor arrangement whose resistance value is variable for the purpose of controlling the Triac, said Triac being disconnectible from the power supply by means of a first switch, wherein a second switch is provided by means of which the series arrangement comprised of the resistor arrangement and the Diac is disconnectible from the power supply, and wherein, on turning the electrical load on, the first switch is closed first, while the second switch is closed with a time delay. Advantageously, on turning the electrical load off, the second switch is opened first, while opening of the first switch occurs with a time delay.

Abstract: The present invention teaches a dimmer which incorporates an alternating current (AC) trigger which exhibits asymmetrical electrical characteristics. This eliminates the undesirable snap on hysteresis effect associated with conventional dimmers utilizing symmetrical AC triggers such as diacs and silicon bilateral switches (SBS). One embodiment of the present invention utilizes a zener diode to create the asymmetry. During one polarity of the AC source, the breakover voltage of the trigger is increased, forcing the trigger to breakover at a time later in the AC cycle than it would otherwise have with a symmetric trigger. This compensates for charge dumping of the phase control capacitor into the gate of the triac which would otherwise cause the snap on hysteresis effect.

Abstract: A method for regulating the power in a load connected to the mains through a controlled switch and a device for implementing the method. The method includes the following steps: detecting a mains synchronization pulse, which determines the start of a cycle, within a fixed time interval of the preceding cycle; as soon as the pulse has been detected, waiting for the end of the fixed interval, then counting down a first time interval that substantially corresponds to a selected time interval; at the end of the first time interval, triggering the switch on and counting down a second time interval that ends before the normal arrival of the next synchronization pulse; and at the end of the second time interval, counting down the fixed time interval within which the next synchronization pulse must be detected.