Abstract: A system includes a detector array having a plurality of level detectors to monitor an optical input signal. Each level detector of the detector array operates in a different operating range, and each operating range for each level detector has a different saturation level and a different cutoff level based on a power level of the optical input signal. A controller monitors the plurality of level detectors of the detector array to detect a present power level for the optical input signal by selecting the operating range that is associated with the level detector operating between its saturation level and its cutoff level.

Abstract: A system includes a detector array having a plurality of level detectors to monitor an optical input signal. Each level detector of the detector array operates in a different operating range, and each operating range for each level detector has a different saturation level and a different cutoff level based on a power level of the optical input signal. A controller monitors the plurality of level detectors of the detector array to detect a present power level for the optical input signal by selecting the operating range that is associated with the level detector operating between its saturation level and its cutoff level.

Abstract: A frequency monitoring system comprises a plurality of circuit cards. Each circuit card, such as a primary multiplexer card and a backup or redundant multiplexer card, has an oscillator that provides a reference clock signal. On each circuit card, a respective frequency compare element is configured to receive a clock signal to be measured and to provide a frequency error signal indicating a frequency error of the clock signal relative to an average frequency of a plurality of reference clock signals. Accordingly, the frequency measurements for the circuit cards are based on the same reference frequency (e.g., the average frequency of the reference clock signals from the oscillators).

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Abstract: This disclosure describes a dual inductor circuit, which may be particularly useful in a mixer of a wireless communication device to allow the mixer to operate for two different frequency bands. The dual inductor circuit comprises an inductor-within-inductor design in which a small inductor is disposed within a large inductor. The two inductors may share a ground terminal, but are otherwise physically separated and independent from one another. Terminals of the inner inductor, for example, are not tapped from the outer inductor, which can reduce parasitic effects and electromagnetic interference relative to tapped inductor designs. The independence of the inductors also allows the different inductors to define different resonance frequencies, which is desirable.

Abstract: A signal preprocessing device is disclosed, which is integrated into a structure-borne sound sensor or into an acceleration sensor for sensing structure-borne sound, or which is connected at the input end to at least one sensor of this type and is connected at the output end to at least one signal channel that is connected to at least one central electronic control unit, and wherein the signal preprocessing device has at least one filter module having at least two bandpass filters. A method for preprocessing structure-borne sound sensor signals is also disclosed, in which a filtering operation is carried out in which at least two frequency bands, which are at least to a certain extent part of the structure-borne sound spectrum, are transmitted. Use of the above device in electronic motor vehicle security systems, in particular safety systems, in particular in vehicle occupant protection systems and/or passenger protection systems is also disclosed.

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a phase difference between the output signal and the input signal, and to adjust a phase of the output signal based on the samples of the phase difference. Additional apparatus, systems, and methods are disclosed.

Abstract: A frequency generating arrangement for generation of at least two predetermined frequencies is introduced. The arrangement comprises a phase locked loop circuit with at least two control value storage units and at least one controlled oscillator unit, wherein the control value storage units being configured to selectively output a control signal to the at least one voltage controlled oscillator unit, causing generation of one of the at least two predetermined frequencies. Frequency generating system for generation of ultra-fast hopping-frequency sequences comprises at least a first and a second frequency generating arrangement and further a controlling unit and a multiplexer unit for selectively connecting only one of the outputs of the two frequency generating arrangements with an output of the system.

Abstract: A circuit is described that detects high and low frequencies and additional clock frequencies and outputs a signal that indicates a high, a low frequency or an additional mode. When in the low frequency low frequency mode signals are regenerated free of any high frequency signals from appearing on the filtered low frequency clock line. The rising and falling edges of the input clock are low pass filtered separately and then combined to generate a low frequency clock or the additional input clock and that retains the input clock pulse width and duty cycle.

Abstract: Frequency discriminator based on a variant of the DFT transform in which the usual twiddle factors are replaced with twiddle factors as for a DFT on a number of points which is the double as the actual number of sample points. The DFT so modified allows half-bin frequency discrimination, with few added computational burden. Two DFT shifted of half bin with respect to the zero frequency provide a linear response of the discrimination and good immunity to noise. The discriminator is particularly useful in FLL for tracking signals in a GPS receiver.

Abstract: A method and system for monitoring a frequency of a clock signal is disclosed. The method and system comprise dividing a clock signal into a plurality of clock signal components. The method and system further comprise adding a delay to each of the clock signal components and comparing the plurality of signal components with each of the delayed clock signal components to monitor whether the clock signal is within a predetermined frequency range. The method and system includes providing an output signal indicative of a condition of the clock signal based upon the comparing step.

Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.

Abstract: A logarithmic detector circuit including a drive circuit to receive a modulated input signal and generate a buffered modulated signal, a signal shaping circuit coupled to the drive circuit and configured to shape a voltage range of the buffered modulated signal to generate a shaped modulated signal, and a detecting circuit to detect the shaped modulated signal to generate an output signal substantially proportional to a logarithm of an amplitude of the modulated input signal.

Abstract: Frequency discriminator based on a variant of the DFT transform in which the usual twiddle factors are replaced with twiddle factors as for a DFT on a number of points which is the double as the actual number of sample points. The DFT so modified allows half-bin frequency discrimination, with few added computational burden. Two DFT shifted of half bin with respect to the zero frequency provide a linear response of the discrimination and good immunity to noise. The discriminator is particularly useful in FLL for tracking signals in a GPS receiver.

Abstract: The present invention provides a method involving at least one first circuit having at least one first input, at least one second input, and at least one output. The method includes determining at least one first value of at least one output of a second circuit based on at least one first value of the at least one first input. The second circuit has been configured using first configuration information generated based on the first circuit and at least one first value of the at least one second input. The method also includes generating, concurrently with determining the at least one first value of said at least one output, second configuration information based on the first circuit and at least one second value of the at least one second input.

Abstract: Pursuant to certain embodiments of the present invention, methods of generating an internal clock signal in a semiconductor memory device are provided in which the frequency of an external clock signal is measured. A CAS latency value of the semiconductor memory device is automatically set based at least in part on the measured frequency of the external clock signal. The automatically set CAS latency value is then used to generate the internal clock signal from the external clock signal. In these methods, the delay of a delay lock loop of the semiconductor memory device may be based at least in part on the automatically set CAS latency value. The internal clock signal may be generated from the external clock signal using the delay lock loop. Circuits and methods for measuring the frequency of the external clock signal are also provided.

Abstract: A method and an apparatus to provide time-based edge-rate compensation have been disclosed. In one embodiment, the apparatus includes a reference pad, a reference circuit coupled to the reference pad, the reference circuit being operable to charge and to discharge a reference voltage at the reference pad, and an edge-rate detection and measurement circuit coupled to the reference pad to detect and to measure an edge-rate of the reference voltage at the reference pad. Other embodiments have been claimed and described.

Abstract: An integrated circuit device includes a pin for receiving a DC voltage component signal. The device includes a signal source for applying an AC signal to the pin, a buffer for converting the AC signal into a digital signal, and a digital detector for detecting a frequency of the digital signal and outputting a predetermined detection signal. The predetermined detection signal is activated when the frequency of the digital signal is greater than or equal to a predetermined frequency. The predetermined detection signal is used as a signal for setting predetermined functional modes. The device further includes registers or a differential amplifier and a decoder for generating a plurality of functional mode signals.

Abstract: An integrated voltage controlled oscillator is provided. The integrated voltage controlled oscillator includes a first slab inductor having two ends and a second slab inductor having two ends. A first oscillator core is connected to a first end of the first slab inductor and a second end of the second slab inductor, and a second oscillator core is connected to a second end of the first slab inductor and a first end of the second slab inductor. In this manner, the low-loss slab inductors provide the oscillator tank inductance.

Abstract: According to some embodiments, a low gain phase-locked loop circuit is provided.

Abstract: A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal, (B) determining a first value indicating a position of the first edge, (C) adding the first value to a second value, wherein the second value indicates a position of a second edge of the data signal and (D) adjusting the clock signal based on the result of step (C).

Abstract: A push-button signal receiving circuit and a push-button signal detection method are provided which can enhance frequency detection accuracy and yet can reduce erroneous determination as to the valid length of PB signal and thus erroneous operation. Valid signal determining portion determines the validity of a received PB signal in accordance with the results of determination as to the coincidence of continuance times of identification signals extracted by first and second frequency detecting portion for performing frequency detection over a small number of periods, and the coincidence of the frequencies detected by the first and second frequency detecting portion with those detected by third and fourth frequency detecting portion over a large number of periods.

Abstract: A bi-directional semiconductor light source is formed that provides emission in response to either a positive or negative bias voltage. In a preferred embodiment with an asymmetric injector region in a cascade structure, the device will emit at a first wavelength (&lgr;−) under a negative bias and a second wavelength (&lgr;+) under a positive bias. In other embodiments, the utilization of an asymmetric injector region can be used to provide a light source with two different power levels, or operating voltages, as a function of the bias polarity.

Abstract: An integrated processor includes a microprocessor core and a bus interface unit. The integrated processor receives a reference clock signal and an external clock signal. The frequency of the reference clock signal is compared to the frequency of the external clock signal. Based upon this comparison, the appropriate frequency for the internal clock signal that controls the bus interface unit is determined. A clock generation circuit, such as a phase-locked loop, generates the appropriate frequency for the internal clock signal based upon the comparison of the reference clock signal and external clock signal.

Abstract: A reference ring oscillator circuit (RROC) is used to determine timing characteristics of a test interconnect structure in an integrated circuit. The RROC includes an odd number of inverters coupled together in a ring manner and has defined test segments at which a test interconnect can be loaded. Reference timing characteristics of the unloaded RROC are determined according to a calibration method including the steps of: (a) directly measuring signal propagation delay through each segment of the RROC; (b) modeling each test segment using an RC tree type reference circuit model having reference elements; (c) simulating the reference circuit model to provide a functional relationship between two reference capacitors; (d) defining upper and lower bounds for propagation delay through the test segment in terms of the reference elements; (e) determining values for the reference capacitor elements; and (f) measuring a reference frequency of oscillation of the unloaded RROC.

Abstract: A reference ring oscillator circuit (RROC) is used to determine timing characteristics of a test interconnect structure in an integrated circuit. The RROC includes an odd number of inverters coupled together in a ring manner and has defined test segments at which a test interconnect can be loaded. Reference timing characteristics of the unloaded RROC are determined according to a calibration method including the steps of: (a) directly measuring signal propagation delay through each segment of the RROC; (b) modeling each test segment using an RC tree type reference circuit model having reference elements; (c) simulating the reference circuit model to provide a functional relationship between two reference capacitors; (d) defining upper and lower bounds for propagation delay through the test segment in terms of the reference elements; (e) determining values for the reference capacitor elements; and (f) measuring a reference frequency of oscillation of the unloaded RROC.

Abstract: A telephone answering device (TAD) includes a remote access mode which is operative responsive to dual tone multi-frequency (DTMF) signals. At least three bandpass filters each receive an input signal from a telephone line interface provided in the TAD. A software controlled sampling section receives outputs from all the bandpass filters for sampling outputs from the bandpass filters, the sampling section including a multiplexer which receives the outputs from all of the bandpass filters, and a peak hold circuit coupled to an output of the multiplexer. An analog-to-digital converter receives an output from the peak hold circuit, and a digital controller receives the output of the analog-to-digital converter for controlling operations of the TAD in a remote access mode responsive to the detected DTMF signals. First and second ones of the bandpass filters have respective center frequencies corresponding to frequencies of respective DTMF signals and a third bandpass filter has a different center frequency.

Abstract: A harmonic filter for active or adaptive noise attenuation control systems for obtaining the complex amplitude of a single harmonic component from a signal which contains one or more harmonic components.

Abstract: A detector (100) determines whether an input signal (10) comprises a first signal or a second signal. A first local signal (207) is generated based on the first signal and a second local signal (307)is generated based on the second signal. A first error (211) is formed based on the first local signal and a scaled input signal (50), and a second error (311) is formed based on the second local signal and the scaled input signal. A first distance (215) between the scaled input signal and the first local signal is formed based on the first error, while a second distance (315) between the scaled input signal and the second local signal is formed based on the second error. Whether the input signal comprises the first signal or the second signal is determined by comparing (60) the first distance to the second distance.

Abstract: A dual tone detector (100) for a single dual tone, a dual tone multi-frequency (DTMF), or similar system processes an input signal through both bandpass (103) and band reject (104) tone detectors. If both the bandpass (103) and band reject (104) tone detectors detect a tone, then the dual tone detector (100) provides a tone detect output signal. If only the bandpass tone detector (103), which is susceptible to false tones, detects a tone, then a voice input signal is muted and the tone detector (100) activates the tone detect output signal only if both the bandpass (103) and band reject (104) tone detectors subsequently detect a tone. In one embodiment, a dual bandpass/band reject tone detector (120) processes the input signal through shared front-end band reject filters (121, 122), limiters (124), resonators (127, 128), and a processing section (130) in order to save circuit area. Limiter and peak detector functions are also implemented in shared circuitry to further reduce circuit area.