Inverse Parallel Connection Patents (Class 327/505)
  • Patent number: 8253471
    Abstract: This document discusses, among other things, a system and method for offsetting reverse-bias leakage of a high impedance bias network. In an example, an apparatus includes an anti-parallel diode pair coupled between a signal node and a common-mode node. The anti-parallel diode pair can include a first diode and a second diode coupled to the first diode. A third diode can be coupled between a supply node and the signal node, and the third diode can be sized to compensate for a parasitic diode junction of the anti-parallel diode pair.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: August 28, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Christopher Bennett, Hrvoje Jasa
  • Publication number: 20120200335
    Abstract: One high-frequency switch Qm supplied with transmit and receive signals to ON, and another high-frequency switch Qn supplied with a signal of another system to OFF are controlled. In the other high-frequency switch Qn, to set V-I characteristics of near-I/O gate resistances Rg1n-Rg3n of a near-I/O FET Qn1 near to a common input/output terminal I/O connected with an antenna are set to be higher in linearity than V-I characteristics of middle-portion gate resistances Rg3n and Rg4n of middle-portion FETs Qn3 and Qn4. Thus, even in case that an uneven RF leak signal is supplied to near-I/O gate resistances Rg1n-Rg3n, and middle-portion gate resistances Rg3n and Rg4n, the distortion of current flowing through the near-I/O gate resistances Rg1n-Rg3n near to the input/output terminal I/O can be reduced.
    Type: Application
    Filed: April 16, 2012
    Publication date: August 9, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shigeki Koya, Shinichiro Takatani, Takashi Ogawa, Akishige Nakajima, Yasushi Shigeno
  • Patent number: 7018095
    Abstract: A circuit for sensing on-die temperature at multiple locations using a minimum number of pins is described. Thermal diodes coupled to pins are placed on a die to measure the temperature at various die locations. Voltage is applied to the pins to determine the temperature at each given diode location. The polarity of the voltage applied across the pins determines what diodes are selected for measurement.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Dean J. Grannes, Harjinder Singh, Jason A. Gayman
  • Patent number: 6084458
    Abstract: A bi-directional transistor structure is provided, which can help solve the problem of degraded performance due to hot carrier injection (HCI) effect that is otherwise prominent in conventional bi-directional transistors.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: July 4, 2000
    Assignee: United Microelectronics Corp.
    Inventor: Kuan-Yu Fu
  • Patent number: 5714900
    Abstract: An electrical overstress power protection device consists of a diode limiter array and an input and output electrical matching network. All of these functions are integrated monolithically on a single semiconductor chip which allows ease of use, small size, and high frequency operation. The device is used to protect instrument input and output circuitry from damage.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: February 3, 1998
    Assignee: Hewlett-Packard Company
    Inventor: Eric R. Ehlers