Abstract: A fuse cell circuit includes a first fuse and a first fuse sense circuit that senses a programming state of the first fuse and supplies an indication thereof. A sense control circuit includes a plurality of reference fuses and a second fuse sense circuit coupled to the reference fuses. The sense control circuit supplies a sense control signal to the fuse cell circuits to cause the fuse cell circuits to sense the programming state of the first fuse when the sense control signal is asserted. The sense control signal is asserted for a time period determined , at least in part, by a resistance value of the reference fuses. The integrated circuit may also include a resistance varying circuit coupled to vary a resistance value of a current path of the reference fuses according to one or more control signals.

Abstract: An integrated polysilicon fuse and diode and methods of making the same are provided. The integrated polysilicon fuse and diode combination may be implemented in a programmable cross point fuse array. The integrated polysilicon fuse and diode may be used in a random access memory (RAM) cell. The polysilicon diode may be isolated from a substrate and other devices, use less area on a substrate, and cost less to manufacture compared to other diodes.

Abstract: An apparatus and method for improving the gate oxide reliability of an antifuse circuit is provided by coupling the gate input of a protection device of the antifuse circuit to a voltage converter circuit. In a program mode, a first voltage is applied through the voltage converter circuit to the gate input of the protection device to limit the voltage passed to internal transistor devices, thus increasing their gate oxide reliability. In a normal operation mode, however, a second, lower voltage is applied through the voltage converter to the gate input of the protection device to remove the large voltage stress placed across the gate oxide of the protection device itself. The voltage converter may attenuate the first voltage to create the second voltage or it may switch its output between the first and second voltage levels.

Abstract: A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, the fuse formed from a part of the uppermost wiring level, and a surface protective film formed on the uppermost wiring level.

Abstract: A fuse-based cell. The fuse-based cell includes a fuse with a programming device electrically coupled to the fuse to program the fuse. A sensing device is electrically coupled to the fuse to sense a programming state of the fuse. A clamping device is electrically coupled to the sensing device to control voltages across the sensing device during programming. A pass device is electrically coupled to the sensing device to control voltages across the sensing device during sensing.

Abstract: An antifuse circuit serves to generate an antifuse enable signal for use in repairing a defected memory cell in a semiconductor device. The inventive antifuse includes: an antifuse unit employing an antifuse, wherein the antifuse is controlled as being shorted or insulated according to a repair program; an antifuse precharge unit for precharging the antifuse by using a predetermined voltage level in response to a power-up signal, wherein the predetermined voltage level is lower than that of an external voltage source; and an output latch unit driven by the predetermined voltage level for latching a antifuse voltage level appearing on the antifuse and generating the antifuse enable signal corresponding to the antifuse voltage level.

Abstract: An oxide anti-fuse structure is provided with vertical-drain NMOS transistors and vertical-source-drain NMOS transistors to obtain higher area density and low programming current requirement.

Abstract: A polysilicon fuse trim read cell utilizes a fuse structure in a single bit memory cell. When the fuse structure is blown, the memory cell can be read and its stored value retained as a digital output. The cell uses no power in the steady state.

Abstract: An integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser fuse between the bond pad and the second input buffer is blown. In another operating configuration of the die, the die uses the second input buffer but does not use the first input buffer, so the laser fuse between the bond pad and the first input buffer is blown. As a result, the capacitive load on the bond pad is similar to the capacitive load on similar bond pads in the die connected to only one input buffer in the die. Thus, signals propagate into all the bond pads at about the same improved speed.

Abstract: A software programmable fuse cell which reduces or eliminates static power consumption is disclosed. The programmable fuse cell can be operated in programmable and non-programmable operating modes. Depending on the operating mode, the fuse cell output is determined by the actual state of the fuse or which fuse state the fuse cell is simulating. To reduce static power consumption, a latch is used to store the actual or simulated fuse state.

Abstract: An apparatus and associated method are provided to improve the programming of anti-fuse devices in an integrated circuit. A programming circuit capable of programming a plurality of anti-fuse devices in parallel permits a state-changing voltage to be applied to multiple anti-fuses substantially simultaneously using a common control signal.

Abstract: The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link.

Abstract: An antifuse structure for improved programming efficiency is disclosed wherein the antifuse structure including a first node providing a first voltage, a plurality of antifuse elements, and a plurality of first switches. The plurality of antifuse elements are commonly connected to the first node. The plurality of first switches are sequentially activated during a program mode to individually apply the first voltage to each antifuse element. The antifuse structure may include a second node to which a second voltage is provided. Each of the plurality of first switches may be coupled between the second node and a corresponding one of the plurality of antifuse elements. The antifuse structure may also include a third node to which a fuse latch is connected. A plurality of second switches may be coupled between the third node and a corresponding one of the plurality antifuse elements. The plurality of second switches may be simultaneously activated during a read mode.

Abstract: The present invention provides for the programming of an antifuse having a dielectric disposed between a plurality of conductive elements with one of the conductive elements connected to a capacitor. The antifuse is programmed to an “on” state by precharging the capacitor and then applying a programming voltage to another one of the conductive elements. This results in the breakdown of the interposed dielectric to form a conductive link between the conductive elements. Immediately, following the formation of a conductive link, the electrical energy stored in the capacitor is released through the conductive link across the dielectric. Further, the capacitor can be common to a plurality of programmable antifuses and the application of the programming voltage serves to select one of the plurality of antifuses to be ‘blown’.

Abstract: An antifuse having a dielectric disposed between a plurality of conductive elements is programmed with one of the conductive elements connected to a capacitor. The antifuse is programmed to an “on” state by precharging the capacitor and then applying a programming voltage to another one of the conductive elements. This results in the breakdown of the interposed dielectric to form a conductive link between the conductive elements. Immediately, following the formation of a conductive link, the electrical energy stored in the capacitor is released through the conductive link across the dielectric. Further, the capacitor can be common to a plurality of programmable antifuses and the application of the programming voltage serves to select one of the plurality of antifuses to be ‘blown’. This arrangement can be realized in a FET and the device can be easily integrated in the CMOS process commonly used for the manufacture of memory arrays and logic circuitry.

Abstract: The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards.

Abstract: An invention is provided for a fuse state sensing circuit that senses the state of a fuse, which is coupled between a ground rail and a fuse state sensing node. The fuse state sensing node indicates a state of the fuse when rail voltage is provided to the fuse state sensing circuit. In addition, a capacitive element is included that is coupled to the fuse state sensing node. The capacitive element is capable of providing a first amount of current to the fuse state sensing node when an initial voltage is supplied to the rail voltage. The capacitive element is further configured to stop supplying the first amount of current upon reaching a threshold voltage of the capacitive element. The fuse state sensing circuit further includes a keeper latch circuit that is coupled to the fuse state sensing node in parallel with the capacitive element. The keeper latch circuit is capable of latching the state of the fuse state sensing node.

Abstract: An apparatus and method for improving the gate oxide reliability of an antifuse circuit is provided by coupling the gate input of a protection device of the antifuse circuit to a voltage converter circuit. In a program mode, a first voltage is applied through the voltage converter circuit to the gate input of the protection device to limit the voltage passed to internal transistor devices, thus increasing their gate oxide reliability. In a normal operation mode, however, a second, lower voltage is applied through the voltage converter to the gate input of the protection device to remove the large voltage stress placed across the gate oxide of the protection device itself. The voltage converter may attenuate the first voltage to create the second voltage or it may switch its output between the first and second voltage levels.

Abstract: An antifuse structure for improved programming efficiency is disclosed wherein the antifuse structure including a first node providing a first voltage, a plurality of antifuse elements, and a plurality of first switches. The plurality of antifuse elements are commonly connected to the first node. The plurality of first switches are sequentially activated during a program mode to individually apply the first voltage to each antifuse element. The antifuse structure may include a second node to which a second voltage is provided. Each of the plurality of first switches may be coupled between the second node and a corresponding one of the plurality of antifuse elements. The antifuse structure may also include a third node to which a fuse latch is connected. A plurality of second switches may be coupled between the third node and a corresponding one of the plurality antifuse elements. The plurality of second switches may be simultaneously activated during a read mode.

Abstract: A trim bit circuit is provided that uses a cascoded differential PMOS EPROM with a fixed offset cross-coupled latch. The output sense signal is transferred by transmission gates to NMOS latched inverters. The output is buffered by another inventor. Programming is performed by a NMOS current sink that pulls the drain of the programmed (trimmed) PMOS EPROM device to ground. This places the full positive supply across the short channel trimmed device, the punchthrough inducing a trapped charge on the device. The reference (untrimmed) PMOS EPROM device is uncharged. Thus, the two PMOS EPROM transistors have unequal current. During the read mode, a replication bias voltage is induced by an external “read” power-on-reset circuit, thereby placing a few volts below positive supply on the gates of the cascode devices. This allows the Vds of the PMOS EPROM devices to increase to a little less than a volt.

Abstract: A software programmable fuse cell which reduces or eliminates static power consumption is disclosed. The programmable fuse cell includes programmable and non-programmable operating modes. Depending on the operating mode, the fuse cell output is determined by the actual state of the fuse or which fuse state the fuse cell is simulating. To reduce static power consumption, a latch is used to store the actual or simulated fuse state.

Abstract: A buried fuse reading device includes at least one buried fuse and at least one sense amplifier sensing a condition of the buried fuse. A validation circuit in the buried fuse reading device detects and indicates when output from the sense amplifier is valid.

Abstract: An anti-fuse useful in implementing redundancy in a memory utilizes a normal transistor characteristic that is generally considered undesirable in order to provide two easily detected states. The un-programmed state, which is the high impedance state, is achieved simply with a normal transistor in its non-conductive state. The programmed state, which is the low impedance state, is achieved by forcing a normal transistor to conduct current through its gate. This causes the gate dielectric to become permanently conductive. This programmed transistor then is conductive between its source and drain that is easily differentiated from the transistor that is held in its non-conductive state. The result is a fuse technology using an anti-fuse that provides for easily distinguishable programmed and un-programmed states achieved by electrical programming rather than by laser programming.

Abstract: An electrical device is disclosed, comprising electrical components forming an electrical circuit, with a trim circuit comprising two or more trim cells providing selectively removable resistances between first and second nodes in the electrical circuit. The resistance between the nodes is trimmed incrementally by application of trim signals to a single pair of terminals or pads on the device, allowing post-packaging trimming. Methods are also disclosed for selective removal of resistance between first and second nodes in a packaged electrical device.

Abstract: An anti-fuse useful in implementing redundancy in a memory utilizes a normal transistor characteristic that is generally considered undesirable in order to provide two easily detected states. The un-programmed state, which is the high impedance state, is achieved simply with a normal transistor in its nonconductive state. The programmed state, which is the low impedance state, is achieved by forcing a normal transistor to conduct current through its gate. This causes the gate dielectric to become permanently conductive. This programmed transistor then is conductive between its source and drain that is easily differentiated from the transistor that is held in its non-conductive state. The result is a fuse technology using an anti-fuse that provides for easily distinguishable programmed and un-programmed states achieved by electrical programming rather than by laser programming.

Abstract: A semiconductor integrated circuit includes a control data storage circuit (6) having nonvolatile storage devices with programmed control data and a latch circuit for holding data read out from the storage devices, and a read control circuit (7) for controlling read operations of the control data, which are built in a semiconductor chip. The control data storage circuit (6) is divided into groups (1, 2), and the read control circuit (7) generates read control signals for the groups (1, 2) at different timings, using an output of an internal potential detecting circuit 41 as the timing reference, thereby preventing the peak of power consumption from unacceptably rising during reading operations.

Abstract: An antifuse memory cell comprises a first antifuse having a first electrode and a second electrode, a second antifuse having a first electrode and a second electrode, and an MOS transistor having a gate, a source and a drain, wherein the first electrode of the first antifuse is connected to the first electrode of the second antifuse, and the drain of the MOS transistor is connected to said first electrode of the first antifuse and the first electrode of the second antifuse.

Abstract: A universal fuse latch device includes a latch circuit receiving an electrical signal for initializing the latch circuit to a first state; one or more legs connected at the latch node, with a first leg implementing a fuse type element capable of transitioning the latch from the first state to a second state; and a second leg including an anti-fuse type element, wherein the fuse latch is provided with a fuse resistance trip point to ensure adequate reading of one of the fuse and anti-fuse type elements. The universal fuse latch device may be part of a programmable fuse bank including a plurality of information fuse latches for storing redundancy information in a memory system and capable of being simultaneously interrogated. A master fuse control device comprising the universal fuse latch circuit is programmed in accordance with a priority of legs to be interrogated in the information fuse latches.

Abstract: A method and apparatus are provided for laser fuseblow protection in transistors, such as silicon-on-insulator (SOI) transistors. The transistors are connected to a fuse. A pair of diodes are connected in series between a high supply and ground. A common connection of the series connected pair of diodes is connected to a common connection of the fuse and transistors. A charge is shunted to the high supply or ground by the pair of diodes with a first voltage a set value above the high supply and a second voltage a set value below the ground. A pair of protection diodes are provided on each side of the fuse with transistors. The transistors are either connected to one side of the fuse or to both sides of the fuse.

Abstract: An antifuse memory cell comprises a first antifuse having a first electrode and a second electrode, a second antifuse having a first electrode and a second electrode, and an MOS transistor having a gate, a source and a drain, wherein the first electrode of the first antifuse is connected to the first electrode of the second antifuse, and the drain of the MOS transistor is connected to said first electrode of the first antifuse and the first electrode of the second antifuse.

Abstract: Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.

Abstract: An integrated circuit has a programmable element with an electrical interconnect resistance that can be varied by programming. An evaluation circuit for the evaluation of the electrical interconnect resistance is connected to the programmable element. The electrical interconnect resistance of the programmable element is read out and evaluated by the evaluation circuit. With a trimming circuit, connected to the evaluation circuit, an operating point of the evaluation circuit is adjusted in dependence on the electrical interconnect resistance that has been read out by the evaluation circuit. In this way, a state of the programmable element can be read out and evaluated largely independently of technological fluctuations.

Abstract: Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.

Abstract: A synchronous semiconductor device having a delay locked loop capable of adjusting phase offset between an external clock signal and an internal clock signal after a packaging process is completed is disclosed. The disclosed synchronous semiconductor device may include a replica delay for replicating delay time of an internal circuit and a delay controller for controlling the replicated delay time.

Abstract: The present invention provides for evaluating a programmable anti-fuse element. For a programmable transistor anti-fuse, the gate of the anti-fuse is precharged with a predetermined voltage and/or current and the anti-fuse is subsequently evaluated. In one embodiment a precharge voltage sufficient to turn ON a transistor is provided to the gate. Here, an intact (unblown) transistor remains ON over a period of time and a damaged (blown) transistor dissipates the charge voltage and turns OFF. The status of the transistor is subsequently determined by evaluating the resistance between the drain and source. A high resistance indicates a blown condition and a low resistance indicates an unblown condition. In another embodiment, a small current is provided to the gate in which the small current is greater than a leakage current for an intact transistor and is less than a leakage current for a damaged transistor.

Abstract: A fuse circuit configuration is described wherein a compensation capacitor counteracts a parasitic capacitor. The parasitic capacitor occurs between a connection point of a switching transistor and a fuse and ground. The compensation capacitor is connected to an evaluation circuit. In this manner, the negative effects caused by the parasitic capacitor are compensated for.

Abstract: A configurable electronic circuit having configuration nodes is provided. Each of the configuration nodes is coupled to corresponding first circuitry that is non-modifiable during configuration and second circuitry that is modifiable during the configuration. The non-modifiable first circuitry selectively imposes one of at least a first potential and a second potential on the configuration node prior to configuration, and the modifiable second circuitry allows modification of the potential imposed on the configuration node by the non-modifiable first circuitry. In a preferred embodiment, the modifiable second circuitry includes at least one fuse that is in an intact state before configuration and that can be changed to a destroyed state after configuration. This enables a reduction in the number of fuses that have to be destroyed during the configuration of the circuit. Also provided is an information processing system that includes at least one configurable electronic circuit having configuration nodes.

Abstract: A method for programming antifuses includes applying a programming pulse having a magnitude equal to the programming potential across the conductive electrodes of the antifuse such that the more positive potential is applied to the upper electrode of the antifuse than to the lower electrode of the antifuse. The disruption of the antifuse material is sensed and the programming pulse is extended for a fixed period of time following the disruption of the antifuse material. The programming pulse is followed by a soak pulse having a polarity having a polarity such that a more negative potential is applied to the upper electrode of the antifuse than to the lower electrode of the antifuse.

Abstract: An integrated circuit is provided, in which a one-time programmable logic device disables writing to a storage device on the user side once a current is passed therethrough. The integrated circuit has a flash memory operating as a storage device to/from which writing/erasure is possible when a read/write enable port is in a high level. When a power supply is applied to an external power supply input terminal, a fuse having a polysilicon interconnection pattern is blown after a set time period by the output of a step up regulator circuit. After the fuse is blown, the input of a buffer is fixed to a low level through a resistor, so that the read/write enable port of the flash memory as the output of an AND circuit is fixed to a low level and the flash memory becomes a read only memory.

Abstract: A user-programmable resistor module includes a resistive element connected in series with first and second antifuses between an input circuit node and an output circuit node. Third and fourth antifuses are connected in series between the input circuit node and the output circuit node. A first programming transistor is connected between the common connection of the resistive element and the first antifuse and a first programming voltage node. A second programming transistor is connected between the common connection of the first and second antifuses and a fixed voltage node such as ground. A third programming transistor is connected between the input circuit node and the first programming voltage node. A fourth programming transistor is connected between the common connection of the third and fourth antifuses and a fixed voltage node such as ground.

Abstract: A software programmable fuse cell which reduces or eliminates static power consumption is disclosed. The programmable fuse cell includes programmable and non-programmable operating modes. Depending on the operating mode, the fuse cell output is determined by the actual state of the fuse or which fuse state the fuse cell is simulating. To reduce static power consumption, a latch is used to store the actual or simulated fuse state.

Abstract: A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.

Abstract: A fuse circuit according to the present invention includes fuse elements each connected to first and second nodes, a sense circuit for sensing a difference of currents flowing through the fuse elements, and an amplifier circuit for amplifying voltages of the first and second nodes with rail-to-rail voltages, respectively. By this configuration, the resistor difference of the fuse elements is sensed by a current difference, thus whether a fuse element is programmed is exactly sensed regardless of capacitive parasitic loading of the respective nodes.

Abstract: A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.

Abstract: An on-chip parallel/load, serial-shift shift register stores information bits for one or more chip parameters. The bits are represented by fuses that are connected to respective input terminals of the shift register. When the chip is not in test mode (TM), the fuses are electrically connected to respective cells of the shift register, and the output of the shift register is electrically isolated from an output buffer. When the chip is put into test mode, the electrical connections between the fuses and the shift register bits are broken, leaving the fuse information isolated in the shift register. The test mode also connects the output of the shift register to the output buffer and the output of the first shift register bit is seen on the output pin. The rest of the shift register information bits are serially shifted out of the shift register by toggling the CEB pin.

Abstract: An antifuse circuit includes a capacitor and a detector. The capacitor is formed using standard MOS processes in a well. The gate serves as one electrode and the well serving as another electrode of the capacitor. The antifuse is programmed by externally provided radiation that can rupture the gate oxide so that the gate and well can contact each other. The gate and well form a PN junction, transforming the capacitor into a diode. The diode provides the conductive path of the programmed antifuse.

Abstract: A chip information output circuit including a fuse box, capable of reducing a layout area without affecting input capacitance, is provided. The chip information output circuit includes a plurality of fuse blocks for generating different outputs according to whether a fuse is cut and a pipeline circuit for receiving a plurality of signals, which are output in parallel from the respective fuse blocks, and serially outputting the plurality of signals. Each of the fuse blocks includes a plurality of fuse boxes for generating output signals, the levels of which are either a high or low logic level according to whether the fuses included therein are cut, wherein the respective fuse boxes are enabled in response to the respective control signals and the output lines of the fuse boxes are wired by an OR operation. The pipeline circuit includes a plurality of serially connected latch units for latching signals output from the fuse blocks and outputting the latched signals.

Abstract: An enhanced fuse circuit is discussed that advances redundancy techniques in integrated circuits. The enhanced fuse circuit uses a single nonvolatile fuse and a latch that is coupled at a desired time. One embodiment of the invention discusses a fuse circuit that includes a volatile latch and a nonvolatile fuse. The nonvolatile fuse adapts to operate with a voltage supply greater than about 1.65 volts. The voltage supply is boosted at a desired time to a predetermined level and for a predetermined duration so that the nonvolatile fuse transfers its data to the volatile latch.

Abstract: An integrated circuit die includes a bond pad connected to first and second input buffers in the die through laser fuses. In one operating configuration of the die, the die uses the first input buffer but does not use the second input buffer, so the laser fuse between the bond pad and the second input buffer is blown. In another operating configuration of the die, the die uses the second input buffer but does not use the first input buffer, so the laser fuse between the bond pad and the first input buffer is blown. As a result, the capacitive load on the bond pad is similar to the capacitive load on similar bond pads in the die connected to only one input buffer in the die. Thus, signals propagate into all the bond pads at about the same improved speed.

Abstract: An input circuit having one or more individual signature circuits connected in parallel between an input line and an voltage node in a semiconductor device and an individual signature circuit are provided. The individual signature circuits are isolated from an input/output port to which a high frequency signal is applied so that the input/output port of the semiconductor device can operate at high speed. The signature circuits are provided for an input/output port to which a relatively low frequency signal is applied. An individual signature circuit includes an indexer and a selector connected in series between the voltage node and the input line. The selector includes two terminals which are electrically short-circuited or snapped in response to a control signal, and the indexer includes one or more voltage reducing devices connected in series between input and output terminals of the indexer and signature fuses each of which is connected in parallel to corresponding one of the voltage reducing devices.