Abstract: An apparatus may include a transient voltage suppression (TVS) device array coupled to a first input terminal and a second input terminal; and a linear regulator module having a pair of inputs connected to a respective pair of outputs of the TVS device array, wherein the TVS device array includes at least one TVS diode is connected between a first output and second output of the pair of outputs to generate a first clamping voltage signal, and wherein the linear regulator module is configured to generate a second clamping voltage signal having a second clamping voltage independent of a first clamping voltage of the first clamping voltage signal received from the TVS device array.

Abstract: An electro-optical device includes one unit circuit provided corresponding to an intersection between one scanning line and one data line, another unit circuit provided corresponding to an intersection between the one scanning line and another data line or an intersection between another scanning line and the one data line or an intersection between another scanning line and another data line, and an electro-optical element configured to be driven by using the one unit circuit or the another unit circuit.

Abstract: A metal oxide semiconductor (MOS) varactor includes a first diffusion region of a first polarity and a second diffusion region of the first polarity on a semiconductor substrate. The MOS varactor further includes a channel between the first diffusion region and the second diffusion region on the semiconductor substrate. The channel has a surface dopant concentration less than 4e1017.

Abstract: A display driving method, a display panel and a manufacturing method thereof, and a display apparatus are provided. The display driving method comprises: driving a display area of a display panel by using at least two data driving circuits (101); driving a part of display area of the display panel by each of the data driving circuits (102); and splicing display areas driven by respective data driving circuits as an entire display area (103). In the display driving method, the display area of the display panel is driven for display by using a plurality of data driving circuits. In this way, the display area driven by each of the data driving circuits is relatively small, and then a difference value of a distance from the data driving circuit to respective columns of sub-pixels within the driven display area is relatively small, so that the resulted difference of luminance is weakened.

Abstract: A radio frequency amplifier comprises a transistor, a transformer and a variable capacitor. The transistor has an input terminal, an output terminal and a control terminal. The transformer has a first coil conductor and a second coil conductor. The first coil conductor magnetically couples to the second coil conductor. The second coil conductor connects to the control terminal. The first coil conductor connects to the input terminal. The variable capacitor connects in parallel with the second coil conductor. An integrated circuit using the radio frequency amplifier is also introduced.

Abstract: A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.

Abstract: A system and method is provided to control a purge valve during an unsafe condition associated with a cryopump. An electronic controller may be used to control the opening and closing of one or more purge valves during the unsafe condition. The purge valve can be a cryo-purge valve or exhaust purge valve. The purge valve can be a normally open valve. The electronic controller can release the normally open valve in response to the unsafe condition. The electronic controller can delay its response to the unsafe condition for a safe period of time. Attempts from other systems to control these valves during unsafe conditions can be preempted during unsafe conditions. A user can be inhibited from manually controlling the purge valve during unsafe conditions. A power failure recovery routine may be initiated in response to a restoration of power. The power failure recovery routine can respond to an unsafe condition even if the power failure recovery routine has been manually turned off by a user.

Abstract: A method for acquiring signals such as signals representative of the state of contacts (C1-Cn) of a motor vehicle, on communication ports (P1-Pn), which can be configured either in input mode or in output mode, of an electronic unit (1), called a computer, of the motor vehicle, according to which method the signals are acquired periodically by the alternation of time intervals of acquisition of the signals with standby time intervals. This method consists in configuring each communication port (P1-Pn) in input mode during the acquisition time intervals, and in level 0 output mode during the standby time intervals.

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a plurality of through silicon vias (TSVs) configured to provide paths via which digital signals are transmitted or received; at least one redundant TSV configured to provide a path via which a digital signal to be transmitted or received via a failed TSV with a defect among the plurality of TSVs is transmitted or received; a digital-to-analog converter (DAC) configured to convert a digital signal transmitted via the at least one redundant TSV into an analog signal; an analog-to-digital converter (ADC) configured to convert an analog signal received via the at least one redundant TSV into a digital signal; and a multilevel modulator configured to perform multilevel modulation on a digital signal transmitted via the at least one redundant TSV.

Abstract: A driving circuit includes: an input terminal; an output terminal; a first transistor having a source electrode coupled to the input terminal, a drain electrode coupled to the output terminal, and a gate electrode; a second transistor having a source electrode, a drain electrode, and a gate electrode respectively coupled to the source electrode, the drain electrode, and the gate electrode of the first transistor; a first capacitor having a first electrode coupled to the input terminal and a second electrode coupled to the output terminal; and a second capacitor coupled in parallel with the first capacitor and having a first electrode coupled to the first electrode of the first capacitor and a second electrode that is floated.

Abstract: A semiconductor system including a semiconductor integrated circuit or a semiconductor chip, and a method of driving the semiconductor system are described. The semiconductor integrated circuit includes a plurality of semiconductor chips, at least one first chip through via suitable for penetrating through the plurality of semiconductor chips and interfacing a source ID code between the plurality of semiconductor chips, a plurality of second chip through vias suitable for penetrating through the plurality of semiconductor chips and interfacing a plurality of chip selection signals between the plurality of semiconductor chips, wherein the semiconductor chip uses one of chip selection signals as an internal chip selection signal in response to a chip ID code by selecting one of a unique ID code for the semiconductor chip and an alternative ID code for a preset semiconductor chip when the semiconductor chip fails.

Abstract: Each of a plurality of redundantly formed semiconductor circuits integrally has a monitor transistor and is energized by being supplied with an enable signal. A monitor circuit associated with each semiconductor circuit detects a collector current of the monitor transistor and, when the collector current is less than a predetermined threshold value, outputs an alarm signal. A variation predicting circuit calculates the rate of change per unit time with respect to the collector current. An order determining circuit stores the identification numbers of the semiconductor circuits into an order determination register in descending order of the rate of change. The order determination register initially outputs the front identification number, and thereafter outputs the respective following identification number each time a respective one of the monitor circuits outputs an alarm signal.

Abstract: A power management device of a touchable control system includes a boost circuit, a storage circuit, a detection circuit and a loading circuit. The boost circuit has an output terminal and generates an output voltage. The storage circuit electrically connects to the output terminal of the boost circuit and stores the output voltage. The detection circuit electrically connects to the storage circuit so as to detect the output voltage. The loading circuit electrically connects or disconnects to the output terminal of the boost circuit according to a predetermined value of the output voltage.

Abstract: A multi-chip package having a plurality of slice chips coupled through a through-via, at least one slice chip may include an input unit suitable for receiving a slice activation signal, and outputting the slice activation signal to the through-via in response to a slice identification corresponding to the slice chip, a first output unit suitable for outputting the activation signal transferred through the through-via to an internal circuit of the slice chip in response to the corresponding slice identification, and a second output unit suitable for selectively outputting the activation signal transferred through the through-via to the internal circuit of the slice chip in a predetermined activation mode for the multi-chip package.

Abstract: The invention pertains to a logic circuit device comprising at least one digital input furnished with a fuse (FUS) being, in the closed state, suitable for applying an electrical input voltage of the logic circuit corresponding to a first logic state from among the logic states 0 and 1, and, in the definitive open state, suitable for applying an electrical input voltage of the logic circuit corresponding to the second logic state from among the logic states 0 and 1, said fuse (FUS) being suitable for being placed definitively in the second logic state by injection of a current greater than a threshold current (CS).

Abstract: The interference-compensated sensor for detecting an object located in a detection area in a contactless manner, particularly a rain sensor, is provided with a first and a second measuring channel each having a control device and an output, wherein both measuring channels are substantially identical. The sensor further comprises a main subtractor having an output for outputting the difference of the signals at the outputs of the measuring channels. The sensor is provided with a controller unit having an input that is connected to the output of the main subtractor and with an output for outputting a controller signal, by means of which the two measuring channels can be controlled in such a way that the signal at the output of the main subtractor can be controlled to zero. By means of the magnitude of the signal at the output of the controller, it can be determined if an object is located in the detection area.

Abstract: In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.

Abstract: A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation.

Abstract: An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of ?bumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the ?bumps as a faulty ?bump, and store a first value that corresponds with the identified faulty ?bump in the first memory.

Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison.

Abstract: An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of ?bumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the ?bumps as a faulty ?bump, and store a first value that corresponds with the identified faulty ?bump in the first memory.

Abstract: Managing reliability of a circuit that includes a plurality of duplicate components, with less than all of the components being active at any time during circuit operation, where reliability is managed by operating, by the circuit, with a first set of components that includes a predefined number of components; selecting, without altering circuit performance and in accordance with a circuit reliability protocol, a second set of components with which to operate, including activating an inactive component and deactivating an active component of the first set of components; and operating, by the circuit, with the second set of components.

Abstract: A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming voltage to the programming sensing node, and a transferring unit configured to transfer the value of the programming sensing node in response to the sensing result of the sensing unit.

Abstract: A redundancy circuit includes a plurality of block address lines, a first fuse array storing a first data, a plurality of first local lines configured to supply a verification voltage to the first fuse array in response to a signal of a corresponding line among the plurality of block address lines, a second fuse array storing a second data, a plurality of second local lines configured to supply the verification voltage to the second fuse array in response to a signal of a corresponding line among the plurality of block address lines, and a plurality of verification lines configured to check the first data of the first fuse array and the second data of the second fuse array, wherein the plurality of verification lines are shared by the first fuse array and the second fuse array and are disposed between the first fuse array and the second fuse array.

Abstract: A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.

Abstract: Each of APRM units equipped for each of the diversity channels has printed circuit boards having circuit patterns thereon and a circuit description elements installed on the printed circuit board. The circuit description elements are FPGA elements manufactured by mutually different providers for example and implemented an electric circuit described in a hardware description language by a configuration tool. The circuit description elements can be implemented mutually different descriptions of the electric circuit, or can be implemented the electric circuit by mutually different configuration tools. Also, the printed circuit boards for the diversity channels can be different from each other.

Abstract: A display device includes a rescue circuit line structure having a first conductive pattern, a second conductive pattern and a dielectric layer. The first conductive pattern is adapted to electrically interconnect a first circuit element and a second circuit element, wherein the first conductive pattern has an open. Neither of the first and second conductive patterns is used as a data line or a scan line. The dielectric layer is located on the open and disposed between the first conductive pattern and the second conductive pattern.

Abstract: In one embodiment, a redundancy circuit may include a comparison unit configured to record a first repair address through fuse cutting, compare a comparison address with the first repair address, and output a comparison result signal; a first fuse enable unit configured to output a first fuse enable signal for repairing the first repair address; a second fuse enable unit configured to output a second fuse enable signal for repairing a second repair address; a first determination unit configured to output a first repair determination signal in response to receipt of the first fuse enable signal and the comparison result signal; and a second determination unit configured to output a second repair determination signal in response to receipt of an inverted signal of a value of the comparison result signal corresponding to the certain bit, remaining bits, and the second fuse enable signal.

Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison.

Abstract: The present invention is directed to improve reliably of an on-chip redundancy system by preventing influence of a physical failure exerted on an entire semiconductor chip. A comparator measure for comparing outputs of an on-chip redundancy system is mounted on a semiconductor chip different from the on-chip redundancy system. The another semiconductor chip is, preferably, mounted on a semiconductor chip on which a power source circuit for supplying power to the on-chip redundancy system redundantly having the comparing function in the chip, a driver circuit for driving an output circuit, and the like are mounted. With the configuration, the influence of a failure occurring in the on-chip redundancy system can be prevented from being exerted on the comparator measure.

Abstract: A comparator circuit for comparing outputs of an on-chip redundant system is mounted on a second semiconductor chip that is separate from the on-chip redundant system. The second semiconductor chip which preferably contains a power source circuit for supplying power to the on-chip redundant system, a driver circuit for driving an output circuit, and the like are mounted. With this configuration, the influence of a failure occurring in the on-chip redundancy system can be prevented from being exerted on the comparator measure.

Abstract: A shift register array includes a plurality of first shift registers, a second shift register, a first connection line, a second connection line, and a third connection line. A signal output terminal of each first shift register overlaps the first connection line and the third connection line without electric connection. The first connection line is connected to a signal input terminal of the second shift register. The second connection line is connected to a signal output terminal of the second shift register, and establishes a plurality of electric connection paths. When one of the first shift registers malfunctions, the corresponding connection points and overlapping points are cut or connected so that the malfunctioned first shift register can be replaced by the second shift register.

Abstract: A pre-emphasis circuit to emphasize edges of transmission data is controlled in correspondence with the result of analysis of the transmission data.

Abstract: A display driver includes: a first memory circuit for storing a line of pixels constituting an image; a second memory circuit for storing pixels of the immediately previous line; an output terminal pair switch circuit which outputs voltages each corresponding to a value of a pixel stored in the first memory circuit to a plurality of output terminals respectively corresponding to the pixels; and an inter-terminal load determination circuit for determining, for every pair of selected columns of pixels constituting the image, whether or not a short circuit is to be established between two of the plurality of output terminals which respectively correspond to the two selected columns based on values of at least three out of four pixels belonging to the two selected columns which are stored in the first and second memory circuits.

Abstract: A display device includes a rescue circuit line structure having a first conductive pattern for interconnecting electrically two circuit elements. The first conductive pattern is formed with an open for electrically disconnecting the circuit elements. A dielectric layer is disposed above the first conductive pattern in such a manner to cover the open. A second conductive pattern is disposed on the dielectric layer. A melting process is conducted onto the dielectric layer to interconnect electrically the second conductive pattern and the first conductive pattern so that signals can be passed between the circuit elements.

Abstract: The present invention is directed to improve reliably of an on-chip redundancy system by preventing influence of a physical failure exerted on an entire semiconductor chip. A comparator measure for comparing outputs of an on-chip redundancy system is mounted on a semiconductor chip different from the on-chip redundancy system. The another semiconductor chip is, preferably, mounted on a semiconductor chip on which a power source circuit for supplying power to the on-chip redundancy system redundantly having the comparing function in the chip, a driver circuit for driving an output circuit, and the like are mounted. With the configuration, the influence of a failure occurring in the on-chip redundancy system can be prevented from being exerted on the comparator measure.

Abstract: A gate of a MOS transistor connected to a fuse device in series is controlled by an AND circuit connected to the same power source as the fuse device is connected, thereby pulling down one input of the AND circuit to a ground. Thus, misprogramming of the fuse device when an LSI power source is turned ON/OFF can be prevented.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a circuit that employs an anti-tamper sensor. The circuit employs an anti-tamper sensor that includes a circuit element that is responsive to a first input and to a second input. A selective coupling element couples the circuit element to the first input and is responsive to the anti-tamper sensor. The selective coupling element has a first state that allows the circuit element to operate normally when the anti-tamper sensor does not detect a tamper condition and is configured to enter a second state that causes the circuit element to become inoperable when the anti-tamper sensor detects a tamper condition. A decoy coupling element is disposed between the second input and the circuit element and has an appearance corresponding to the selective coupling element.

Abstract: An electronic device including series-connected open failure-susceptible components and re-routing assemblies for directing current through an ancillary current path to maintain operability of the series array despite an open-failed component therein. The re-routing assembly can be constituted as an ancillary circuit containing a bypass control element arranged to maintain the ancillary circuit in a non-current flow condition when none of the open failure-susceptible components has experienced open failure, and to re-route current from a main circuit around an open-failed component therein and through the ancillary circuit and back to the main circuit, to bypass the open-failed component so that all non-failed series components of the main circuit remain operative when electrically energized.

Abstract: Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors.

Abstract: A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal.

Abstract: A storage element within a circuit design is identified. The storage element is replaced with both a first storage cell and a second storage cell. The second storage cell operates as a redundant storage cell to the first storage cell. An output of the first storage cell is connected to a first input of a comparator and an output of the second storage cell is connected to a second input of the comparator. The comparator provides an error indicator. Placement of the first storage cell, the second storage cell, the comparator, and one or more intervening cells is determined. The one or more intervening cells are placed between the first storage cell and the second storage cell. An integrated circuit is created using the comparator, the first storage cell, the second storage cell, the one or more intervening cells, and the determined placement.

Abstract: Each of APRM units equipped for each of the diversity channels has printed circuit boards having circuit patterns thereon and a circuit description elements installed on the printed circuit board. The circuit description elements are FPGA elements manufactured by mutually different providers for example and implemented an electric circuit described in a hardware description language by a configuration tool. The circuit description elements can be implemented mutually different descriptions of the electric circuit, or can be implemented the electric circuit by mutually different configuration tools. Also, the printed circuit boards for the diversity channels can be different from each other.

Abstract: The invention provides an electrical fuse device comprising: a plurality of fuse cores, each having an electrical fuse element and a switching element serially connected to the electrical fuse element; a program control circuit generating a program shift signal by sequentially shifting a program control transmission signal in synchronization with an effective program clock signal and subsequently generating a program signal to be sent to each of the switching elements in the plurality of fuse cores based on program data and the program shift signal; and a program clock control circuit controlling the conducting and non-conducting states of a program clock signal in accordance with a program clock enable signal and, when the program clock signal is in a conducting state, transmitting the program clock signal to the program control circuit as the effective program clock signal.

Abstract: A binary bidirectional trimming circuit is disclosed. The trimming circuit includes: a first resistor set having 4 resistors in parallel connected and a first fuse bridged two ends thereto provide one trimming step; a second resistor set having 2 resistors in series connected and a second fuse bridged two ends thereto provide eight trimming steps; a third resistor set having 2 resistors in parallel connected and a third fuse bridged two ends thereto provide two trimming steps; a fourth resistor set having 1 resistor and a fourth fuse bridged two ends thereto provide four trimming steps; a first loading resistor; and a second loading resistor. The first resistor set, second resistor set, first loading resistor, third resistor set, the fourth resistor set, and the second loading resistor are in series connected.

Abstract: A circuit that employs an anti-tamper sensor includes a circuit element that is responsive to a first input and to a second input. A selective coupling element couples the circuit element to the first input and is responsive to the anti-tamper sensor. The selective coupling element has a first state that allows the circuit element to operate normally when the anti-tamper sensor does not detect a tamper condition and is configured to enter a second state that causes the circuit element to become inoperable when the anti-tamper sensor detects a tamper condition. A decoy coupling element is disposed between the second input and the circuit element and has an appearance corresponding to the selective coupling element. The decoy coupling element will cause the circuit element not to operate normally if the decoy coupling element has a selected physical property of the selective coupling element in the first state.

Abstract: A circuit for programming an antifuse coupled between a first node and a second node includes at least one transistor for supplying a programming potential VPP to the first node. A first transistor has a source coupled to a third node switchably coupleable between a potential of VPP/2 and ground potential, a drain, and a gate. A second transistor has a source coupled to the drain of the first transistor, a drain coupled to the second node, and a gate. Programming circuitry is coupled to the gate of the first transistor and the gate of the second transistor and configured to in a programming mode apply a potential of either zero volts or VPP/2 to the gate of the first transistor and to apply a potential of VPP/2 to the gate of the second transistor. The first and second transistors have a BVDss rating of not more than about VPP/2.

Abstract: A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal.

Abstract: An electronic device and method for commuting an electric load, including an electronic commutator controlled by a microcontroller, positively supplied at a voltage, with an outlet that may adopt at least three states and operating in a nominal mode that may be switched intentionally or by default to a failsafe mode in case of malfunction of the electronic commutation device. The electronic commutation device additionally includes a positive commuted supply greater than the voltage and connected to the microcontroller of the electronic commutation device by a resistive polarization device to carry out the function of safety barrier, and an interface device for recognizing the presence or absence of the positive commuted supply.

Abstract: A fuse sensing circuit includes a sense controller and a fuse state sensor. The sense controller includes a reference fuse and a reference sensor coupled to the reference fuse. The reference sensor generates a sample clock with a certain threshold transition characteristic in response to the assertion of a sense input by detecting a programming state of the reference fuse. The fuse state sensor includes a sample fuse, a fuse sensor coupled to the sample fuse, and a flip-flop. The sample fuse is configured to generate a data signal indicative of a programming state of the sample fuse when an enable input is asserted and the sense input is asserted. The flip-flop is configured to sample the data signal using the threshold transition characteristic on an assertion edge of the sample clock. The fuse sensing circuit may be included in an image sensor or an imaging system.