Abstract: An integrated circuit includes a first circuit section and a second circuit section, which is necessary or useful for the emulation of the first circuit section. Such an integrated circuit provides the necessary conditions which allow emulating the integrated circuit. An integrated circuit which optionally contains such a second circuit section or another second circuit section or no such circuit section can be fabricated particularly simply if exposure masks are used for fabrication that have respective patterns for fabricating a first circuit section and patterns for fabricating a second circuit section. That part of the exposure masks which serves for fabricating the second circuit section is covered during the fabrication of a first variant of the integrated circuit, and remains uncovered during the fabrication of a second variant of the integrated circuit.

Abstract: According to the present invention, a programable latch device for use in personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment programmable latch device can use both fuses and antifuses as programmable elements. The programmable latch device provides a solid digital output indicative of the state of the programmable device, and can be reliably read to provide customization and personalization of associated semiconductor devices. The preferred embodiment programable latch device includes an integrated fuse or antifuse as a programmable element in the latch device. By integrating the programmable element into the latch, device size and complexity is minimized. In particular, the number of transistors required drops considerably when compared to prior art approaches.

Abstract: A differential voltage sense circuit has a fuse placed in one upper leg of a resistance bridge while the remaining upper leg (sense leg) employs a resistor constructed of doped poly or poly silicide or constructed of the doped silicon that forms the N-well or P-well in CMOS process. The lower legs each have a switch selected from a pair of matched switches. A comparator, latch and combinational logic sense the state of the fuse in the resistance bridge and latch the state information before the switches can operate to stop the flow of current in the resistance bridge. The differential voltage sense circuit can operate at low voltage levels compatible with advanced CMOS processes.

Abstract: A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.

Abstract: An antifuse circuit provides a stabilized high voltage to an antifuse programming circuit through the use of an NC pin which is not used in the chip operation.

Abstract: A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.

Abstract: A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state. A second anti-fuse has a programmed state and an unprogrammed state and couples the first node to a second power supply when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state. The state of the programmed signal can be used to replace a primary circuit element of an integrated circuit with a redundant circuit element.

Abstract: A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.

Abstract: A redundant decoder having fuse-controlled transistor comprises as follows: a bistable circuit which outputs a pair of complementary signals; a discharging device which is turned on at an evaluating cycle to form a discharging path; a precharging device which is turned on at a precharging cycle before an evaluating cycle to provide a precharging voltage; a first pair of transistors, having first terminals coupled to the precharging voltage, first gate terminals coupled to receive pair of complementary signals whose logic values decide whether the first pair of transistors are turned on or not, and second terminals; a second pair of transistors, having third terminals coupled to the second terminals of the first pair of transistors, second gate terminals coupled to receive a pair of complementary address bit signals whose logic values decide whether the second pair of transistors are turned on or not, and fourth terminals coupled to the discharging device; and a fuse device, having a fuse which is coupled to t

Abstract: A duplex board system comprises two functionally identical processing boards, one of the boards being in an active state and the other being in a stand-by state, each of the boards generating a state signal depicting the state thereof, wherein the stand-by state board succeeds the active state board when the state of the active state board becomes deactivated; and two cancelling units, each coupled between the two boards for receiving the state signal from one of the boards, suppressing a glitch period from the state signal generated at said one of the boards, the glitch period representing an unstable signal level transition of the state signal, and outputting the glitch suppressed state signal to the other board.

Abstract: Integrated circuit devices include a comparator circuit and a fuse programmable input circuit. The fuse programmable input circuit generates first and second differential input signals at voltage levels that can be controlled through a pair of fuses. The comparator circuit generates an output signal based on the relative voltage levels exhibited by the first and second differential input signals. In particular, the output signal is driven to a first logic state when the voltage difference between the first and second differential input signals is positive and the output signal is driven to a second logic state, which is opposite the first logic state, when the voltage difference is negative. Because the comparator is responsive to the relative difference between the voltage levels of the first and second differential input signals and not the absolute magnitudes of the voltage levels, fuse remnants that may exist after the fuse programmable input circuit has been programmed (i.e.

Abstract: A semiconductor integrated circuit includes a plurality of programmable elements, each having a first terminal connected to a first power supply potential, and a second terminal. Each of a plurality of first semiconductor switching elements has a first terminal respectively connected to the second terminal of a corresponding one of the plurality of programmable elements and has a second terminal. Each of a plurality of second semiconductor switching elements has a first terminal connected in common to selected ones of the second terminals of the plurality of first semiconductor switching elements and has a second terminal connected to a second power supply potential.

Abstract: An anti-fuse programming circuit comprising a variable voltage generator for varying the level of its output voltage in response to a programming signal, a buffer for making gentle variations in the output voltage from the variable voltage generator, an operation switching part for precharging the anti-fuse programming circuit with the output voltage from the variable voltage generator to operate it, an anti-fuse connected to the operation switching part, the anti-fuse being subjected to a dielectric breakdown when it is supplied with an overcurrent, a sense signal input part for inputting a sense signal to verify a programmed state of the anti-fuse, a breakdown voltage supply part for supplying the output voltage from the variable voltage generator for the dielectric breakdown of the anti-fuse, an output part for outputting a signal indicative of the programmed state of the anti-fuse in response to the sense signal inputted by the input part, a current blocking part for blocking a current path from the break

Abstract: An anti-fuse programming circuit comprising an operation switching part for precharging the anti-fuse programming circuit with a half voltage to operate it, an anti-fuse connected to the operation switching part, the anti-fuse being subjected to a dielectric breakdown when it is supplied with an overcurrent, a sense signal input part for inputting a sense signal to verify a programmed state of the anti-fuse, a breakdown voltage supply part for supplying a source voltage for the dielectric breakdown of the anti-fuse, an output part for outputting a signal indicative of the programmed state of the anti-fuse in response to the sense signal inputted by the sense signal input part, a feedback part for feeding back the output signal from the output part strongly at low power and high speed, a current blocking part for blocking a current path from the breakdown voltage supply part to the anti-fuse in response to a control signal from the feedback part, a reverse current prevention part for blocking the flow of curre

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determines the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programming voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: A semiconductor memory device with a redundancy circuit includes a reference section, a fuse section and a latch section. The reference section includes a reference resistance and supplies a first current to the reference resistance. The fuse section includes a fuse and supplies a second current to the fuse. The second current is proportional to the first current. The latch section has a threshold and latches a fuse state data based on the threshold and a voltage drop across the fuse. The fuse state data indicates whether or not the fuse is cut.

Abstract: A redundant circuit for a semiconductor device including a fuse program means producing a control signal determining whether or not a chip is normal; a high-voltage generating means producing a first voltage or second voltage according to a control signal from the fuse program means; and an on-chip redundant decoding means driven by the first voltage or second voltage produced from the high-voltage generating means. In case that the chip is normal, the high-voltage generating means generates the first voltage, and in case that the chip fails, the high-voltage generating means produces the second voltage. The first voltage is an output voltage from the high-voltage generating means, and the second voltage is an output voltage higher than the first voltage.

Abstract: A redundancy fuse read circuit includes an external source voltage detector for detecting a voltage level of an external source voltage and generating a HIGH enable detection signal, a fuse information storage unit for generating fuse information by capacitive coupling in accordance with the HIGH enable detection signal and for sensing the fuse information, and a comparator for comparing an output signal of the fuse information storage unit and one of an internal and external address signals.

Abstract: A fault tolerant circuit arrangement includes: an input; an output; a first circuit element, a second circuit element, a third circuit element, and a fourth circuit element, provided in such a manner that the first and second circuit elements are connected in series between the input and the output to form a first series combination, and the third and fourth circuit elements are connected in series between the input and the output to form a second series combination, the first series combination being connected in parallel with the second series combination between the input and the output; and, a control element connected between an interconnection point of the first and second circuit elements and an interconnection point of the third and fourth circuit elements. The control element is switchable by a control signal between a conducting mode in which current flow is enabled between the interconnection points and a non-conducting mode in which current flow is prevented between the interconnection points.

Abstract: A fusible link circuit including a preview feature and a method for programming or calibrating therefore. The fusible link circuit includes a fusible link, including a threshold above which the fusible link will be forced to an open condition with the application of a threshold condition applied thereto and a circuit, coupled to the fusible link, including an input and an output, generating an output signal on the output in response to a signal being applied to the input, wherein the output signal provides an output state which simulates the open condition of the fusible link as a preview feature. The fusible link circuit includes the preview feature so that the output of any circuit, which must be calibrated, programmed, or have its output set to a predetermined value, can be simulated or previewed to determine whether the correct output is obtainable without destroying the fusible links.

Abstract: An array of anti-fuse cells forming rows and columns of a matrix is described. The anti-fuse cell includes an MOS capacitor connected to a source of high voltage which is capable of rendering the capacitor permanently conductive. A first voltage limiting transistor connects the free end of the MOS capacitor to a second transistor. An address decoder provides address signals to a source and gate of the second transistor within the cell. The MOS capacitor is rendered permanently conductive when the first and second transistors are rendered conductive. The high voltage is confined to the MOS capacitor, which is fused through the high current being drawn through the capacitor by the first and second transistors. Other components on the integrated circuit carrying the array of fusible cells are maintained free of any high voltage.

Abstract: In an integrated circuit having addressable primary elements and redundant elements which can be programmed to replace primary elements, a circuit and method are provided for cancelling and replacing redundant elements. A circuit is described which can be used in a memory such as a dynamic random access memory (DRAM) which uses a selectively blowable anti-fuse to disable a redundant element which was previously programmed to replace a defective primary element. The disclosure describes a method for permanently cancelling the defective redundant element and replacing the defective redundant element with another redundant element.

Abstract: A plurality of source signal lines which supplies display data of picture elements, which are sampled at a sampling gate, from a video signal line to a plurality of picture element TFTs arranged in a matrix pattern, and a plurality of gate signal lines that supplies a control signal for controlling the picture element TFTs and that intersect the source signal lines are provided to a display section. A spare wiring is formed on each source signal line or gate signal line so that the spare wiring intersects only a non-input end of each source signal line or of each gate signal line. A corrective signal supplying circuit for supplying a corrective signal of display data or a corrective signal of the control signal for controlling picture element TFTs is provided to the outside of the display section. As a result, a line breakdown can be completely corrected.

Abstract: A shift register circuit includes a plurality of shift register blocks and a plurality of connecting sections that belong to a plurality of signal shifting systems. Each of the shift register blocks includes a plurality of shift register groups, each of which belongs to the plurality of signal shifting systems. Each of the connecting sections is provided to mutually connect the shift register groups belonging to the associated signal shifting system. The plurality of shift register blocks and the plurality of connecting sections are arranged in a line in the shift register circuit. Further, the plurality of connecting sections are separated by at least two connecting section groups in that line arrangement with at least one of the shift register blocks located between the connecting section groups.

Abstract: A clock distribution system in a reliable electronic system includes a predetermined number of clock signal load circuits, each having a clock signal input terminal. A first clock signal generator has the same predetermined number of clock signal output terminals coupled to the clock signal input terminals of the clock signal load circuits. A second clock signal generator also has the same predetermined number of clock signal output terminals which are also coupled to the clock signal input terminals of the clock signal load circuits.

Abstract: A modular digital dictation system that can be easily modified to service a variable number of dictation stations and transcription stations. The modular digital dictation station comprises a central station for receiving digitized dictation signals from a network of dictation stations, storing the voice portion of the digitized dictation signals as digitized dictation segments, and routing the digitized dictation segments to a network of transcription stations. The central station includes a plurality of line interface and signal processing cards. The number of line interface and signal processing cards connected to the central station determines how many dictation stations and transcription stations the modular digital dictation station can service. The line interface cards may be removed from or connected to the central station during operations. A redundant power supply is connected to the central station to provide continuous power to the central station.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determines the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programming voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.

Abstract: A shift register has four systems of shift registers for bidirectional scans and normal/redundant lines. The respective systems of shift registers are divided into blocks, so that transmission circuits are provided therebetween. The transmission circuits form switching circuits through transfer gates. The transmission circuits receive output signals from both of the shift registers for the normal/redundant lines, and output only normal output signals to next stage shift registers in accordance with control signals.

Abstract: An embodiment of the present invention describes a redundancy repair circuit fabricated in a Static Random Access Memory (SRAM) semiconductor device, with the redundancy repair circuit comprising: a plurality of thin film transistors (TFTs); a programming pad connecting to serially connected control gates of the plurality of TFTs; the plurality of TFTs having their individual source/drain terminals connecting between substitution logic and an address multiplexer.

Abstract: A programmable hybrid fuse circuit having a laser fuse and an electrical fuse. The programmable hybrid fuse circuit includes a reference circuit, a current mirror and at programming circuit. The reference circuit generates a reference current mirror. The current mirror generates an output current in response to the reference current. The current mirror has at least one current output which is coupled to a programming circuit to receive the output current. The programming circuit includes a laser fuse and an electrical fuse coupled in a serial order such that either the laser fuse or the electrical fuse is capable of being blown during programming. The programming circuit generates an output signal having a first voltage level or a second voltage level dependent on whether one of the fuses is blown during programming.

Abstract: A zero power fuse circuit includes a latch means having two inputs, a first input being latched to ground and a second input being latched to V.sub.cc. The latch means is triggered either by a momentary contact of the first input to ground or by the momentary contact of the second input to V.sub.cc. A first embodiment includes two fuse element/capacitor pairs each coupled to one of the two inputs of the latch means. A second embodiment includes a pull-up transistor and a fuse element/capacitor pair, coupled to the first and second inputs respectively. A third embodiment includes a pull-down transistor and a fuse element/capacitor pair respectively coupled to the second and first inputs of the latch means.

Abstract: A row address detection circuit includes a fuse bank, including a plurality of fuses connected to a common node. A precharge circuit is connected to bias the common node at a supply voltage. The fuse bank is also coupled through an isolation circuit to a buffer circuit. Selected ones of the fuses are blown in a pattern corresponding to an address of a defective circuit to enable a redundant circuit to be substituted for the defective circuit. The isolation circuit allows the buffer circuit to measure the node voltage to determine if an input to a group of address select lines corresponds to the address of the defective circuit, yet isolates the buffer circuit from the common node to prevent partially blown fuses from placing an excessive load on the buffer circuit. In one embodiment, the isolation circuit is realized with a pair of transistors of opposite channel type coupled for synchronous switching to provide substantial isolation while minimizing voltage drop.

Abstract: An electrically programmable fuse element includes a fuse having a first end coupled to a data output node selectively coupled, e.g., via a PMOS pull-up transistor, to a power source voltage, e.g., Vcc or Vpp, and a second end, a bipolar transistor connected between the second end of the fuse and a reference potential (e.g., Vss), a first MOS transistor having a channel connected between the base of the bipolar transistor and the reference potential, and a gate electrode coupled to a fuse program control signal, a second MOS transistor having a channel connected between the second end of the fuse and the reference potential, and a gate electrode coupled to a read-out control signal.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determine the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programing voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: An embodiment of the present invention describes a redundancy repair circuit fabricated in a Static Random Access Memory (SRAM) semiconductor device, with the redundancy repair circuit comprising: a plurality of thin film transistors (TFTs); a programming pad connecting to serially connected control gates of the plurality of TFTs; the plurality of TFTs having their individual source/drain terminals connecting between substitution logic and an address multiplexer.

Abstract: A clock signal failure detection and recovery circuit for use in a system utilizing multiple, redundant clock signals. Multiple clock source circuits generate a clock signal and a periodic sync pulse, which in turn are manipulated to produce a clock signal present pulse and a periodic clock pulse. The periodic clock pulse associated with one clock signal will clock the circuitry which monitors a clock signal present pulse associated with a different clock signal. In this way, the absence of a clock signal present pulse can still be clocked into the monitoring circuitry when that particular clock signal has failed. Each clock signal present pulse is compared to at least two other clock signal present pulses, and upon recognition of a predetermined number of inconsistencies between the compared clock signal present pulses, a clock signal error signal will be issued.

Abstract: A redundancy passgate circuit is implemented in NMOS technology in order to provide a more rapid transmission of the transmitted signals. The circuit provides for the more rapid signal transmission by reducing the capacitance experienced by the input signals. The reduced capacitance loading is achieved at the expense of a greater layout area and a requirement for an on-chip power supply.

Abstract: A row address detection circuit includes a fuse bank, including a plurality of fuses connected to a common node. A precharge circuit is connected to bias the common node at a supply voltage. The fuse bank is also coupled through an isolation circuit to a buffer circuit. Selected ones of the fuses are blown in a pattern corresponding to an address of a defective circuit to enable a redundant circuit to be substituted for the defective circuit. The isolation circuit allows the buffer circuit to measure the node voltage to determine if an input to a group of address select lines corresponds to the address of the defective circuit, yet isolates the buffer circuit from the common node to prevent partially blown fuses from placing an excessive load on the buffer circuit. In one embodiment, the isolation circuit is realized with a pair of transistors of opposite channel type coupled for synchronous switching to provide substantial isolation while minimizing voltage drop.

Abstract: An LCD display having at least one redundant data driving circuit on a substrate that can be substituted for a defective data driving circuit on the substrate. These redundant subcircuits are exact copies of a column driving subcircuit except that some of the connecting points to the control and driving signal lines are not hardwired. That is, the connecting points are left as potential welding points. If a column driving circuit that is coupled to a particular input data line is damaged, then a redundant data driving subcircuit can be hardwired by welding the corresponding crossing points to compensate the damaged circuit. The damaged circuit is also disconnected (by using a laser cut or compatible methods) from the corresponding input data line and the internal data line as necessary.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determine the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programming voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: Fuse circuitry is presented which emulates fuse blowing in a temporary manner. As an embodiment, redundant elements of an integrated circuit may be enabled and/or tested prior to laser repair through the use of non-destructive fuse circuitry which emulates fuse blowing. An integrated circuit has a plurality of addressable elements and a plurality of redundant elements, which may be used to replace defective addressable elements. Each redundant element has a non-destructive fuse circuit associated with it which may be used to enable and/or test the redundant element prior to laser repair by emulating the blowing of a fuse contained in the non-destructive fuse circuit. The non-destructive fuse circuit is comprised of a fuse connected to a control logic element, such as an inverter, wherein the control logic element is in turn controlled by a test signal. Emulation of blowing the fuse or not blowing the fuse is accomplished by the logic level of the test signal.

Abstract: There is disclosed a semiconductor memory device comprising a plurality of blocks in which memory cells are respectively arranged on a plurality of normal rows and one spare row. Each block includes a plurality of normal row selection lines for selecting any one of the normal rows, and one spare row selection line for instead selecting the spare row in the case where any one of the normal rows is defective. The device further comprises non-selection circuit elements provided for every normal row selection line, and being such that when a corresponding normal row is defective, the non-selection circuit element allows that defective normal row selection line to be brought into non-selective state; and a selector adapted so that when the normal rows in a corresponding block are all in non-selective state, the selector allows the spare row selection line to be brought into selective state. Also, with respect to a column direction, a circuit configuration similar to the above may be provided.

Abstract: In a microcircuit device such as a memory chip, where a bank of fuse-controlled latch pulse routing-circuits are used to program redundant circuits or other programming options with every memory cycle or multiple thereof, the amount of current drawn by every fuse-control circuit is reduced by controlling each bank of circuits with a bank-enabling, fuse-programmed circuit between the latch pulse source and the bank of fuse-controlled programming circuits, and by adding a second fuse into each programming circuit; whereby, the bank of programing circuits can be enabled by alternately blowing one of two fuses in the bank-enabling circuit, and each programming logic can set by alternately blowing one of its pair of fuses thus cutting off any current path through the programming circuit regardless of the programming state of the circuit.

Abstract: To provide a type of semiconductor memory device characterized by the fact that the redundancy for the defective memory of defective bits is increased and the area occupied by the redundant memory address decoder on the chip is minimized, thereby reducing the cost of the semiconductor memory device. It has multiple fuse decoders which are commonly connected to the address bus and are programmed for the different addresses, and it has a redundant address decoder which detects coincidence/uncoincidence between the outputs of the two decoders and generates a redundant address coincidence signal, so as to increase the efficiency in repairing the defective memory.

Abstract: A pulse signal generator includes a first delay device for delaying an input pulse signal and converting the input signal into a first intermediate signal. A power supply voltage detector detects a power supply voltage and outputs a signal representative thereof. A second delay device serves to delay the first intermediate signal and to convert the first intermediate signal into a second intermediate signal in response to the output signal from the power supply voltage detector. A logic OR operation is executed between the first and second intermediate signals, and an output signal is generated in response to the first and second intermediate signals. The output signal has a pulse width, which is greater than a pulse width of the input signal when the power supply voltage lies in a predetermined range.

Abstract: A plurality of address transition detecting circuits incorporated in a semiconductor memory device monitors address bits to see whether or not at least one address bits is changed in logic level for producing an address transition signal from the output signals of the respective address transition detecting circuits, and a plurality of charging transistors coupled in parallel between a power voltage line and a decoding line are respectively gated by the output signals of the address transition detecting circuits for charging the decoding line so that a decoding circuit quickly determines whether or not the stored address is matched with the address represented by the address bits for replacing a defective row of regular memory cells with a row of redundant memory cells.

Abstract: A latch output driver including an output driver circuit having a pull-up transistor and a pull-down transistor connected in series, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage. The latch controlled output driver also includes a first latch circuit having an output connected to the gate of the pull-up transistor and a second latch circuit having an output connected to the gate of the pull-down transistor. A control circuit is connected to the first and second latches, wherein the control circuit may selectively disable and enable the latch controlled output driver in response to a control signal. A driver output is connected between the pull-up and pull-down transistors, wherein the output driver is in an open state when the latch controlled output driver is disabled by the control circuit.

Abstract: An embodiment of the present invention describes a redundancy repair circuit fabricated in a Static Random Access Memory (SRAM) semiconductor device, with the redundancy repair circuit comprising: a plurality of thin film transistors (TFTs); a programming pad connecting to serially connected control gates of the plurality of TFTs; the plurality of TFTs having their individual source/drain terminals connecting between substitution logic and an address multiplexer.

Abstract: A fuse-programmable control circuit has a master control circuit with a first fusible link that controls the feeding of power to a fuse-programmable memory. If output of signals from the fuse-programmable memory is not required, the first fusible link is cut. If output of signals from the fuse-programmable memory is required, the first fusible link is left uncut and the fuse-programmable memory is programmed by cutting one fusible link in each of a number of pairs of fusible links. In either case, no current can flow through the fuse-programmable control circuit.