Abstract: A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.

Abstract: Disclosed is a SOMA circuit having a positive input and a negative input, and which ensures that a difference of the current pulses coming from these inputs is taken and a current pulse is transmitted to an output when this difference value exceeds a threshold value.

Abstract: Josephson junction based logic devices and methods for their use are described. An example Josephson junction based logic device includes a two-input OR/AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide single-flux-quantum (SFQ) pulses. The OA2 gate also includes first plurality of inductors coupled between the first input node and one of: a first output node or a second output node. The OA2 gate additionally includes a second plurality of inductors coupled between the second input node and one of: the first or the second output nodes. The OA2 gate also includes Josephson junctions coupled between a common node and one of: the first or the second input node, or the first or the second output node.

Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line.

Abstract: A superconducting controller for a superconducting qubit to execute high fidelity quantum gates using magnetic flux drive. The controller comprises: an inductance forming an inductive loop and configured to be inductively coupled to a qubit with a small mutual inductance; a pulse shaping circuit configured to apply a current pulse with a predefined shape across the inductance. The pulse shaping circuit comprises: a superconducting circuit configured to output single flux quanta (SFQ) pulses and a digital counter circuit configured to produce the shape of the current (magnetic flux) pulse by controlling the number of SFQ pulses applied to the inductive loop by incrementing or decrementing the current across the inductance by one SFQ pulse at a time.

Abstract: Systems and techniques that facilitate enabling transfer of a quantum state between a quantum device and a microwave resonator of a microwave optical transducer. In various embodiments, a system can comprise a quantum device, a microwave optical transducer including a microwave resonator, and a coherent interconnect. In various embodiments, the coherent interconnect can be between the quantum device and the microwave optical transducer that can enable bi-directional transfer of a quantum state between the quantum device and the microwave resonator. In various embodiments, the microwave optical transducer can be separately packaged from the quantum device. With various embodiments, the coherent interconnect can be a superconducting coaxial cable.

Abstract: Methods, systems and apparatus for resetting a qubit. In one aspect, an apparatus includes a qubit, wherein the state of the qubit occupies a plurality of levels comprising two computational levels and one or more non-computational levels; a resonator that operates at a resonator frequency; control electronics that control a frequency of the qubit such that during a reset operation the qubit frequency is adjusted from a holding frequency that is lower than the resonator frequency to an idling frequency that is higher than the resonator frequency, and during the adjustment a first derivative of the qubit frequency at a first time is positive, at a second time that occurs after the first time is zero, and at a third time that occurs after the second time is positive, where the qubit frequency achieves the idling frequency at a fourth time that occurs after the third time.

Abstract: Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate an epitaxial Josephson junction transmon device are provided. According to an embodiment, a device can comprise a substrate. The device can further comprise an epitaxial Josephson junction transmon device coupled to the substrate. According to an embodiment, a device can comprise an epitaxial Josephson junction transmon device coupled to a substrate. The device can further comprise a tuning gate coupled to the substrate and formed across the epitaxial Josephson junction transmon device. According to an embodiment, a device can comprise a first superconducting region and a second superconducting region formed on a substrate. The device can further comprise an epitaxial Josephson junction tunneling channel coupled to the first superconducting region and the second superconducting region.

Abstract: The present disclosure describes techniques for optimizing two-qubit gates performance in a quantum circuit of a quantum computing system. A quantum computing system selects, from qubits in the quantum circuit, a pair of target qubits on which to perform a quantum gate operation. The quantum computing system selects, from the plurality of qubits, a second plurality of qubits on which to introduce an intentional noise. The intentional noise is applied to the second plurality of qubits via a numerical optimizer. An optimized frequency is determined based on the applied intentional noise. The quantum gate operation is performed by modifying the pair of target qubits frequency to the optimized frequency.

Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor layer and a superconductor layer. The superconductor layer is arranged over an edge of the semiconductor layer so as to enable energy level hybridisation between the semiconductor layer and the superconductor layer. The semiconductor layer is arranged in a sandwich structure between first and second insulating layers, each insulating layer being in contact with a respective opposed face of the semiconductor layer. This configuration may allow for good control over the geometry of the semiconductor layer and may improve tolerance to manufacturing variations. The device may be useful in a quantum computer. Also provided is a method of manufacturing the device, and a method of inducing topological behaviour in the device.

Abstract: A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.

Abstract: Aspects of the present disclosure relate generally to systems and methods for use in the implementation and/or operation of quantum information processing (QIP) systems, and more particularly, to techniques for removing or correcting for translation errors between a programmed strength and an applied strength of quantum gates. A method is described that includes determining, for each quantum gate in a quantum operation, a non-linearity between an applied strength of a laser beam used for the respective quantum gate and a programmed strength intended to be applied by the laser beam for the respective quantum gate. The method further includes linearizing the non-linearity for each quantum gate and storing linearization information in memory. Moreover, the method includes applying the linearization information to correct for the non-linearity when implementing each quantum gate as part of the quantum operation. A system is also described that is configured to implement the method described above.

Abstract: An electronic component is formed by a semiconductor component or a semiconductor-like structure having gate electrode assemblies, for reading out the quantum state of a qubit in a quantum dot. The electronic component comprises a substrate having a two-dimensional electron gas or electron hole gas. Electrical contacts connect the gate electrode assemblies to voltage sources. The gate electrode assemblies have gate electrodes, which are arranged on a surface of the electronic component, for producing potential wells in the substrate.

Abstract: Disclosed are a method and an apparatus for constructing a quantum circuit corresponding to a linear function. The method includes: adding an independent variable of a target linear function on a first qubit; obtaining a second qubit for outputting the target linear function, adding a parametric quantum logic gate acting on the second qubit, and controlling the parametric quantum logic gate by using the first qubit; and determining a parameter value of the parametric quantum logic gate based on the target linear function, to obtain a quantum circuit corresponding to the target linear function.

Abstract: A parameter calibration method is provided. The parameter calibration method includes: obtaining a control parameter to be calibrated; determining a simulation running error corresponding to a quantum chip; determining calibration data corresponding to the control parameter to be calibrated based on the simulation running error; and obtaining a calibrated control parameter by calibrating the control parameter to be calibrated based on the calibration data, wherein the calibrated control parameter is used for controlling operation of the quantum chip.

Abstract: A device includes a die stack including a first die including a quantum circuit and a second die including an electronic circuit. The second die and the first die face each other. The device also includes a first interconnect between the quantum circuit and the electronic circuit and a second interconnect between the quantum circuit and the electronic circuit.

Abstract: Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.

Abstract: A silicon-based quantum device is provided. The device comprises: a first metallic structure (501); a second metallic structure (502) laterally separated from the first metallic structure; and an L-shaped elongate channel (520) defined by the separation between the first and second metallic structures; wherein the elongate channel has a vertex (505) connecting two elongate parts of the elongate channel. The device further comprises: a third metallic structure (518), mediator gate, positioned in the elongate channel; a fourth metallic structure (531) forming a first barrier gate, arranged at a first end of the third metallic structure; and a fifth metallic structure (532) forming a second barrier gate arranged at a second end of the third metallic structure. The first, second, third, fourth and fifth metallic structures are configured for connection to first, second, third, fourth and fifth electric potentials respectively.

Abstract: A quantum circuit includes a first qubit and a second qubit. A bus resonator transmission line is coupled between the first qubit and the second qubit. A readout bus is coupled to the first qubit. A switch is coupled to the bus resonator transmission line between the first qubit and the second qubit.

Abstract: In an aspect, the present disclosure provides a superconducting circuit including: a ground plane including a superconducting member; a plurality of superconducting parts surrounded by a non-conductive part with space from the ground plane, each of the plurality of superconducting parts including four coupling ports each configured to enable the superconducting part to interact with another superconducting part; a superconducting quantum interference device configured to set a resonance frequency of a first superconducting part included in the plurality of superconducting parts; and a multilevel wiring line configured to form, in cooperation with the ground plane, a superconducting loop surrounding the superconducting quantum interference device, in which the superconducting quantum interference device is disposed, in an area inside the superconducting loop, at a place where a magnetic field generated by a current from a bias line for the first superconducting part is applied.

Abstract: A device including a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions; wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

Abstract: Systems and techniques that facilitate multi-resonant couplers for preserving ZX interaction while reducing ZZ interaction are provided. In various embodiments, a first qubit can have a first operational frequency and a second qubit can have a second operational frequency, and a multi-resonant architecture can couple the first qubit to the second qubit. In various embodiments, the multi-resonant architecture can comprise a first resonator and a second resonator. In various cases, the first resonator can capacitively couple the first qubit to the second qubit, and a second resonator can capacitively couple the first qubit to the second qubit. In various aspects, the first resonator and the second resonator can be in parallel.

Abstract: Processor elements are disclosed herein. A processor element comprises a silicon layer. The processor element further comprises a dielectric layer disposed upon and forming an interface with the silicon layer. The processor element further comprises a conductive via in contact with the dielectric layer, the conductive via comprising a metallic portion having an interface end closest to the dielectric layer and a distal end. A cross-sectional area of the interface end of the metallic portion of the conductive via is less than or equal to 100 nm by 100 nm. In use, the application of a bias potential to the distal end of the conductive via induces a quantum dot at the interface between the dielectric layer and the silicon layer, the quantum dot for confining one or more electrons or holes in the silicon layer. Methods are also described herein.

Abstract: The various embodiments described herein include methods, devices, and systems for operating superconducting circuitry. In one aspect, a programmable circuit includes: (1) a superconducting component arranged in a multi-dimensional array of alternating narrow and wide portions, the superconducting component having an input terminal at a first end and an output terminal at a second end opposite of the first end; and (2) control circuitry coupled to the narrow portions of the superconducting component, the control circuitry configured to transition the narrow portions between superconducting and non-superconducting states. In some implementations, the superconducting component and the control circuitry are formed on different layers of the programmable circuit.

Abstract: Superconducting output amplifiers with interstage filters and related methods are described. An example superconducting output amplifier includes a first superconducting output amplifier stage and a second superconducting output amplifier stage. The superconducting output amplifier may further include a first terminal for receiving a first single flux quantum (SFQ) pulse train and coupling the SFQ pulse train to each of the first superconducting output amplifier stage and the second superconducting output amplifier stage. The superconducting output amplifier may further include an interstage filter comprising a damped Josephson junction (JJ) coupled between the first superconducting output amplifier stage and the second superconducting output amplifier stage, where the interstage filter is arranged to reduce distortion in an output voltage waveform generated by the superconducting output amplifier in response to at least the first SFQ pulse train.

Abstract: A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.

Abstract: A spin qubit quantum device including: a data qubit and a measurement qubit made in a semiconducting layer and coupled to each other by a tunnel junction made in the semiconducting layer, each of which comprising a quantum dot and a control gate; an inductor coupled to the gate of one of the qubits or to another gate capacitively coupled to one of the qubits, the inductor, and a capacitor formed by said gate forming an LC circuit; a first input terminal coupled to the LC circuit and receiving a periodic control voltage of frequency fr substantially equal to the resonant frequency of the LC circuit; a voltage amplifier comprising an input coupled to the gate to which the inductor is coupled; an output terminal coupled to an output of the amplifier.

Abstract: This electromagnetic wave detector that detects electromagnetic waves by performing photoelectric conversion includes: a substrate; an insulating layer that is provided on the substrate; a graphene layer that is provided on the insulating layer; a pair of electrodes, which are provided on the insulating layer, and which are connected to both ends of the graphene layer, respectively; and a contact layer that is provided such that the contact layer is in contact with the graphene layer. The contact layer is formed of a material having a polar group, and a charge is formed in the graphene layer by having the contact layer in contact with the graphene layer.

Abstract: Devices and/or computer-implemented methods to facilitate a cross-resonance operation in a dispersive regime of a qubit frequency space are provided. According to an embodiment, a device can comprise a first qubit having a first operating frequency and a first anharmonicity. The device can further comprise a second qubit that couples to the first qubit to perform a cross-resonance operation. The second qubit having a second operating frequency and a second anharmonicity. A detuning between the first operating frequency and the second operating frequency is larger than the first anharmonicity and the second anharmonicity.

Abstract: A signal amplifier is distributed between first and second IC devices and includes a low-power input stage disposed within the first IC device, a bias-current source disposed within the second IC device and an output stage disposed within the second IC device. The output stage includes a resistance disposed within the second IC device and having a first terminal coupled to a drain terminal of a transistor within the input stage via a first signaling line that extends between the first and second IC devices.

Abstract: An reciprocal quantum logic (RQL) gate circuit has an input stage having logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and an amplifying output stage comprising a JTL to deliver an output signal. The input stage includes two or more storage loops, at least two being associated each with a logical input, each comprising an input Josephson junction (JJ), a storage inductor, and a logical decision JJ, the logical decision JJ being common to all the storage loops associated with the logical inputs and being configured to trigger based on biasing provided by one or more currents stored in the storage loops and a bias signal provided to the circuit. The output stage asserts an output based on the triggering of the logical decision JJ.

Abstract: The invention relates to a power supply unit for the provision of at least one switchable power output, having at least one power input UIN, at least one voltage measuring device that monitors the voltage at the at least one power input UIN, wherein, if the input voltage falls below a defined threshold Uthres or if the change in the input voltage UIN per unit of time rises above a defined threshold ?Uthres/?t, the power output/power outputs is/are switched off and the input voltage is then measured at a first timepoint t1, and, after a first predetermined time (td1) (S240), the input voltage U is measured again at a second timepoint t2, and if the input voltage at the second timepoint is greater than the input voltage at the first timepoint, it is assumed that a short circuit is present at at least one power output.

Abstract: A connecting structure includes: a Si substrate; a nanocarbon material formed above the Si substrate; and an electrode electrically connected to the nanocarbon material, wherein a molecular material having a doping function is inserted between the Si substrate and the nanocarbon material. With this configuration, a highly-reliable connecting structure and a method for manufacturing the same are obtained which realize, even though using the nanocarbon material, a sufficiently low contact resistance between the nanocarbon material and the electrode.

Abstract: A current-limiting and power-flow control device according to the present invention includes a superconducting current-limiting element including a superconductor, a series capacitor, and a parallel circuit. The series capacitor is connected in series with the superconducting current-limiting element. The parallel circuit includes a reactor connected in parallel with a series circuit including the superconducting current-limiting element and the series capacitor. Accordingly, overcurrent at the time of occurrence of a fault causes transition of the superconductor of the superconducting current-limiting element to the normal conducting state, and thus causes autonomous current-limiting operation of the superconducting current-limiting element. Thus, application of an excessive load across the terminals of the series capacitor due to the aforementioned fault can surely be prevented.

Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.

Abstract: Neuronal networks of electronic neurons interconnected via electronic synapses with synaptic weight normalization. The synaptic weights are based on learning rules for the neuronal network, such that a synaptic weight for a synapse determines the effect of a spiking source neuron on a target neuron connected via the synapse. Each synaptic weight is maintained within a predetermined range by performing synaptic weight normalization for neural network stability.

Abstract: A device and a method of thermal management. In one embodiment, the device includes an integrated circuit, including: (1) a conductive region configured to be connected to a voltage source, (2) a transistor having a semiconductor channel with a controllable conductivity and (3) first and second conducting leads connecting to respective first and second ends of said channel, wherein a charge in the conductive region is configured to substantially raise an electrical potential energy of conduction charge carriers in the semiconductor channel and portions of said leads are located where an electric field produced by said charge is substantially weaker than near the semiconductor channel.

Abstract: The method for cancellation of low frequency noise in a magneto-resistive mixed sensor (1) comprising at least a superconducting loop with at least one constriction and at least one magneto-resistive element (6) comprises a set of measuring steps with at least one measuring step being conducted with the normal running of the mixed sensor and at least another measuring step being conducted whilst an additional super-current is temporarily injected in the at least one constriction of the at least one superconducting loop of the mixed sensor (1) up to a critical super-current of the constriction so that the result of the at least another measuring step is used as a reference level of the at least one magneto-resistive element (6).

Abstract: An embodiment of a graphene device includes a layered structure, first and second electrodes, and a dopant island. The layered structure includes a conductive layer, an insulating layer, and a graphene layer. The electrodes are coupled to the graphene layer. The dopant island is coupled to an exposed surface of the graphene layer between the electrodes. An embodiment of a method of using a graphene device includes providing the graphene device. A voltage is applied to the conductive layer of the graphene device. Another embodiment of a method of using a graphene device includes providing the graphene device without the dopant island. A dopant island is placed on an exposed surface of the graphene layer between the electrodes. A voltage is applied to the conductive layer of the graphene device. A response of the dopant island to the voltage is observed.

Abstract: This invention concerns interfacing to electronic circuits or systems operating at low temperature or ultra-low temperature using complementary metal-oxide semiconductor (CMOS) technology. Low temperature in this case refers to cryogenic temperatures in particular, but not exclusively, to the 4.2 K region. Ultra-low temperatures here refers to the sub-1 K range, usually accessed using dilution refrigerator systems. The electronic circuits comprise a controller (for writing and manipulation), an observer (for readout and measurement) circuits, or both, fabricated from ultra-thin silicon-on-insulator (SOI) CMOS technology.

Abstract: A control method is proposed that controls inter-component phase difference solitons by using splitting or fusion caused by the interaction between inter-component phase difference solitons themselves, without the need for application of external energy.

Abstract: A control system architecture for quantum computing includes an array of qubits, which is divided into a plurality of sub-arrays based on a first direction and a second direction, the second direction intersecting the first direction, a plurality of control lines each coupled to a corresponding sub-array of qubits in the first direction, a plurality of enable/unenable lines each coupled to a corresponding sub-array of qubits in the second direction, a controls signal source that generates a control signal, wherein the control lines are used to apply the control signal commonly to one or more sub-arrays of qubits in the first direction, an enable/unenable signal source that generates a enable signal, wherein the enable/unenable lines are used to apply the enable signal independently to the corresponding sub-array of qubits in the second direction to set a bias point of each qubit of the corresponding sub-array of qubits in the second direction between a first position, in which the qubit is unenabled and not r

Abstract: The present invention relates to verification of a transmission margin of various transmission lines transmitting a signal such as a high-speed digital signal and ensures improved verification accuracy. A transmission margin verification apparatus according to the present invention is configured with a measurement unit (e.g., LSI tester 4, network analyzer 6, pulse generator 8, oscilloscope 10) operable to measure a transmission loss and a leading edge waveform of pseudo transmission lines (e.g., transmission lines 56, 62, 66) corresponding to a target device 44 to be verified, and a calculation unit (tester controller 12) operable to reference the transmission line loss and the leading edge waveform measured by the measurement unit, calculate a transmission waveform of the target device, and associate the transmission waveform with a mask of the target device to calculate a transmission margin of the target device.

Abstract: A superconducting switching amplifier embodying the invention includes superconductive devices responsive to input/control signals for clamping the output of the amplifier to a first voltage or to a second voltage. The amplifier includes a first set of superconducting devices serially connected between a first voltage line and an output terminal and a second set of superconducting devices serially connected between the output terminal and a second voltage line. The first set and the second set of devices are operated in a complementary fashion in response to control signals. When one of the first and second sets is driven to a superconducting (zero resistance) state the other set is driven to a resistive state. In accordance with the invention, the devices of each set are laid out in a pattern and driven in a manner to enable all the devices of each set to be driven to a selected state at substantially the same time.

Abstract: This invention concerns interfacing to electronic circuits or systems operating at low temperature or ultra-low temperature using complementary metal-oxide semiconductor (CMOS) technology. Low temperature in this case refers to cryogenic temperatures in particular, but not exclusively, to the 4.2 K region. Ultra-low temperatures here refers to the sub-1 K range, usually accessed using dilution refrigerator systems. The electronic circuits comprise a controller (for writing and manipulation), an observer (for readout and measurement) circuits, or both, fabricated from ultra-thin silicon-on-insulator (SOI) CMOS technology.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Abstract: Novel multichromophoric complexes comprising the formula R1—RA-[MC]-([RM]z-[MC])m-RA—R2 are provided. Polymeric compositions and devices comprising the same are also discussed. The complexes are characterized by a central bridging moiety comprising one or a plurality of linked conjugated macrocyclic molecules [MC] coupled to at least one inorganic moiety (R1 and/or R2) through organic linker RA. Preparation methods include metal-mediated cross-coupling techniques. The complexes can be useful in nonlinear optical devices and other optoelectronic applications.

Abstract: An anti-gate leakage programmable capacitor including at least one capacitor having a first terminal coupled to a first node and a second terminal, a second node, and a control circuit which selectively couples the second terminal of the capacitor to the second node or which drives the second terminal to the same voltage as the first node. In one embodiment, the programmable capacitor includes multiple capacitors, an amplifier having an input coupled to the first node and an output, and a switch circuit coupled to the second node, to each second terminal of each capacitor and to the amplifier output. The switch circuit selectively switches each second terminal of each capacitor between the amplifier output and the second node. The switch circuit may include pairs of switches each controlled by a corresponding select signal to selectively switch a corresponding capacitor between the reference node and the output of the amplifier.

Abstract: To obtain a superconducting driver circuit which can obtain an output voltage of several millvolts or above, can use a DC power source as a driving power source, can form no capacitance between it and a ground plane, and has a small occupation area, the superconducting driver circuit is constructed by superconducting flux quantum interference devices (SQUIDs) each constructing a closed loop having as components two superconducting junctions and an inductor. The SQUIDs share the inductors and are connected in series in three or more stages.

Abstract: A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.