Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to bypass one or more memory cells in a bypass mode of operation. The various exemplary memory storage devices can adjust, for example, pull-up or pull-down, the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. In some situations, the various exemplary memory storage devices may introduce an unwanted bias into the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. The various exemplary memory storage devices can pull-down the electronic data and/or pull-up the electronic data as the electronic data is passing through these exemplary memory storage devices in the bypass mode of operation to compensate for this unwanted bias.

Abstract: A semiconductor memory device for reducing the peak current during the read operation is provided. A flash memory of the disclosure includes a memory cell array; a plurality of charge pump circuits; and a controller controlling a timing of activating the charge pump circuits when a selected page of the memory cell array is read so that the charge pump circuits are not activated at the same timing.

Abstract: A memory cell includes a latch, two antifuse elements, and two select transistors. The latch is connected with a first node and a second node, and receives a first power voltage and a second power voltage. The latch is selectively enabled or disabled according to an enable line voltage. The first antifuse element is connected with the first node and an antifuse control line. The second antifuse element is connected with the second node and the antifuse control line. The gate terminal, the first drain/source terminal and the second drain/source terminal of the first select transistor are connected with a word line, the first node and a bit line, respectively. The gate terminal, the first drain/source terminal and the second drain/source terminal of the second select transistor are connected with the word line, the second node and an inverted bit line, respectively.

Abstract: A power converter unit comprising a rectifier arranged to receive AC input from a variable or fixed frequency AC power source and an active power filter with an adaptive control algorithm connected as a shunt between the AC input and the rectifier.

Abstract: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. The voltage regulator is enabled by a controller.

Abstract: A system and method providing power supply rejection. One embodiment provides for power supply rejection in PLL or DLL circuitry. First subcircuitry provides second subcircuitry a supply voltage which is a filtered version of power from an external source. The first subcircuitry includes a first field effect transistor and a first low pass filter coupled to receive a signal from the external power source during operation of the second subcircuitry. The filter is coupled to provide a filtered version of the power source signal to the gate of the first transistor, so that when a first source/drain region of the first transistor is connected to receive power from the external source and the gate of the first transistor receives the filtered version of the power source signal, the second source/drain region of the first transistor provides a first modified version of the power received from the external source.

Abstract: A parallel filter arrangement with at least two filters supplying current in line side sensing configuration and a number of sensors for measuring current. The sensors are used to determine the amount of current being supplied by the filters and the amount of current being supplied by a source. The filters adjust their supplied current in order to reduce or eliminate the amount of reactive or harmonic current being supplied by a source.

Abstract: A biasing circuit for an acoustic transducer is provided with: a voltage-booster stage, which supplies, on a biasing terminal, a boosted voltage for biasing a first terminal of the acoustic transducer; and filtering elements, set between the biasing terminal and the acoustic transducer, for filtering disturbances on the boosted voltage. The biasing circuit is further provided with switches, which can be actuated so as to connect the first terminal to the biasing terminal of the voltage-booster stage, directly during a start-up step of the biasing circuit, and through the filtering elements at the end of the start-up step.

Abstract: A delay lock loop includes a phase frequency detector, a loop filter, and a voltage controlled delay circuit. The phase frequency detector is used for outputting an upper switch signal or a lower switch signal according to a reference clock and a feedback clock. The loop filter includes a first capacitor, a second capacitor, and a first switch. The first capacitor is charged or discharged and the first switch is turned off during a phase tracking period. The first capacitor and the second capacitor are charged or discharged and the first switch is turned on during a phase locking period. The voltage controlled delay circuit is used for outputting the feedback clock according to the reference clock and a control voltage outputted by the loop filter.

Abstract: A D/A converter having reference node for receiving a reference voltage and together network having a network reference bus connected to the reference node by way of a first electrical connection. The converter network produces a series of reference outputs derived from the reference voltage in response to a digital input applied to the converter, with the converter network sinking a network reference current at the network reference bus which varies with the converter digital input. A reference current compensator circuit is included which provides a compensation current at the network reference bus having a magnitude which varies in response to at least a portion of the digital input, with the compensation current operating to reduce variations in current through the first electrical connection caused by changes in the digital input.

Abstract: Filter circuit includes Nth-order active filters switching circuit which switches shorting or non-shorting of active filter, and power-supply control circuit which controls such that a power supply of active filter is turned off when switching circuit shorts active filter. A receiver employing filter circuit turns off the power supply of active filter not needed when no interference wave exists within a given range from a desired frequency band. The foregoing structure allows lowering the power consumption of filter circuit.

Abstract: An apparatus and method for the dynamic detection and compensation of performance variations within an integrated circuit (IC) is provided to detect performance variations within the IC at any stage of test or operation. An arbitrary reference signal is utilized in conjunction with an internal oscillation device to establish a speed reference that may be used to characterize the IC. Dynamic detection and compensation may also be configured within a plurality of geographic locations within the IC, so that performance variations may be detected and compensated. Test data that is indicative of the IC's performance may be dynamically generated continuously, or at programmable intervals, so that performance variations caused by virtually any source may be substantially detected and compensated at any point in time of the IC's life cycle.

Abstract: A power measurement circuit and method are described. The circuit comprises: a transconductance rectifier arrangement including an input and configured to receive a periodically varying input voltage signal having an approximate 50% duty cycle; and an averaging filter for producing a time averaged DC output signal proportional to the mean square of the voltage at the input of the transconductance rectifier arrangement and representative of the average power of the input voltage signal within a range of voltages at the input.

Abstract: Techniques for adjusting the voltage across an active filter element include a controlled circuit element and a control circuit element adapted to control the voltage across the controlled circuit element to increase transient load response and to reduce power dissipation.

Abstract: A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance monitor and control circuit providing a feedback loop to the variable resistor.

Abstract: The present invention relates to verification of a transmission margin of various transmission lines transmitting a signal such as a high-speed digital signal and ensures improved verification accuracy. A transmission margin verification apparatus according to the present invention is configured with a measurement unit (e.g., LSI tester 4, network analyzer 6, pulse generator 8, oscilloscope 10) operable to measure a transmission loss and a leading edge waveform of pseudo transmission lines (e.g., transmission lines 56, 62, 66) corresponding to a target device 44 to be verified, and a calculation unit (tester controller 12) operable to reference the transmission line loss and the leading edge waveform measured by the measurement unit, calculate a transmission waveform of the target device, and associate the transmission waveform with a mask of the target device to calculate a transmission margin of the target device.

Abstract: Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.

Abstract: A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.

Abstract: Capacitive decoupling circuits and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip with a first power rail for a first no-load bias level and a ground rail. A first voltage divider is electrically coupled between the first power rail and the ground rail and has a midpoint node. A first pair of capacitors is electrically coupled between the first power rail, the midpoint node and the ground rail to provide capacitive decoupling for power delivered to the first power rail. A second power rail has a second no-load bias less than the first no-load bias. A second pair of capacitors is electrically coupled between the ground rail and the second power rail to provide capacitive decoupling for power delivered to the second power rail.

Abstract: An active filter for reducing the common mode current in a pulse width modulated drive circuit driving a load, said drive circuit comprising an a-c source, a rectifier connected to said a-c source and producing a rectified output voltage connected to a positive d-c bus and a negative d-c bus, a PWM inverter having input terminals coupled to said positive d-c bus and negative d-c bus and having a controlled a-c output, a load driven by said a-c output of said PWM inverter, a ground wire extending from said load, and a current sensor for measuring the common mode current in said drive circuit, said current sensor producing an output current related to said common mode current; said active filter comprising a first and second transistor, each having first and second main electrodes and a control electrode, and an amplifier circuit driving said transistors; said first electrode of said first and second transistor coupled to a common node, said second electrodes of said first and second transistors being coupled t

Abstract: A voltage jitter suppression circuit and a method thereof are disclosed. The circuit is utilized for alleviating the voltage jitter phenomenon of an IC. Regardless of the circuit frequency and voltage, the voltage jitter phenomenon of the circuit can be improved significantly by utilizing the present invention.

Abstract: Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.

Abstract: Techniques for adjusting the voltage across an active filter element include a controlled circuit element and a control circuit element adapted to control the voltage across the controlled circuit element to increase transient load response and to reduce power dissipation.

Abstract: A method and an apparatus for switching on a voltage supply of a voltage domain of a semiconductor circuit is disclosed. A voltage supply is connected to a supply voltage of the semiconductor circuit by means of a switchable element. The switchable element is activated in such a way that, for switching on the voltage supply of the voltage domain, a current through the switchable element rises progressively with at least one intermediate value, in particular stepwise manner.

Abstract: A current mirror with selectable filter poles provides a selected low pass filtering function to a DC bias signal generated by the current mirror. Coupled between a first MOSFET and second MOSFET of the current mirror, a low pass filter with selectable filter poles comprises a plurality of resistor-configured MOSFETs coupled to at least one capacitor-configured MOSFET to provide one of a fast settle time and improved filtering for the current mirror in one embodiment of the invention. A first resistor-configured MOSFETs, biased by logic and bias circuitry, provides a low frequency filter pole that provides an improved filtering for the current mirror. A second resistor-configured MOSFET provides a high frequency filter pole that provides a fast charge time to meet a settle time requirement.

Abstract: An active filter for reducing the common mode current in a pulse width modulated drive circuit driving a load said drive circuit comprising an a-c source, a rectifier connected to said a-c source and producing a rectified output voltage connected to a positive d-c bus and a negative d-c bus, a PWM inverter having input terminals coupled to said positive d-c bus and negative d-c bus and having a controlled a-c output, a load driven by said a-c output of said PWM inverter, a ground wire extending from said load, and a current sensor for measuring the common mode current in said drive circuit, said current sensor producing an output current related to said common mode current; said active filter comprising a first and second transistor, each having first and second main electrodes and a control electrode, and an amplifier circuit driving said transistors; said first electrode of said first and second transistor coupled to a common node, said second electrodes of said first and second transistors being coupled to

Abstract: A detection device includes a detection circuit and a reference voltage supply circuit. The detection circuit includes an amplifier circuit, a synchronous detection circuit, and a filter section. The reference voltage supply circuit includes a first supply circuit which includes a reference-voltage first-type operational amplifier and supplies an analog reference voltage to the amplifier circuit, and a second supply circuit which includes a reference-voltage second-type operational amplifier and supplies the analog reference voltage to the filter section.

Abstract: The invention is directed to a network filter that comprises at least one phase input and a protective conductor in which each phase input is connected via a filter inductance to a corresponding phase output, in which the input side of each filter inductance is connected to the protective conductor via a filter capacitor, and in which an auxiliary inductance is connected between each filter capacitor and the protective conductor, permitting the inductances in the filter to be kept small, potentially realized by simply slipping a ferrite core over a conductor.

Abstract: A voltage controlled variable capacitor, formed of a larger number of fixed capacitor segments and a corresponding number of switching elements, linearly switches on each switching element, one after the other. Several techniques are disclosed to have only a minimum number of switching stages being in the active mode-of-change at any one time with a minimum overlap. The arrangement achieves a nearly linear change of capacitance versus tuning voltage change, while resulting in high Q-factor due to the low RDSon and high RDSoff of the fully switched stages.

Abstract: There is provided a noise canceling circuit that includes a first source terminal, a second source terminal, an output terminal, a reference voltage generator for generating a reference voltage, a bias current generator for generating a bias current determining an operating current, a voltage-current generator for generating an output of a power circuit, a voltage divider for detecting a fluctuation of an output voltage at the output terminal, and an error amplifier for amplifying an error voltage between said reference voltage and an output voltage from the voltage divider.

Abstract: A current modulation filter for mitigating fluctuations in current on a power supply line due to time dependent current demands of a load circuit includes a biasing circuit for providing a source voltage reference and a quiescent current reference and a load voltage sensing circuit for providing a voltage measurement of the operating voltage of the load circuit. A current sensing circuit is electrically interposed between the power source and the load circuit. A voltage drop across the current sensing circuit is transmitted as a voltage difference to a current controller which subsequently supplies or sinks current to the power supply line so as to maintain a constant current level thereon.

Abstract: Some of the members constituting a semiconductor element are formed from ?-Si and an HSG forming process is implemented to form hemispherical polysilicon grains at some of the members formed from ?-Si. Thus, a semiconductor device that is achieved without requiring a great number of manufacturing steps such as film formation and etching, facilitates control of the individual steps and assures reliable electrical connection between the members and a method of manufacturing such a semiconductor device are provided.

Abstract: A control circuit for a MOSFET used in a synchronous rectification circuit applies a gate voltage to the MOSFET during most of a period in which a current flows in a MOSFET. As a result, conduction loss is decreased, making it possible to increase device efficiency and form a device that is compact and lightweight.

Abstract: The present invention relates to a synchronous rectifier circuit having a transformer (Ü) in single-phase center-tap connection. MOSFETs containing a body diode are used as switches. The MOSFETs are connected up in such a way that a current flows only from source to drain. The channel of the MOSFETs is always switched on if current would flow through the body diode.

Abstract: A component inaccuracy correction system has a current source capable of outputting two currents with a fixed ratio, a voltage dividing circuit formed on the integrated circuit having at least an output end capable of receiving a current of the current source to output a divided voltage, a reference voltage generator capable of receiving another current of the current source to output a reference voltage, a comparison circuit electrically connected to the output end of the voltage dividing circuit for receiving the divided voltage from the voltage dividing circuit and comparing the divided voltage to the reference voltage to create a corresponding comparison signal, and a correction circuit electrically connected to the comparison circuit for correcting component inaccuracies of the integrated circuit according to the comparison signal generated by the comparison circuit.

Abstract: In one aspect, a bias circuit includes a rectifier, a negative bias level setter, and a negative bias extractor. The rectifier has a rectifier input and a rectifier output. The rectifier is configured to produce at the rectifier output a negative rectified voltage signal from an alternating input signal applied at the rectifier input. The negative bias level setter couples to the rectifier output and provides a path for current establishing the negative rectified voltage signal produced at the rectifier output. The negative bias extractor has an extractor output and an extractor input coupled to the rectifier output. The negative bias extractor is configured to produce at the extractor output a substantially constant negative bias signal from the negative rectified voltage signal produced at the rectifier output.

Abstract: A condenser having a huge area is required to reduce a noise on LSI power supply nets (−&Dgr;VDD) of an integrated circuit because a bypass condenser can only utilize a part of accumulated electric charges. A noise of LSI power supply nets is suppressed by generating a noise of a reversed polarity (+&Dgr;VDD) to the noise on the LSI power supply nets (−&Dgr;VDD), based upon a noise reducing circuit discharging a condenser charged with a high voltage. A noise reduction effect equivalent to a bypass condenser having a large capacity is obtained even when a condenser having a small capacity is used.

Abstract: A power supply filter capable of functioning with low power supply voltages includes a resistor-capacitor circuit coupled to a power supply line and a transistor for providing power to a target circuit, such as a phase-locked loop circuit, coupled between the resistor-capacitor circuit and the power supply line. The resistor-capacitor circuit is coupled to a charge pump controller to keep the transistor in a saturation state. The charge pump controller receives at least one clock signal that is coupled to at least one capacitive circuit. The at least one capacitive circuit includes at least two capacitors in series with a biased middle node located between the at least two capacitors in order to provide immunity to time dependent dielectric breakdown, the middle node coupled to approximately half the power supply line.

Abstract: An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

Abstract: A reference voltage generator includes a voltage controlled oscillator which has fixed and accurate relationship between a frequency of an oscillation signal and a voltage supplied thereto, a reference frequency oscillator for generating a reference frequency signal of high accuracy and stability, a phase comparator for detecting a phase difference between the oscillation signal of the voltage controlled oscillator and the reference frequency signal, a low pass filter for smoothing a detection signal from the phase comparator, a gain adjust circuit for amplifying a signal from the low pass filter, a voltage adder for providing a sum of voltages from the gain adjust circuit and an offset voltage to the voltage controlled oscillator, and a phase clock loop formed by the phase comparator, low pass filter, gain adjust circuit and voltage adder to null the phase difference by regulating a control voltage applied to the voltage controlled oscillator.

Abstract: An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

Abstract: A voltage splitter circuit (100) that generates a one-half supply voltage includes a first switched operational transconductance amplifier (switched OTA) (120), a first transistor switch (110) that is controlled by a first clock signal (108) to periodically switch a first supply voltage (135) to a non-inverting input (118) of the first switched OTA, a second switched OTA (115), a second transistor switch (105) that is controlled by an inverted second clock signal (104) to periodically switch a second supply voltage (130) to a non-inverting input (114) of the second switched OTA, a commutating capacitor (112) coupled between the non-inverting input of the first switched OTA and the non-inverting input of the second switched OTA, a first filter capacitor (145) coupled to an output (121) of the first switched OTA, a second filter capacitor (140) coupled to an output (116) of the second switched OTA, and a third switched OTA (125). The first and second clock signals are non-overlapping.

Abstract: The present invention comprises an active shunt filter for filtering a power supply for noise sensitive devices. The active shunt filter includes a transistor and an op amp. A first resistor is coupled between the emitter of the transistor and a first power supply. A second resistor is coupled between the collector of the transistor and a ground. A third resistor is coupled between the base of the transistor and the output of the op amp. The output of the op amp controls the impedance of the transistor. The op amp is coupled to receive power from a second power supply. The negative input of the op amp is coupled to the emitter. The positive input of the op amp is coupled to the first power supply via a fourth resistor. A fifth resistor couples the positive input of the op amp to ground. A capacitor is also coupled between the positive input of the op amp and ground.

Abstract: A transistor bias circuit which achieves stable operation in a multistage-connected amplifier circuit or in a compound circuit is formed, for example, by a transistor amplifier and a mixer. The transistor bias circuit, which establishes the operating point of a transistor, has an input biasing circuit which is connected to a signal input terminal of the transistor and which applies a bias current to this input terminal from a power supply. The input biasing circuit has an input frequency selection unit which passes an AC input signal input to the transistor signals input terminal within a prescribed frequency band, and which attenuates an AC input signal input to the transistor signal input terminal outside the prescribed frequency band.

Abstract: An input buffer circuit for a frequency divider includes a bias circuit including a first group of diodes connected in series and to a power supply voltage terminal, at least first and second resistors connected in series to each other at a first junction, the first resistor being connected in series with the first plurality of diodes, and a second plurality of diodes connected in series, the second plurality of diodes being connected between the second resistor and a ground; an input signal terminal for receiving an input signal from a frequency divider; a reference input terminal for receiving a reference signal; an output signal terminal; a reference output terminal connected to the reference input terminal; an amplitude limiting circuit connected to and between the output signal terminal and the reference output terminal; third and fourth resistors connected in series to each other at a second junction, the third resistor being connected to the output signal terminal and the fourth resistor being connecte

Abstract: A power supply filter is constructed with a capacitive element and an active element coupled to a filtered node and an impedance coupled between the filtered node and a power supply node. The filtered node for carrying a filtered version of a power supply signal on the power supply node. The active element having electrical characteristics such that the addition of the active element to the power supply filter reduces the amount of capacitance needed from the capacitive element to achieve a desired pole frequency for a given voltage drop across the impedance element.

Abstract: An integrated circuit includes a semiconductor die and electronic circuitry elements formed therein. First and second internal power supply lines transmit first and second supply voltages to provide power for the circuitry elements. The die includes bypass circuitry to inhibit variations in the supply voltages. The bypass circuitry includes transconductance circuitry, characterized by a variable conductivity, having a first flow electrode coupled to the first supply line, a second flow electrode coupled to the second supply line, and a control electrode for controlling current flow between the flow electrodes. The conductivity of the transconductance circuitry varies in response to a voltage difference between the control electrode and the second flow electrode. Voltage amplifier circuitry has a first input terminal coupled to the first supply line and a second input terminal coupled to the second supply line.

Abstract: A sensor apparatus is capable of removing RF noise. The sensor apparatus is comprised of a first power supply line connected to a power supply terminal; a second power supply line separately branched from the first power supply line and connected thereto; an output line; and a sensor circuit unit connected to the first power supply line so as to receive power therefrom, and for detecting a condition of an article under measurement to output a detection signal to the output line. In this sensor apparatus, the sensor circuit unit includes an operational amplifier operated by accepting the power supplied from the second power supply line, which performs the detection operation; a first filter circuit is connected to the first power supply line defined from a branch point between the first power supply line and the second power supply line to the first power supply line; a second filter circuit is connected to the second power supply line; and a third filter circuit is connected to the output line.

Abstract: An adaptive active filtering method and apparatus that detects changes in noise conditions and reduces the signal propagation speed as noise conditions worsen. This active filter has a level shifting inverter, which inverts the input signal and converts the logic levels of the input signal into chip logic levels. This inverted input signal is presented at the input of a driver inverter, which once again inverts the signal. This second inversion filters out input noise, because a voltage controlled device (which is attached to the driver inverter) reduces the switching speed of this inverter as the noise condition worsen; this reduction in switching speed reduces the propagation speed and thus filters out noise.

Abstract: A semiconductor memory device having a memory cell array with a plurality of transistors (memory cells MC) disposed in a matrix form capable of electrically altering data. In writing data to a plurality of memory cells (MC), a write voltage (V.sub.pp ') is applied to the plurality of memory cells (MC) from a plurality of write circuits (7). The write voltage is generated by boosting an internal voltage (V.sub.CC) by a charge pump circuit (21). In writing data, one of the following methods is used. The plurality of write circuits (7) are sequentially activated by a write control circuit (20) at intervals of delayed timings. The operating point of each memory cell (transistor)(MC) is controlled by operating point control means so as to reduce a current. A capacitor is connected to the output side of the charge pump circuit, and a boosted write voltage is supplied via the capacitor to the write circuit.