With Specific Source Of Supply Or Bias Voltage Patents (Class 327/530)
  • Patent number: 11348502
    Abstract: The present invention of the embodiment provides a drive circuit, comprising a first group of drive circuits and a second group of drive circuits each having multiple stages of gate drive circuits connected in series, each stage of the gate drive circuits comprising a shift register outputting a first gate drive signal and a touch voltage stabilizing unit coupled to the shift register, the touch voltage stabilizing unit comprising a reference end electrically connected to a reference potential of the shift register, a first voltage stabilizing end electrically connected to the first gate drive signal, a second voltage stabilizing end outputting a second gate drive signal and a signal end electrically connected to a control signal, wherein the control signal disables the touch voltage stabilizing unit during a display period, and the control signal enables the touch voltage stabilizing unit during a touch period.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: May 31, 2022
    Assignees: AU OPTRONICS (KUNSHAN) CO., LTD., AU OPTRONICS CORPORATION
    Inventors: Tsi-Hsuan Hsu, Manman Li, Chun-Da Tu, Fu Liang Lin
  • Patent number: 11323111
    Abstract: A method of signal detection includes receiving an input voltage signal; using AC (alternate current) coupling to couple the input voltage signal into a coupled voltage signal; establishing a DC (direct current) value of the coupled voltage signal using a resistor; generating a self-mixed voltage signal by performing a self-mixing of the coupled voltage signal using a pair of cross-coupling MOS (metal oxide semiconductor) transistors; generating an output voltage by applying low-pass filtering on the self-mixed voltage signal; generating a reference voltage using a reference current terminated with a reference load; and determining a logical signal by comparing the output voltage with the reference voltage.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: May 3, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 11320526
    Abstract: A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: May 3, 2022
    Assignee: NXP USA, Inc.
    Inventors: Didier Salle, Cristian Pavao Moreira, Dominique Delbecq, Olivier Doaré, Jean-Stephane Vigier, Birama Goumballa
  • Patent number: 11235970
    Abstract: Disclosed herein is a MEMS ASIC. In some examples, the MEMS ASIC can include a MEMS, an analog front end (AFE) amplifier, an analog-to-digital converter (ADC), an overload detector, and a high-ohmic (HO) block. The HO block and the MEMS can form a high-pass filter (HPF). The impedance of the HO block can be related to the DC operating level of the AFE amplifier and the cutoff frequency of the HPF. In some examples, an overload event can occur, and the overload detector can be configured to adjust the impedance of the HO block to reduce the settling time of the MEMS ASIC. Methods of using the MEMS ASIC to reduce the settling time of the MEMS ASIC due to an overload event are disclosed herein.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: February 1, 2022
    Assignee: Apple Inc.
    Inventor: Eddie L. Ng
  • Patent number: 11228335
    Abstract: A method and apparatus capable of adjusting a signal level in a wireless communication system are provided. An electronic device includes an oscillator configured to output a local oscillator (LO) signal, a mixer configured to convert a frequency band of a first signal based on the LO signal and output a third signal, and a feedback circuit configured to output a feedback signal for adjusting a magnitude of the LO signal, wherein the mixer is further configured to adjust a magnitude of LO signal based on the feedback signal.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: January 18, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaesik Jang, Kyuhwan An, Youngchang Yoon, Kihyun Kim, Sangho Lee
  • Patent number: 11208977
    Abstract: To provide an ignition control device of an internal combustion engine capable of reducing the number of adjustment steps required for adjustment such as matching of a MOS gate voltage or the like without being affected by device variation. A detection voltage is generated on the basis of a primary current flowing through a current detection resistor having a positive temperature dependent characteristic. A reference voltage is generated by a potential difference between a base and an emitter of a first bipolar transistor circuit and a multiple type second bipolar transistor circuit in which a plurality of bipolar transistors are connected in parallel, and a resistance value of a first resistor connected to the emitter side of the plurality of the bipolar transistor circuit, on the basis of a current having a positive temperature dependent characteristic similar to the current detection resistor.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: December 28, 2021
    Assignee: HITACHI ASTEMO, LTD.
    Inventors: Masato Kita, Yoichiro Kobayashi
  • Patent number: 11126234
    Abstract: A method is provided for initializing an electronic circuit in dependence on an externally applied voltage. The electronic circuit contains a first input circuit and further circuit elements. In a first step, a first enable signal for the operation of the input circuit and a further enable signal for the operation of the further circuit elements are deactivated if the voltage falls below a first threshold. In a second step, the first enable signal for the operation of an input circuit is activated and the further enable signal for the operation of the further circuit elements is deactivated if the voltage exceeds the first threshold. This is followed by the reception, with the first input circuit, of a chip select signal for the activation of the electronic circuit and of a code word at a terminal for the command bus. The activation of the further enable signal for the operation of the further circuit elements takes place if the received chip select signal and the received code word have predetermined values.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: September 21, 2021
    Assignee: Infineon Technologies AG
    Inventors: Giacomo Curatolo, Andreas Soukup
  • Patent number: 11095092
    Abstract: The switch circuit includes a MOS transistor one end of which is coupled to a power supply line and to a control terminal of which voltage is input, a switch coupled between the power supply line and one end of the MOS transistor or one end of which is coupled to the other end of the MOS transistor, a MOS transistor coupled between an output terminal and ground potential, and a series-connected switch and constant current source coupled to a connection point between an opposite-side end of the whole series-connected MOS transistor and switch to the power supply line and the control terminal of the MOS transistor and performing adjustment to prevent current from flowing from the MOS transistor to ground potential after the switch turns on until the MOS transistor turns on.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: August 17, 2021
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Kazuki Egawa
  • Patent number: 11070747
    Abstract: Various techniques are provided for implementing a segmented focal plane array (FPA) of infrared sensors. In one example, a system includes a segmented FPA. The segmented FPA includes a top die having an array of infrared sensors (e.g., bolometers). The top die may also include a portion of a read-out integrated circuit (ROIC). The segmented FPA also includes a bottom die having at least a portion of the ROIC. The top and the bottom dies are electrically coupled via inter-die connections. Advantageously, the segmented FPA may be fabricated with a higher yield and a smaller footprint compared with conventional FPA architectures. Moreover, the segmented FPA may be fabricated using different semiconductor processes for each die.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: July 20, 2021
    Assignee: FLIR Systems, Inc.
    Inventors: Brian Simolon, Eric A. Kurth, Mark Nussmeier, Nicholas Högasten, Theodore R. Hoelter, Katrin Strandemar, Pierre Boulanger, Barbara Sharp
  • Patent number: 11017855
    Abstract: An operating method of an electronic device including a semiconductor memory, the operating method includes selecting one of a plurality of memory cells during a set operation, applying a write current having a slow quenching pattern to the selected memory cell, monitoring a cell current flowing through the selected memory cell, generating a discharge control signal corresponding to a result of the monitoring, and discharging the write current in response to the discharge control signal.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventors: Seok-Man Hong, Tae-Hoon Kim
  • Patent number: 11018227
    Abstract: A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 25, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiro Goryu, Akira Kano, Kenji Hirohata
  • Patent number: 11009902
    Abstract: Disclosed herein is an apparatus that includes a first external terminal supplied with a first power potential, a second external terminal supplied with a second power potential different from the first power potential, a first transistor connected between the first external terminal and an internal power line, a second transistor connected between the second external terminal and the internal power line, and a first circuit configured to bring the first transistor OFF during at least a first period until the second power potential is supplied after the first power potential is supplied.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ikuma Miwa, Yoshifumi Mochida
  • Patent number: 10972074
    Abstract: The disclosure relates to solid state relay circuit for switching an electrical load. The solid state relay circuit may include a relay transistor; and a driver circuit comprising a constant current source. The driver circuit is configured and arranged to switchably operate the relay transistor, and the relay transistor is configured and arranged to switchably operate the electrical load.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: April 6, 2021
    Assignee: Nexperia B.V.
    Inventors: Stefan Berglund, Soenke Habenicht, Michael Felix Konejung, Joachim Stange, Seong-Woo Bae
  • Patent number: 10930321
    Abstract: Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first voltage, a second charge pump circuit configured to provide a second voltage, a plurality of coupling circuits configured to voltage couple and current couple the first voltage and the second voltage to a common node to provide a regulated voltage, and a feedback circuit configured to regulate the first voltage and the second voltage based on the regulated voltage.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojiang Guo, Qiang Tang
  • Patent number: 10886774
    Abstract: A method for switching a power supply for low current standby operation includes deactivating a first supply connected to a first supply node, in response to activating an enable signal. A second supply is changed to a low power mode in response to activating the enable signal, wherein the second supply is connected to a second supply node. The first supply node is connected to the second supply node in response to a first voltage of the first supply node being less than or equal to a positive offset above a second voltage of the second supply node. The first supply node is disconnected from the second supply node in response to deactivating the enable signal, wherein the first supply node is disconnected at a rate preventing the first supply node from discharging below a first supply minimum voltage.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: January 5, 2021
    Assignee: NXP USA, Inc.
    Inventors: Keith Jackoski, Arif Alam
  • Patent number: 10832754
    Abstract: Methods, systems, and devices for a current monitor for a memory device are described. A memory device may monitor potential degradation of memory cells on the device by monitoring the amount of current drawn by one or more memory cells. As the memory cells degrade, the current supplied to the memory cells may change (e.g., increase due to additional leakage current. The memory device may indirectly monitor changes in the current supplied to the memory cells by monitoring a voltage of a node of a transistor that controls the amount of current supplied to the array of memory cells. The voltage at the control node may be compared to a reference voltage to determine whether the two voltages differ by a threshold amount, indicating that the memory cells are drawing more current. The memory device may output a status indicator when the voltages differ, for example, by the threshold amount.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kristen M. Hopper, Debra M. Bell, Aaron P. Boehm
  • Patent number: 10812081
    Abstract: A computer system may include circuit blocks that may operate in different operating modes. When operating in a retention mode, a voltage level of a local power supply node for a particular circuit block may be less than a voltage level of the local power supply node when the particular circuit block is operating in an active mode. An output buffer circuit may be configured to generate, when the particular circuit block is operating in retention mode, an output signal using a circuit signal generated by the particular circuit block, and a voltage level corresponding to the active mode of operation.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 20, 2020
    Assignee: Apple Inc.
    Inventors: Michael R. Seningen, Michael A. Dreesen
  • Patent number: 10784876
    Abstract: A charge pump circuit has load driven clock frequency management. The charge pump circuit includes a CCO generating a CCO output signal that has a frequency generally proportional to a feedback current, and a charge pump operated by the CCO output signal and boosting a supply voltage to produce a charge pump output voltage at an output coupled to a load. A current sensing circuit senses a load current drawn by the load and generates the feedback current as having a magnitude that varies as a function of the sensed load current if a magnitude of the load current is between a lower load current threshold and an upper load current threshold. The magnitude of the feedback current does not vary with the sensed load current if the magnitude of the sensed load current is not between the lower load current threshold and the upper load current threshold.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: September 22, 2020
    Assignee: STMicroelectronics Design and Application S.R.O.
    Inventor: Sandor Petenyi
  • Patent number: 10778019
    Abstract: A battery reverse polarity protection circuit is disclosed. The battery reverse polarity protection circuit includes a field effect transistor (FET) coupled to a control circuit. The FET is configured to transmit an input voltage from a normal-polarity-connected battery to an output terminal, and block the input voltage from a reverses polarity-connected battery to the output terminal. The control circuit is coupled to the input terminal, the output terminal, and a common terminal and is configured to detect, during transmission of the input voltage from the normal-polarity-connected battery to the output terminal, that the input voltage is less than an output voltage, indicating onset of an abnormal operating mode, and turn off the FET to prevent the output voltage from being affected by the input voltage during the abnormal operating mode.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 15, 2020
    Assignee: Connaught Electronics Ltd.
    Inventors: Noah Gagnon, Guillaume Hamard, Bernd Rabich, Dominik Lebherz
  • Patent number: 10749527
    Abstract: A level shifting circuit includes a level shifting portion configured to receive an input signal and generate an output signal, and a current adjustment circuit connected between the level shifting portion and a drive high voltage node at which a drive high voltage is applied. The current adjustment circuit is configured to adjust an amount of current provided from the drive high voltage node to the level shifting portion.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dalhee Lee, Jintae Kim, Jaeha Lee
  • Patent number: 10734074
    Abstract: An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is coupled to an element whose status is to be determined, and the first module is to receive an input current that increases over time. The second module is to perform a temporal derivative of a voltage across the element. The third module is to provide an output signal based on a current behavior of the element, according to a change in voltage as a function of a change in current.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 4, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Brent Buchanan
  • Patent number: 10672687
    Abstract: A semiconductor device includes a die pad, and a first lead integrally connected to the die pad. A second lead and a third lead are arranged laterally away from the first lead. A semiconductor element including a first lateral surface and a second lateral surface adjacent to each other and a third lateral surface located opposite to the first lateral surface and adjacent to the second lateral surface, is mounted on the die pad. A plurality of first conductive members electrically connects the at least part of a main electrode pad to the end on the die pad side of the second lead. A second conductive member connects a control electrode pad to the end on the die pad side of the third lead.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 2, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yoshisumi Kawabata
  • Patent number: 10630173
    Abstract: A negative charge pump without the need for a negative supply potential. The negative charge pump can be manufactured utilizing standard CMOS processes. The charge pump includes a first inverter, a second inverter, a charge storage and a coupling element.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 21, 2020
    Assignee: TDK CORPORATION
    Inventors: Lei Zou, Gino Rocca
  • Patent number: 10601320
    Abstract: Voltage regulators for battery operated systems are provided. In certain implementations, a voltage regulator is operable in a regulating mode and a bypass mode. In the regulating mode, an input voltage greater than a selected value can be regulated so as to yield a desired output voltage. In the bypass mode, an input voltage at or less than the selected value can be regulated so as to yield an output voltage that substantially tracks the input voltage. Such a capability of switching between two modes can provide advantageous features such as reducing the likelihood of damage in a powered circuit due to high input voltage, and extending the operating duration of a power source such as a rechargeable battery. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of operation and fabrication.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 24, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Florinel G. Balteanu, Jakub F. Pingot, Peter Harris Robert Popplewell
  • Patent number: 10483961
    Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply voltage; a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage; a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first supply voltage, and wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication; and a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Suyoung Bang, Minki Cho, Pascal Meinerzhagen, Muhammad Khellah
  • Patent number: 10461964
    Abstract: A driver circuit includes two pull-up portions coupled respectively between VDD and first and second driver output nodes and two pull-down sections coupled respectively between ground and third and fourth driver output nodes. The driver circuit is configurable as an RS485 driver or a CAN driver. The active diodes in the pull-up sections are turned off when necessary to prevent unwanted reverse currents between the first and second output nodes and VDD. The active diodes in the pull-down sections are turned off when necessary to prevent unwanted reverse current between ground and the third and fourth output nodes.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: October 29, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Alexander Cherkassky, Bruce P. Del Signore
  • Patent number: 10454471
    Abstract: A power supply switching circuit that selects one power supply potential from among a plurality of power supply potentials. This power supply switching circuit is provided with a transistor QP1 that is connected between an input node N1 and node N2 and has a back gate connected to node N1, a transistor QP2 that is connected between node N2 and output node N3 and has a back gate connected to node N3, a transistor QP3 that is connected between input node N4 and node N5 and has a back gate connected to node N4, a transistor QP4 that is connected between the node N5 and N3 and has a back gate connected to node N3, and a control signal generation unit that sets a group of transistors QP1 and QP2 and a group of transistors QP3 and QP4 to a conduction state and sets the other to a non-conduction state.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 22, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hiroaki Nomizo, Hiroshi Kiya, Nobuyuki Oikawa
  • Patent number: 10382852
    Abstract: Provided is a condenser microphone circuit that can support variation in power supply voltage of a phantom power supply using a wiring system of two lines. A condenser microphone circuit includes a microphone unit, an FET, a constant current diode, a collector grounding first transistor that generates an operation power supply of the FET, a first resistor that sets base potential of the first transistor, a collector grounding second transistor that amplifies an output signal from the FET, a second resistor that sets base potential of the second transistor, and an output circuit. A base of the first transistor is connected to a source of the FET, an emitter of the first transistor is connected to a drain of the FET, a base of the second transistor is connected to the drain of the FET, an emitter of the second transistor is connected to the output circuit, and the second resistor divides voltage on a cathode side of the constant current diode.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 13, 2019
    Assignee: Audio-Technica Corporation
    Inventor: Satoshi Yoshino
  • Patent number: 10373660
    Abstract: Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hyun Yoo Lee, Kang-Yong Kim, John D. Porter
  • Patent number: 10367485
    Abstract: To provide a receiver, a communication device, and a communication method capable of restoring a signal transmitted via a non-contact transmission channel with high accuracy. A communication device has a transmission circuit that converts an input signal into a pulse, a non-contact transmission channel that has a primary side coil and a secondary side coil and transmits the pulse from the transmission circuit in a non-contact manner, a restoration circuit that restores the input signal on the basis of a reception signal corresponding to the pulse transmitted via the non-contact transmission channel, an initialization unit that initializes an output of the non-contact transmission channel, and an initialization control unit that outputs a control signal of controlling the initialization unit on the basis of the reception signal corresponding to the pulse received via the non-contact transmission channel.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: July 30, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirokazu Nagase, Koichi Takeda, Shunichi Kaeriyama
  • Patent number: 10359800
    Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 23, 2019
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: Serge Ramet, Sandrine Nicolas, Danika Perrin, Cedric Rechatin
  • Patent number: 10304524
    Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 28, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 10277176
    Abstract: A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: April 30, 2019
    Assignee: Raytheon Company
    Inventors: John P. Bettencourt, Alan J. Bielunis, Istvan Rodriguez, Zhaoyang C. Wang
  • Patent number: 10256808
    Abstract: A bandgap reference circuit includes a voltage generation circuit, a capacitor and a clamping control circuit. The voltage generation circuit is used to generate a current on an operation terminal. The capacitor includes a first terminal coupled to the operation terminal, and a second terminal coupled to a first reference voltage terminal. The clamping control circuit is coupled between the operation terminal and a second reference voltage terminal. The clamping control circuit includes a switch and a clamping unit, and is used to allow part of the current flowing through the clamping unit to the second reference voltage terminal when the switch is turned on.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: April 9, 2019
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Tien-Yun Peng
  • Patent number: 10248177
    Abstract: A processor system includes first and second regulators for regulating an adjusted supply voltage. The first and second regulators generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value by implementing first and second control loops. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply. One regulator is a global regulator while another is a local regulator found in each of the processing tiles. Processing tiles are grouped into two groups wherein one group includes tiles that may powered down to save power. Voltage rails of the two groups are selectively connected to equalize voltage levels when both groups are powered on and operating.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: April 2, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Miguel Rodriguez, Stephen Victor Kosonocky
  • Patent number: 10250996
    Abstract: An acoustic energy detection circuit can include a microphone interface circuit configured for coupling to a microphone. The microphone interface circuit is configured to intermittently activate the microphone to detect acoustic energy and convert the acoustic energy to an electrical signal. The acoustic energy detection circuit also includes a comparator circuit for receiving the electrical signal and comparing the electrical signal with a threshold signal. The comparator circuit is configured to output an output signal to indicate detection of acoustic energy.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: April 2, 2019
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Peter Holzmann
  • Patent number: 10170989
    Abstract: Methods for fabricating an integrated circuit with a voltage regulator are provided. In some implementations, a method includes forming a primary regulator on a semiconductor substrate, including fabricating a switch, fabricating an amplifier for controlling the switch, and fabricating a voltage generator for biasing the amplifier to operate the primary regulator in a bypass mode or in a regulating mode. The method further includes forming an input terminal and an output terminal of the primary regulator on the semiconductor substrate, forming a secondary regulator on the substrate, forming an input terminal and an output terminal of the secondary regulator on the semiconductor substrate, and forming an electrical connection between the output terminal of the primary regulator and the input terminal of the secondary regulator.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: January 1, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Florinel G. Balteanu, Jakub F. Pingot, Peter Harris Robert Popplewell
  • Patent number: 10168443
    Abstract: A system for interfacing an LC sensor includes a starter configured to selectively start an oscillation of the LC sensor. The system also includes an analog peak detector configured to determine a signal (Vpeak) being indicative of a peak voltage of the oscillation of the LC sensor and a detector configured to determine a state of the LC sensor as a function of the signal (Vpeak) determined by the analog peak detector.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: January 1, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Riccardo Condorelli
  • Patent number: 10163763
    Abstract: An integrated circuit package having a first die configured to sense a first physical characteristic and provide a first data signal, and a second die, wherein the first die is configured to transmit the first data signal to the second die, and the second die is configured to determine if there is an error in the first die and transmit the result to a controller.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: December 25, 2018
    Assignee: Infineon Technologies AG
    Inventors: Friedrich Rasbornig, Wolfgang Granig, Dirk Hammerschmidt, Hans-Joerg Wagner, Thomas Zettler
  • Patent number: 10157644
    Abstract: Methods of operating a voltage generation circuit, and apparatus configured to perform such methods, include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the voltage driver output to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of the voltage driver output is less than a threshold, connecting the voltage driver output to a second voltage node configured to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of the voltage driver output is greater than the threshold, and connecting the voltage driver output to a third voltage node configured to receive a third voltage less than the first voltage when the clock signal has a different logic level.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Macerola, Marco-Domenico Tiburzi, Stefano Perugini
  • Patent number: 10141925
    Abstract: A circuit for strengthening load transient response compensation is provided, including a comparator, a first MOSFET and a second MOSFET. The comparator compares a system voltage of an electronic device with a reference voltage. The first MOSFET is coupled to the comparator and a first power supply. The second MOSFET is coupled to the comparator and a second power supply of the electronic device. When an external device is connected to the electronic device such that the system voltage is lower than the reference voltage, the comparator outputs a low-level signal and the first MOSFET becomes conductive, so that the external device is powered by the first power supply.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 27, 2018
    Assignee: WISTRON CORP.
    Inventors: Chengwei Huang, Sin-Fang Wang, Yen-Hsiang Wang, Jiun-Lin Tseng, Po-Yen Huang
  • Patent number: 10056783
    Abstract: An energy harvesting circuit for use with a logic circuit includes an induction coil positioned near conductive elements of the logic circuit and configured to extract energy from the magnetic fields produced by transient currents associated with state changes within the logic circuit.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 21, 2018
    Assignee: Johnson Research & Development Co., Inc.
    Inventor: Lonnie G. Johnson
  • Patent number: 10050518
    Abstract: A power supply circuit may include a first power converter that may be configured to generate a first inner supply voltage having a first voltage level based on a first external supply voltage and to output the first inner supply voltage to a first node that is coupled to the first node, a second power converter that may be configured to generate a second inner supply voltage having the first voltage level based on a second external supply voltage and to output the second inner supply voltage to a second node that is coupled to the second node, a first diode that may include an anode coupled to the first node and a cathode coupled to the second node, and a second diode that may include an anode coupled to the second node and a cathode coupled to the first node.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 14, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoung-Taek Lim, Chung-Hyun Ryu
  • Patent number: 10033355
    Abstract: A voltage adjustment circuit includes switches connected in parallel between a circuit unit and an electric power supply line to which a first electric power supply voltage is applied, and changes the number of switches turned off, based on a comparison result between a target value and a second electric power supply voltage supplied to the circuit unit, to adjust the second electric power supply voltage. A control circuit decides an interval for increasing the number of switches turned off when the circuit unit changes to standby state, based on a leak current value of the circuit unit in standby state, a time in which the second electric power supply voltage changes from a first to a second value, the first and second values, and an electric potential difference by which the second electric power supply voltage changes when one switch switches between on and off.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: July 24, 2018
    Assignee: SOCIONEXT INC.
    Inventor: Yosuke Tsukamoto
  • Patent number: 10031544
    Abstract: A power supply voltage detection circuit can detect the power supply voltage obtained by stabilizing a power supply voltage supplied from outside and also the magnitude of the power supply voltage before being stabilized. This power supply voltage detection circuit includes a selection circuit that selects one power supply potential from among a plurality of power supply potentials including a first power supply potential supplied from outside and a second power supply potential obtained by stabilizing the first power supply potential, a variable voltage dividing circuit that divides the voltage between the power supply potential selected by the selection circuit and a reference potential by a set division ratio, a comparison voltage generation circuit that generates a comparison voltage based on a reference voltage, and a comparator that compares the voltage divided by the variable voltage dividing circuit with the comparison voltage and outputs a signal representing a comparison result.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 24, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Sachiyuki Abe
  • Patent number: 10014762
    Abstract: The invention provides a protection circuit applied in an inductive boost converter, the inductive boost converter includes a transmission circuit and a charging circuit, the protection circuit includes a detection circuit and a control circuit, an input terminal of the detection and an output terminal of the transmission circuit are connected, a first output terminal of the detection circuit and an input terminal of the charging circuit are connected, a second output terminal of the detection circuit and an input terminal of the control terminal are connected; the detection circuit detects whether an input current from the transmission circuit is a short-circuit current, if the circuit is shorted, the result will be sent to the control circuit, the control circuit cuts the connection of the charging circuit and ground, which can prevent charges stored in the charging circuit from flowing backward into the input terminal of the inductive boost converter.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: July 3, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Xianming Zhang, Dan Cao
  • Patent number: 10008614
    Abstract: A dual channel transistor includes a first gate electrode, a second gate electrode, a first gate insulation layer, a second gate insulation layer, a silicon semiconductor channel layer, and an oxide semiconductor channel layer. The first gate insulation layer is disposed on the first gate electrode. The silicon semiconductor channel layer is disposed on the first gate insulation layer. The oxide semiconductor channel layer is disposed on the silicon semiconductor channel layer. The second gate insulation layer is disposed on the oxide semiconductor channel layer. The second gate electrode is disposed on the second gate insulation layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wanxun He, Su Xing
  • Patent number: 9946276
    Abstract: A voltage regulator provides an output current at an output voltage, based on an input voltage. The voltage regulator has a pass transistor for deriving the output current. The voltage regulator contains a drive transistor forming a current mirror in conjunction with the pass transistor, such that the output current through the pass transistor is dependent on a drive current through the drive transistor. The voltage regulator comprises an auxiliary transistor arranged such that at least a fraction of the drive current through the drive transistor flows through the auxiliary transistor. The voltage regulator has amplification circuitry to set the drive current through the drive transistor depending on the output voltage and on a reference voltage. The voltage regulator further contains control circuitry to detect an indication for a dropout situation where a difference between the input voltage and the output voltage falls below a dropout voltage.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: April 17, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Ambreesh Bhattad, Frank Kronmueller, Hande Kurnaz
  • Patent number: 9933286
    Abstract: A sensor comprises a sensor element configured to provide a sensor signal representing at least one measurand detected by the sensor element, an electrical circuit configured to process the sensor signal to form a data signal, a photovoltaic cell configured to provide electrical energy for the sensor element and the electrical circuit, and a housing, in which the sensor element, the electrical circuit and the photovoltaic cell are positioned, the housing including a recess in which the photovoltaic cell is positioned, and a rim surrounding the recess and protruding beyond the photovoltaic cell. A method is also provided.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: April 3, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Ricardo Ehrenpfordt, Mathias Bruendel, Frederik Ante, Johannes Kenntner
  • Patent number: 9933800
    Abstract: A linear voltage regulator and associated integrated circuit and method are disclosed. The linear voltage regulator is operable within a plurality of predefined operational modes, and comprises a pass element configured to generate an output voltage based on a received input voltage. The linear voltage regulator further comprises an error amplifier comprising an output node coupled with a control node of the pass element. The error amplifier is configured to generate a control signal at the output node based on the output voltage and a reference voltage. The linear voltage regulator further comprises a frequency compensation circuit configured to selectively apply an impedance to the output node based on which of the predefined operational modes is selected.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 3, 2018
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Aswani Tadinada, Sivan Kumar Pandian, Kaushalendra Tripathi, Srinivasaraju Dhenuvakonda