Abstract: Resonant impedance sensing with a resonant sensor (such as LC) is based on generating a controlled negative impedance to maintain steady-state oscillation in response to changes in resonance state caused by interaction with a target. Resonant impedance sensing can include: (a) generating a controlled negative impedance at the sensor; (b) controlling the negative impedance based on a detected resonance state to substantially cancel the sensor resonant impedance, such that the sensor resonance state corresponds to steady-state oscillation, where the negative impedance is controlled by a negative impedance control loop that includes the sensor resonator as a loop filter; and (c) providing sensor response data based on the controlled negative impedance, such that the sensor response data represents a response of the sensor to the target. Thus, the response of the sensor to the target corresponds to the negative impedance required for steady-state oscillation.

Abstract: A circuit for synthesising a negative resistance, comprising first and second active devices, the first device having a control terminal connected to a first node, and the second device having a current flow terminal connected to the first node, and the first and second devices interacting with each other such that the circuit synthesises a negative resistance.

Abstract: An N-shaped nonlinear resistor circuit using floating gate MOSFETs; to realize various N-shaped characteristics that can be approximated by piecewise linear functions of third to seventh orders and further to realize N-shaped V-I characteristics that can variously change those characteristics by use of external voltages. A ?-type nonlinear resistor circuit (1) and a V-type nonlinear resistor circuit (2) using multi-input floating gate MOSFETs are connected in parallel, and the currents of the ?-type and V-type nonlinear resistor circuits are added together, thereby providing various N-shaped voltage-current characteristics.

Abstract: An integrated circuit is disclosed which includes a variety of NDR devices having different characteristics. The different NDR devices are formed to have different PVRs, different onset NDR voltages, etc. in a common substrate, by controlling various conventional processing operations, such as an implant, an anneal, an insulator film deposition, and the like.

Abstract: Chemically assembled electronic nanotechnology (CAEN) provides an alternative to using Complementary Metal Oxide Semiconductor (CMOS) for constructing circuits with feature sizes in the tens of nanometers. A molecular latch and a method using the latch that enables it to act as a state holding device, perform voltage restoration, and to provide I/O isolation is disclosed.

Abstract: An effective means and apparatus for generating a negative resistance including a circuit element that exhibits an increase in current as the applied voltage is decreased. Other embodiments of the present invention provide electronic means for improving the quality Q factor of on-chip resonators, which enables the creation of high-performance bipolar RF circuits with a minimum of external components.

Abstract: The provision of a source voltage detecting circuit suitable for integrated circuits, wherein a very simple circuit arrangement makes it possible to satisfy various characteristics required by source voltage detection and to control detection voltage in wafer process. A source voltage detecting circuit, comprising a first resistor R1, a second resistor R2 and a reference voltage source RV which are connected in series between a power source VCC and the ground GND, wherein the point of connection P1 between said first and second resistors R1, and R2 is connected to the output terminal of a negative resistance characteristic section NR, and the point of connection P2 between said second resistor R2 and the reference voltage source RV is connected to the input terminal of the negative resistance characteristic section NR.

Abstract: A high speed digital static shift register includes a series-connected pair of resonant tunneling diodes (RTDs) 22, 24 to achieve a bistable operating state. A clocked switch 20 provides the means of setting the binary state of this bistable pair. In order for one bistable pair to drive a following pair, a method of providing isolation and gain using a buffer amplifier 26 between the two pairs of RTDs is also provided. In one embodiment, the buffer amplifier comprises enhancement FET 30 and depletion load FET 28.

Abstract: A first partial circuit is formed by grounding the emitter electrode of a first negative differential resistive element, connecting the emitter electrode of a second negative differential resistive element to the collector electrode of the first negative differential resistive element, and connecting a first field-effect transistor in parallel with the first negative differential resistive element. A second partial circuit is formed by grounding the emitter electrode of a third negative differential resistive element, connecting the emitter electrode of a fourth negative differential resistive element to the collector electrode of the third negative differential resistive element, and connecting a second field-effect transistor in parallel with the third negative differential resistive element. An output from the first partial circuit is input to the input of the second partial circuit. The inversion of the output of the second partial circuit is input to the input of the first partial circuit.

Abstract: A new negative resistance circuit comprises a first N-channel enhancement FET (E-FET), an N-channel depletion FET as a load element connected to the first N-channel E-FET to form a series branch connected between negative resistance ports, and a second N-channel E-FET having source-drain path parallel to the series branch. The gate of the second N-channel E-FET is connected to the connection node between the load element and the first E-FET, while the gate electrode of the first E-FET is connected to a control port for controlling current-voltage characteristic between the negative resistance ports. The negative resistance circuit can be used in an inverter to enable the inverter to have a hysteretic function or a multivalued logic function.

Abstract: A Schmitt trigger circuit has a field effect transistor coupled between a first fixed potential and an output terminal, and a variable negative resistance circuit coupled between the output terminal and a second fixed potential; the gate of the field effect transistor and the control input of the negative resistance circuit are coupled to the input terminal of the Schmitt trigger circuit; wherein the negative resistance circuit includes a first field effect transistor coupled between the output terminal and the second fixed potential, and a gate coupled to an internal node; a second field effect transistor coupled between the internal node and the second fixed potential, and a gate coupled to the input terminal; and a third field effect transistor coupled between the first fixed potential and the internal node, and a gate coupled to the output terminal.

Abstract: A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Abstract: A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Abstract: An inverting amplifier includes a negative resistance circuit coupled between an output node and a power supply to provide a variable negative resistance in response to an input potential, and a resistance element connected between the output node and ground.

Abstract: An electronically-controlled variable propagation delay digital signal inverter comprises a digital signal inverter having an input signal port and an output signal port, and an electronically-controlled negative resistance (ECNR). The ECNR is coupled to the output port of the inverter in a configuration so as to render the propagation delay of the digital signal inverter capable of being varied by varying the resistance of the ECNR. The electronically-controlled variable propagation delay digital signal inverter may be included in a ring oscillator configuration.

Abstract: A shift register having a first bistable latching circuit operable for switching between a low voltage state and a high voltage state in response to receiving an input current and a first clock voltage pulse. A second bistable latching circuit operable for switching from said low voltage state to the high voltage state in response to receiving a switching current induced from the first bistable latching circuit and a second clock voltage pulse. A clock voltage pulse source operable for successively providing clock voltage pulses in phase sequence to the first and second bistable latching circuits.

Abstract: A series of squarer circuits each providing an ideal square law transfer character comprises at least one backward diode and a compensating resistor connected in series therewith. A second backward, diode can be included connected front to back with the one diode.