Abstract: The various embodiments described herein include methods, devices, and systems for implementing logic gates. In one aspect, a circuit includes: (1) superconducting components; (2) heat sources, each coupled to a corresponding superconducting component and configured to selectively provide heat to that component; and (3) a current source coupled to the superconducting components and configured to selectively provide: (a) a first current to bias the components such that combination of the first current and heat from any heat source causes the components to transition to a non-superconducting state; and (b) a second current to bias the components such that (i) combination of the second current and heat from each heat source causes the components to transition to the non-superconducting state, and (ii) a combination of the second current and heat from only a subset of the heat sources does not cause the components to transition to the non-superconducting state.

Abstract: A radio frequency (RF) transmission line includes a first conductive layer, a second conductive layer conductively isolated from the first conductive layer, a center conductor disposed between the first conductive layer and the second conductive layer, dielectric material disposed between the first conducive layer and the second conductive layer and at least partially surrounding the center conductor, and an RF choke element that conducts a direct current signal between the center conductor and the second conductive layer.

Abstract: Systems and methods for electrical power conversion include the provision of a full-bridge tunnel diode inverter topology which provides a balanced push-pull drive voltage and current across the entire transformer primary. Moreover, the full-bridge tunnel diode inverter may avoid operating its tunnel diodes in a high-current/high-voltage state at light loads, unlike a single-diode inverter. The disclosed principles also allow a full-bridge tunnel diode inverter topology that may avoid RF chirps in the tunnel diodes during rising or falling device ramp currents since the primary current passes through two tunnel diodes in series.

Abstract: A protection device usable with a signal measurement device to limit power level of radio frequency (RF) signals propagated to the signal measurement device can include a direct current (DC) block capacitor, a variable impedance limiter, and a detector. The variable impedance limiter includes a PIN diode electrically connected with a primary signal path of the protection device along a limiter signal path. The detector includes a Schottky detector diode and a limiting resistor electrically connected with the primary signal path along a detector signal path. The detector is configured to generate a DC bias current to adjust resistance of the variable impedance limiter in response to an RF signal.

Abstract: The invention relates to an interconnection network and an integrated circuit and a method for manufacturing the same. Furthermore, the invention relates to a method for signal transfer between semiconductor structures. The invention is characterized in that a signal of a first semiconductor structure is supplied to a transmitter, which generates from the signal a plasmon wave, and couples the latter into a waveguide. The plasmons fed through the waveguide are received by a receiver, converted to an electric signal and forwarded to a second semiconductor structure.

Abstract: The present invention relates to a SET/RESET latch circuit a Schmitt trigger circuit, and a MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. The SET/RESET latch circuit is configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied to very high speed digital circuits.

Abstract: The present invention relates to CML(Current Mode Logic)-type input driving method and tunneling diode logic using MOBILE(Monostable Nistable transition Logic Element) configuration, as kinds of very high-speed digital logic circuits. The objectives of the present invention are to improve the disadvantage of MOBILE circuit configuration that is an existing tunneling diode logic, and at the same time provide new MOBILE based logic functions. Wherein, the difficulty for input voltage adjustment is resolved by replacing the input part with a CML input driving gate, and speed problem due to transistor is resolved. Moreover, a plurality of logic functions such as inverted return-to-zero D flip-flop, non-inverted return-to-zero D flip-flop, return-to-zero OR gate, return-to-zero D flip-flop generating differential output, and optical flip-flop are implemented.

Abstract: An N-shaped nonlinear resistor circuit using floating gate MOSFETs; to realize various N-shaped characteristics that can be approximated by piecewise linear functions of third to seventh orders and further to realize N-shaped V-I characteristics that can variously change those characteristics by use of external voltages. A ?-type nonlinear resistor circuit (1) and a V-type nonlinear resistor circuit (2) using multi-input floating gate MOSFETs are connected in parallel, and the currents of the ?-type and V-type nonlinear resistor circuits are added together, thereby providing various N-shaped voltage-current characteristics.

Abstract: The present invention includes: a series circuit which has a negative differential resistance element and another negative differential resistance element that has a control terminal capable of controlling a value of an element current; a transfer gate; a latch circuit which has negative differential resistance elements connected in series; and an inverter circuit which has an FET as a drive element and a negative differential resistance element as a load element. With this, such a flip-flop can be obtained that when a clock signal is applied to a power supply terminal of the series circuit and a control terminal of the transfer gate and an input signal is supplied to the control terminal of the negative differential resistance element, an output is placed at a terminal.

Abstract: A circuit includes at least one negative differential resistance (NDR) device and at least one magnetic device having reversibly variable resistance, wherein the negative differential resistance device and the magnetic device are operatively connected so that changing the resistance of the magnetic device changes the current-voltage response characteristics of the circuit. NDR devices and magnetic devices can be arranged to form multiple value logic (MVL) cells and monostable-bistable transition logic elements (MOBILE), and these logic cells can form the components of a field programmable gate array.

Abstract: The present invention relates to an optically programmable electric generator of arbitrary time profiles, which comprises a first ultrahigh frequency triggering line (10) and a second ultrahigh frequency discharge line (12) resistively coupled, by points, the first line being triggered by a voltage transition of duration less than one nanosecond, at least one point being taken off from the first line (10) by at least one photoconductor in variable resistance mode, directly coupled to the second line, illuminated by a programmable light source (13). A resistive load is connected at the output (S) of this generator.

Abstract: A high-speed differential comparator is disclosed. The comparator (100) includes a transconductance device (102 through 112) that receives first and second input voltages (V.sub.IN and -V.sub.IN) and generates first and second currents in response to the first and second input voltages. A first resonant tunneling diode (118) conducts the first current and generates a first output voltage (V.sub.OUT1) at a first output terminal (105) in response to the first current. A second resonant tunneling diode (126) conducts the second current and generates a second output voltage (V.sub.OUT2) at a second output terminal (109) in response to the second current. The comparator responds to input voltages at high speed and may be used for high frequency signal sampling and level determination.

Abstract: A high-speed differential comparator (300) is disclosed. A transconductance device is connected to the input terminal and the first and second output terminals (305 and 309, respectively) of the comparator. The transconductance device receives an input voltage (V.sub.IN) from the input terminal and generates a current between the first and second output terminals (305 and 309) in response to the input voltage. A load is connected between the first and second output terminals. The load, which includes a resonant tunneling diode (313), conducts the current and generates a voltage difference between the first and second output terminals (305 and 309) in response to the current. The comparator responds to input voltages at high speed and may be used for high frequency signal sampling and level determination.

Abstract: A high speed digital static shift register includes a series-connected pair of resonant tunneling diodes (RTDs) 22, 24 to achieve a bistable operating state. A clocked switch 20 provides the means of setting the binary state of this bistable pair. In order for one bistable pair to drive a following pair, a method of providing isolation and gain using a buffer amplifier 26 between the two pairs of RTDs is also provided. In one embodiment, the buffer amplifier comprises enhancement FET 30 and depletion load FET 28.

Abstract: Resonant-tunneling transmission lines in the various architectures rely on discrete or continuous resonant-tunneling heterostructures to actively modify propagating logic signals. One embodiment utilizes amplification of logic signals to counteract ubiquitous losses and distortion associated with any transmission medium. Basically, the logic signal is incrementally reamplified and reshaped as it propagates along the transmission line. Another embodiment is directed to a clocking system that transmits a signal represented by a sinusoid. Then, in proximity to the logic gates or modules, the sinusoid is converted into a square wave that actually clocks the gates and other logic structures. The inventive active transmission line naturally performs this feature, thus enabling clock signal transmission over longer links coupled with sinusoid-to-square wave conversion in a limited area. Still other embodiments implement step or continuous variations in the physical width of the resonant-tunneling transmission line.

Abstract: The number of input latching comparators in a flash analog-to-digital converter is significantly reduced by merging the input latching function into exclusive OR gates used in the converter's decoding section. A latching exclusive OR gate used for this purpose employs resonant tunneling diodes as the latching devices, with hysteresis and impedance elements connected to ensure that the gate latches in a logic state that corresponds to the input analog signal. The latching logic gates operate in a current mode, enabling updated logic states to be latched in response to a periodic clock signal.

Abstract: A carrier transport media is doped with impurities or includes barrier structures within or on the carrier transport media and a sinusoidally alternating external electric field(s) with frequencies equal to the Bloch frequency divided by an integer is applied to the carrier transport media to alter the effective barriers of the impurities or barrier structures to an arbitrarily large potential compared to the zero field barrier potential. The various impurities or barrier structures are band engineered and deposited, grown or implanted in the carrier transport media and can take any form such as barrier layers in or on the transport media, laterally induced barriers, and impurities or defects in the carrier transport media. The application of time-dependent external fields across a length of nanoscale or mesoscopic structure leads to an effective renominalization of the barrier potential strengths when the frequency of the applied electric field multiplied by an integer is equal to the Bloch frequency.

Abstract: A heterojunction semiconductor device includes an unipolar transistor having, a collector layer, a base layer, a collector side barrier layer provided between the collector layer and base layer, an emitter layer, and an emitter side barrier layer provided between the base layer and the emitter layer. The emitter side barrier layer has a thickness for tunneling a carrier from the emitter and base layer and injecting the carrier into the base layer according to a predetermined voltage applied between the emitter and base layers, the base layer includes a superlattice structure. The superlattice structure includes a plurality thin barrier layers and a thin well layer for forming a mini-band through which the injected carrier can move and a mini-band gap with which the injected carrier collides.

Abstract: A flip-flop circuit which makes use of a resonant-tunneling effect is improved in that it is simplified in structure and hence in designing of a component and operates at a room temperature. The flip-flop circuit includes a bipolar transistor and a resonant-tunneling diode. The collector terminal of the bipolar transistor is connected to a voltage source, and the base terminal is connected to an input terminal of the flip-flop circuit by way of a resistor. One of a pair of terminals of the resonant-tunneling diode is grounded while the other terminal is connected to the emitter terminal of the bipolar transistor with a junction therebetween connected to an output terminal of the flip-flop circuit.

Abstract: A shift register having a first bistable latching circuit operable for switching between a low voltage state and a high voltage state in response to receiving an input current and a first clock voltage pulse. A second bistable latching circuit operable for switching from said low voltage state to the high voltage state in response to receiving a switching current induced from the first bistable latching circuit and a second clock voltage pulse. A clock voltage pulse source operable for successively providing clock voltage pulses in phase sequence to the first and second bistable latching circuits.