Abstract: A control driver circuit that includes a switching transistor coupled between a first voltage supply node and an output node of the gate, the output node coupled or couplable to a control node of the power transistor. A circuit includes an inductive element coupled between the control transistor and a second voltage supply node. The circuit is configured such that if the output node is coupled to the power transistor, and in response to the switching transistor being turned on, a current is induced within the inductive element and a voltage from the first voltage supply is provided to a control node of the power transistor to thereby turn on the power transistor. On the other hand, in response to the switching transistor being turned off, the induced current is drawn from the output node to thereby turn the power transistor off.

Abstract: A method is disclosed for controlling an IGBT component and a gate driver. An exemplary method includes producing, with two separate driver circuits, a gate voltage for controlling the IGBT component, the outputs of the driver circuits being connected to free ends of a series connection of resistive components. A location, such as a midpoint between the series connection, forms the gate voltage.

Abstract: The present invention relates to a multi-bit non-volatile memory device having a dual gate employing local charge trap and method of manufacturing the same, and an operating method for a multi-bit cell operation.

Abstract: A track and hold circuit including an input terminal V.sub.IN, a first node, a second node and a capacitor C.sub.H. A diode D connects between the first node and the input terminal V.sub.H. Circuitry coupled to the first node makes the diode conductive during track mode of operation, indicated by a clock CK being at a first state, and non-conductive during hold mode of operation, indicated by a clock CK being at a second state. A transistor Q3 is coupled between said first node and said second node. The capacitor C.sub.H is connected to said second node. The transistor Q3 is operative to charge the capacitor C.sub.H during track mode and to isolate the capacitor C.sub.H from the input terminal V.sub.IN during hold mode. Additional circuitry coupled to said transistor Q3 senses the clock shifting from said first to said second state to rapidly discharge the inherent base/emitter capacitor of the transistor Q3 to thereby cause rapid turn off of the transistor Q3.

Abstract: An integrated circuit which includes a detection circuit for detecting the condition of saturation of an output transistor (Q.sub.0) whose collector-emitter path is intended to pass an output current. A threshold circuit (A) of the detection circuit is arranged to perform a switching operation when a representative parameter of the condition of saturation crosses a given threshold. A control transistor (Q) is arranged to supply at least a part of the base current of the output transistor (Q.sub.0) and the threshold circuit (A) performs its switching operation when the value of the current passing through the collector-emitter path of the control transistor exceeds a given level.

Abstract: A voltage-to-current conversion circuit is disclosed which includes a MOS transistor of a source-grounded type having a gate connected to an input terminal, an output circuit producing an output current at an output terminal in response to a drain current of the transistor, and a control circuit maintaining the drain voltage of the transistor to such a value that has the transistor operates in a non-saturation (triode) region.