Abstract: A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; a control electrode provided inside a trench of the semiconductor part; a third electrode provided inside the trench; a diode element provided at the front surface of the semiconductor part; a resistance element provided on the front surface of the semiconductor part via an insulating film, the diode element being electrically connected to the second electrode; a first interconnect electrically connecting the diode element and the resistance element, the first interconnect being electrically connected to the third electrode; and a second interconnect electrically connecting the resistance element and the semiconductor part. The resistance element is connected in series to the diode element. The diode element is provided to have a rectifying property reverse to a current direction flowing from the resistance element to the second electrode.

Abstract: A semiconductor device includes a semiconductor body including first to fourth semiconductor layers. The second semiconductor layer of second conductivity type is provided on the first semiconductor layer of first conductivity type; the third semiconductor layer of first conductivity type is provided selectively on the second semiconductor layer; and the fourth semiconductor layer of second conductivity type is provided selectively on the second semiconductor layer. The semiconductor device further includes first and second control electrodes. The first and second control electrodes are provided inside the semiconductor body and oppose the second semiconductor layer with first and second insulating films interposed, respectively, and are arranged alternately with a third insulating layer interposed. The first control electrode contacts the third insulating layer at a first surface thereof, and the second control electrode contacts the third insulating layer at a second surface opposite to the first surface.

Abstract: Circuits and methods for generating a pulse are provided. The generating can comprise receiving at least one trigger input signal with a pulse generating circuit; generating a voltage pulse having a duration less than the avalanche time of a transistor in response to at least a portion of the at least one trigger input signal with the pulse generating circuit; transmitting the voltage pulse from the pulse generating circuit to a terminal of the transistor, the transistor constructed and arranged to be operable in an avalanche mode; and outputting an avalanche pulse from at least one terminal of the transistor in response to the voltage pulse. In some embodiments, the pulse can be transmitted with an antenna in a radar system, and a return pulse can be received and processed.

Abstract: In various embodiments a voltage regulating circuit is provided which may include a control transistor at least partially formed in an n-type substrate, and a regulating circuit including a regulating output coupled to a control region of the control transistor, wherein the regulating circuit includes at least one transistor which is formed at least one of on and in the n-type substrate.

Abstract: Disclosed is a diode. An embodiment of the diode includes a semiconductor body, a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a base region arranged between the first and second emitter regions and having a lower doping concentration than the first and second emitter regions. The diode further includes a first emitter electrode only electrically coupled to the first emitter region, a second emitter electrode in electrical contact with the second emitter region, and a control electrode arrangement including a first control electrode section, and a first dielectric layer arranged between the first control electrode section and the semiconductor body. At least one pn junction extends to the first dielectric layer or is arranged distant to the first dielectric layer by less than 250 nm.

Abstract: A detection system in which a single sensor is employed to detect an extensive range of a parameter. The output signal from the sensor is fed to the input of the electrical circuit, having a feedback loop, wherein the electrical circuit has a non-linear transfer characteristic. The non-linear transfer characteristic is achieved by changing the behavior of the feedback loop of the electrical circuit at a predetermined level of input signal. The output of the circuit has a proportional relationship with the input until the input signal reaches this predetermined value, whereupon the behaviors of the feedback loop changes and the relationship of the output to the input of the circuit changes. While the input signal is above the predetermined value, the output of the circuit has a linear but disproportionate relationship with the input at a gradient different to that when the input signal is below the predetermined value.

Abstract: A circuit design of a transistor connected as a diode, in particular to a design able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal. The circuit design includes a first pMOS transistor having a second nMOS transistor connected as a diode connected between the gate and the drain of the first transistor and a current generator connected to the gates of the two transistors. Such a circuit design is also applicable to a nMOS transistor. From a general point of view the invention is directed to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series with the gate that provides an appropriate delta of voltage.

Abstract: A bidirectional battery disconnect switch, i.e., a switch which is capable of blocking a voltage in either direction when open and conducting a current in either direction when closed, is disclosed. The switch includes a four-terminal MOSFET having no source/body short and circuitry for assuring that the body is shorted to whichever of the source/drain terminals of the MOSFET is biased at a lower voltage.

Abstract: A process and an integrated circuit are intended for obtaining an adjustable electrical resistance, in which a first voltage is applied to an integrated MOS transistor on its source, its gate and its substrate, and a second voltage is applied on its drain, the first and second voltages being able to initiate a breakdown of the MOS transistor by: avalanche of the drain/substrate junction; biasing of the parasitic bipolar transistor of the MOS transistor; irreversible breakdown of the drain/substrate junction; and shorting between the drain and the source.

Abstract: A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE<ICB according to a voltage applied across a base and emitter where IBE is the base current flowing through a base-emitter path in a forward direction, and ICB is the base current flowing through a collector-base path in a reverse direction.

Abstract: An apparatus and method for recharging a string of avalanche transistors within a pulse generator is disclosed. A plurality of amplification stages are connected in series. Each stage includes an avalanche transistor and a capacitor. A trigger signal, causes the apparatus to generate a very high voltage pulse of a very brief duration which discharges the capacitors. Charge resistors inject current into the string of avalanche transistors at various points, recharging the capacitors. The method of the present invention includes the steps of supplying current to charge resistors from a power supply; using the charge resistors to charge capacitors connected to a set of serially connected avalanche transistors; triggering the avalanche transistors; generating a high-voltage pulse from the charge stored in the capacitors; and recharging the capacitors through the charge resistors.

Abstract: An apparatus for suppressing voltage transients across a first transistor is described. The first transistor has a first terminal, a second terminal, and a gate terminal, and is characterized by an avalanche breakdown voltage rating between the first and second terminals. The cathode of a first diode is coupled to the first terminal, the first diode having a reverse breakdown voltage which is less than the avalanche breakdown voltage rating. Gate driver circuitry is provided by which the gate terminal of the first transistor is coupled to the anode of the first diode. The gate driver circuitry provides a drive signal to the gate terminal of the first transistor, and comprises a plurality of bipolar transistors. Each bipolar transistor has an anode terminal (i.e., base terminal), a p-n junction, and a cathode terminal (i.e., emitter terminal). The anode terminal of each bipolar transistor is coupled to the anode of the first diode.

Abstract: A Zener diode is used to simplify a circuit for detecting the level of an operating voltage with respect to a specified range of use. The semiconductor junction of this Zener diode is biased alternately by one voltage or another. Under these conditions, the avalanche voltage of this Zener diode changes. The operating voltage to be monitored is connected to the cathode of this Zener diode. If the monitored operating voltage is higher than the avalanche voltage of this Zener diode, the diode alternately conducts. If the operating voltage is outside this range, this diode is either permanently on or permanently off. The variations that result therefrom are detected to report whether the operating voltage is correct.

Abstract: A clamp circuit (50) for protecting a MOSFET (52) from destructive voltages includes a clamping element (56), a Zener diode (64), two current mirrors (66 and 62), a current switch (58), a reference current source (68), and a voltage detector (72). When a drain voltage of the MOSFET (52) rises above a clamping voltage of the clamp circuit (50), a clamping current exceeding a current in the current switch (58) flows through the clamping element (56) and activates the MOSFET (52). During the activation, the two current mirrors (66 and 62) generate an output current exceeding a reference current in the reference current source (68) and raise a voltage at an input terminal of the voltage detector (72). The voltage detector (72) generates a signal indicating the activation of the clamp circuit (50), thereby indicating that the clamp circuit (50) and its inductive load (74) are intact.