Abstract: A single-phase electronic power-saving device includes at least one power-saving unit. The power-saving unit includes two ceramic piece capacitors, a safe capacitor, an inductor, a SCR, a first resistor, a second resistor, a live wire and a zero line; the two ceramic piece capacitors connected in series as a whole is connected in parallel with the safe capacitor to two terminals of which are connected the anode and the cathode of SCR, respectively; the anode of SCR is also connected to one terminal of the inductor, the branch composed of the first and the second resistors connected in series is connected in parallel so that one terminal of which is connected to one terminal of the inductor and the other is connected to the cathode of SCR; the gate of SCR is connected between the first and the second resistors.

Abstract: A single-phase electronic power-saving device includes at least one power-saving unit. The power-saving unit includes two ceramic piece capacitors, a safe capacitor, an inductor, a SCR, a first resistor, a second resistor, a live wire and a zero line; the two ceramic piece capacitors connected in series as a whole is connected in parallel with the safe capacitor to two terminals of which are connected the anode and the cathode of SCR, respectively; the anode of SCR is also connected to one terminal of the inductor, the branch composed of the first and the second resistors connected in series is connected in parallel so that one terminal of which is connected to one terminal of the inductor and the other is connected to the cathode of SCR; the gate of SCR is connected between the first and the second resistors.

Abstract: Various apparatuses and methods for starting a thyristor are disclosed herein. For example, some embodiments provide an apparatus for starting a thyristor, the apparatus including a thyristor, a switch, a load connected to the thyristor and the switch, and a controller connected to a control input of the switch. The controller is adapted to operate the switch to apply the load to the thyristor for a predetermined period when power is first applied to the thyristor.

Abstract: Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by ?/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.

Abstract: A gate drive circuit for a silicon controlled rectifier (SCR) connected in an a-c power circuit includes a voltage divider network connected between a d-c voltage source and the SCR for developing a varying voltage on a control node, depending upon whether the anode-to-cathode a-c voltage of the SCR is positive or negative. A first switching transistor, responsive to the control node voltage, controls conduction of a second switching transistor connected between the d-c voltage source and a voltage regulated driver circuit. In this way, a constant drive current is applied to the SCR gate only while the anode-to-cathode voltage of the SCR is positive.

Abstract: An inductance in a path (R1) from a gate electrode (3G) of a GTO (3) through a gate driver (4) and a node (13) to a cathode electrode (3K) is determined so that a turn-off gain may be not more than 1. At a turn-off, a main current (I.sub.A) is entirely commutated from the gate electrode (3G) towards the node (13) through the gate driver (4) in a direction reverse to a turn-off control current (I.sub.G) A peak voltage suppressing circuit (5) clamps an anode-cathode voltage (V.sub.A-K) which rises on, to a prescribed voltage value for a prescribed time. This prevents losses caused by a snubber circuit. Commutation of a main current to the gate prevents locally concentrating in the cathode side of the semiconductor switching element, to thereby increase the turn off capability of the semiconductor switching element. Further, this prevents or reduces dissipation of large amount produced by a discharge of the electric charges from a snubber capacitor.

Abstract: An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR.

Abstract: A control device for controlling a double gate semiconductor device having a second gate electrode for controlling transition from a thyristor operation to a transistor operation, and a first gate electrode for controlling transition from transistor operation to an ON/OFF operation, and for controlling a current passing from a collector electrode to an emitter electrode, includes a first gate control circuit for delaying a turn-off signal to the double gate semiconductor device and applying the turn-off signal to the first gate electrode.

Abstract: A monolithic voltage clamp provides low impedance, low voltage electrostatic discharge protection for an integrated circuit without affecting the integrated circuit's DC characteristics. First, second, third, and fourth regions of semiconducting material are formed with p-n junctions between each region. A first inductor electrically connects the first and second regions, and a second inductor electrically connects the third and fourth regions. The first and second inductors should each have an inductance which is large enough to delay an increase in bypass current around their respective p-n junctions for a period which is long enough to assure that conduction is sufficient to discharge an electrostatic pulse. In a preferred embodiment, first and second reverse bias diodes are used to electrically connect the invention to one or more input/output nodes.

Abstract: A power driver circuit for turning a semiconductor switching device on and off in response to receipt of a control signal includes a trigger circuit that turns on a latching switch at a speed that is independent of the rate of change of the control signal. The trigger circuit is responsive to the control signal to apply a current from the semiconductor switching device to the latching switch. A high speed SCR may be used as the latching switch and may be triggered by a small trigger current from the gate of the semiconductor switching device fed to both the anode and cathode gates of the SCR. High speed diodes may also be used to increase the speed of the circuit. The power driver circuit improves the efficiency of the semiconductor switching device by decreasing the time the switching device spends in transition its two steady states.

Abstract: A new SCR (silicon controlled rectifier) controller characterized by comprising input circuits, SCR trigger circuits, charge circuits, commutation capacitor, discharge circuits and SCR and being constructed in such way that when the input pulse is positive, it will work to activate the trigger and cause the SCR to be in turn-on state as well as to charge the commutation capacitor and when the input pulse is zero, the stored energy of the commutation capacitor will discharge to cause the SCR to be in turn-off state so that it does not need any other electric energy to attain the objective to cut off the source.

Abstract: An inductance in a path (R1) from a gate electrode (3G) of a GTO (3) through a gate driver (4) and a node (13) to a cathode electrode (3K) is determined so that a turn-off gain may be not more than 1. At a turn-off, a main current (IA) is entirely commutated from the gate electrode (3G) towards the node (13) through the gate driver (4) in a direction reverse to a turn-off control current (IG) A peak voltage suppressing circuit (5) clamps an anode-cathode voltage (VA-K) which rises on, to a prescribed voltage value for a prescribed time. This prevents losses caused by a snubber circuit. Commutation of a main current to the gate prevents locally concentrating in the cathode side of the semiconductor switching element, to thereby increase the turn off capability of the semiconductor switching element. Further, this prevents or reduces dissipation of large amount produced by a discharge of the electric charges from a snubber capacitor.