Abstract: In an example, a logic circuitry package is configured to be addressable via a first address and at least one second address and comprises a first logic circuit. The first address may be an address for the first logic circuit, and the package may be configured such that, in response to a first command indicative of a first command time period sent to the first address, the package is accessible via at least one second address for a duration of the first command time period; and in response to a second command indicative of a second command time period sent to the first address, the first logic circuit is to, for a duration of the second command time period, disregard traffic sent to the first address.

Abstract: A multiphase voltage regulator includes a plurality of phases and a controller. Each phase is configured to output a phase current to a load through an inductor in response to a control signal input to the phase. The controller is operable to: generate the control signals input to the phases; set a switching frequency of the control signals to a first value; and change the switching frequency from the first value to a second value different than the first value if the load current changes repetitively at a frequency that is within a predetermined range of the first value of the switching frequency. A corresponding method of operating the multiphase voltage regulator is also provided.

Abstract: A single-photon receiver and method for detecting a single-photon are presented. The receiver comprises a SPAD that receives a gating signal having a fundamental frequency in the 100 MHz to multiple GHz range. The receiver further comprises a two-stage frequency filter for filtering the output of the SPAD, wherein the filter has: (1) a notch filter response at the fundamental frequency; and (2) a low-pass filter response whose cutoff frequency is less than the first harmonic of the fundamental frequency. As a result, the frequency filter removes substantially all the frequency components in the SPAD output without significant degradation of the signal quality but with reduced complexity, cost, and footprint requirement relative to receivers in the prior art.

Abstract: An analog silicon photomultiplier system includes at least one analog pixel comprising a plurality of analog photodiodes (APDs), and a capacitor, a signal generator, a phase detector, and a compensation network. The signal generator is configured to generate and propagate a sinusoidal signal concurrently along first and second transmission lines. A capacitor is loaded on the first transmission line when an APD corresponding to the capacitor detects a photon. The phase detector is coupled with the first and second transmission lines, determines a phase difference between the first transmission line and the second transmission line and calculates a number of APDs that have fired from the phase difference. The compensation network is coupled with the second transmission line and the phase detector, and comprises a plurality of compensation capacitors, wherein the compensation capacitors are loaded on the second transmission line in proportion to the number of APDs that have fired.

Abstract: A gate driver for driving a gate of a switching element Tr7 includes a driving part that drives the switching element according to a control signal and an active clamp circuit to clamp the voltage between the first and second main terminals of the switching element through the driving part. If a voltage applied between a first main terminal (drain) and a second main terminal (source) of the switching element exceeds a predetermined voltage, the active clamp circuit forcibly blocks a driving operation of the driving part from driving the switching element.

Abstract: This disclosure relates to an organic zener diode having one electrode and one counter electrode, and an organic layer arrangement formed between the electrode and the counter electrode, wherein the organic layer arrangement includes the following organic layers: an electrically n-doped charge carrier injection layer on the electrode side, made from a mixture of an organic matrix material and an n-dopant, an electrically p-doped charge carrier injection layer on the counter electrode side, made from a mixture of another organic matrix material and a p-dopant, and an electrically undoped organic intermediate layer that is arranged between the electrically n-doped charge carrier injection layer on the electrode side and the electrically p-doped charge carrier injection layer on the counter electrode side. An electronic circuit arrangement with an organic zener diode and method for operating an organic zener diode are also provided.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and thus also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: The device and method monitor the current delivered to a load through a power transistor including a sense transistor. The circuit includes a disturbances attenuating circuit that has a differential stage, and first, second and third stages referenced to ground, the respective input nodes of which are connected in common to an output node of the differential stage. The third stage is formed by a transistor identical to a transistor of the first stage and delivers a current signal through a current terminal thereof, proportional to the current being delivered to the load.

Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.

Abstract: A trailing edge of a control signal of a transistor controller for controlling an output transistor is detected by an edge detector of a clamp controlling circuit. A surge voltage from a back electromotive voltage induced in an inductance L1 is absorbed from the output transistor, only for a given period immediately after the solenoid is turned off, by turning a switching transistor into an on-state by a timer to force a clamping circuit into conduction. At a normal operation, since the clamping circuit is cut off from an output terminal, the clamping voltage can be set in a manner to reduce to a normal voltage in an IGN-line. Therefore, a peak power value of a power loss caused by the surge voltage at the output transistor can be reduced, whereby generation of heat at the output transistor can be reduced. Therefore, the chip size of the power IC can be reduced.

Abstract: A gate drive circuit for a bidirectional blocking MOSFET, the bidirectional blocking MOSFET being characterized in the source region is not shorted to the body regions In one embodiment, the gate drive circuit includes diodes connected between the source/drain regions and a charge pump, the charge pump generating a gate drive voltage applied to a gate of the bidirectional blocking MOSFET. In a second embodiment, a charge pump generates a gate drive voltage which is applied to the gate of the bidirectional blocking MOSFET, and is also connected to the source/drain regions through zener diodes. In the second embodiment, the potential applied to the gate of the bidirectional blocking MOSFET is limited to a zener diode drop above the lower of the voltages of the source/drain regions. In a fourth embodiment, a charge pump generates a floating gate drive voltage which is applied to the gate of the bidirectional blocking MOSFET through first and second depletion mode MOSFETS.

Abstract: An overvoltage limiting circuit having first and second terminals to produce a temperature-stable voltage proportional to an overvoltage condition. The overvoltage limiting circuit includes a first transistor having a first terminal connected to the first terminal of the circuit, a second terminal kept at a reference voltage relative to the second terminal of the circuit, and a control terminal coupled with the second terminal of the circuit through equivalent resistor means whose value depends on the value of the temperature-stable voltage so that the first transistor has a temperature-stable breakdown voltage.

Abstract: A low cost, less complex microcomputer power supply circuit with temperature stability and low current consumption in which a single voltage regulating element is used to provide the supply voltage, power-on reset (POR) and low voltage inhibitor (LVI) functions to the microcomputer (12). In an exemplary embodiment, the power supply circuit (10) includes a regulating circuit with a zener diode (30) that is conductive when the voltage level of the DC source (14) is above a threshold value and nonconductive when the voltage level of the DC source (14) is below a threshold value. The regulator circuit provides a regulated supply voltage to the microcomputer from the DC source (14). The regulator circuit also provides a regulation signal, whose state depends on the conductivity of the zener diode (30), to a reset circuit. The reset circuit of the power supply circuit is responsive to the regulation signal for providing a reset signal to the microcomputer (12).

Abstract: A dV/dt clamp circuit is connected to a base of a phototransistor for triggering a control electrode of a thyristor, thereby making an attempt to prevent an operation error. A control electrode voltage of the thyristor is applied to the gate of the MOSFET via a high breakdown voltage capacitor. The gate electrode voltage of the MOSFET can be continuously held at a threshold value or more by adjusting a zener voltage of a zener diode and a resistance value of a resistor. Since with a high dV/dt the MOSFET can be operated at a high speed to allow conduction between the drain and source of the MOSFET, the phototransistor does not trigger the thyristor, thereby preventing an operation error.

Abstract: A gate drive circuit for a bidirectional blocking MOSFET, the bidirectional blocking MOSFET being characterized in the source region is not shorted to the body region. In one embodiment, the gate drive circuit includes diodes connected between the source/drain regions and a charge pump, the charge pump generating a gate drive voltage applied to a gate of the bidirectional blocking MOSFET. In a second embodiment, a charge pump generates a gate drive voltage which is applied to the gate of the bidirectional blocking MOSFET, and is also connected to the source/drain regions through zener diodes. In the second embodiment, the potential applied to the gate of the bidirectional blocking MOSFET is limited to a zener diode drop above the lower of the voltages of the source/drain regions. In a fourth embodiment, a charge pump generates a floating gate drive voltage which is applied to gate of the bidirectional blocking MOSFET through first and second depletion mode MOSFETS.

Abstract: An apparatus for suppressing voltage transients across a first transistor is described. The first transistor has a first terminal, a second terminal, and a gate terminal, and is characterized by an avalanche breakdown voltage rating between the first and second terminals. The cathode of a first diode is coupled to the first terminal, the first diode having a reverse breakdown voltage which is less than the avalanche breakdown voltage rating. Gate driver circuitry is provided by which the gate terminal of the first transistor is coupled to the anode of the first diode. The gate driver circuitry provides a drive signal to the gate terminal of the first transistor, and comprises a plurality of bipolar transistors. Each bipolar transistor has an anode terminal (i.e., base terminal), a p-n junction, and a cathode terminal (i.e., emitter terminal). The anode terminal of each bipolar transistor is coupled to the anode of the first diode.

Abstract: A power stage of quasi-complementary symmetry, including a common-source FET and a common-drain FET, with a reduced absorption of current under the conditions of high impedance of the output. The driving node of the upper (common-drain) transistor from is decoupled from the output node of the stage, preventing the current generator Id, which discharges the control node, from absorbing current from the load connected to the output stage, during a phase of high output impedance. This is preferably realized by using a field effect transistor which has its gate connected to the output node of the stage, and is connected to provide the current drawn from the discharge generator of the driving node of the upper common-drain transistor, absorbing it from the supply node VDD instead of absorbing it from the voltage overdriven node Vb. This alternative solution avoids excessive loading of the high-voltage supply, and is particularly useful when the overdriven node Vb drives multiple output stages.

Abstract: The invention relates to a control circuit for a semiconductor switch, comprising a transformer coupling (T1, T2) for generating AC voltage signals including both control energy and control information, a rectification coupling (DB1, DB2) for rectifying the AC voltage signals generated by the transformer coupling (T1, T2) for generating DC voltage levels (U1, U2, U3) appropriate for turning on and turning off a semiconductor switch (SW1), a first resistor (R2) connected at its first end to a driving electrode of the semiconductor switch (SW1), a second resistor (R1) connected between the driving electrode and the emitter or source electrode of the semiconductor switch, and a booster semiconductor switch (V1) provided between the driving electrode of the semiconductor switch (SW1) and an DC voltage output (U3) generated by the rectification coupling and intended for turning off the semiconductor switch, the driving electrode of the booster semiconductor (V1) being connected to a DC voltage output (U2) generate

Abstract: A remote power feed device for electronic equipment comprises two branches in parallel of which a first branch includes in series as many sets of Zener diodes as there are functional systems to be powered. The other or second branch includes one or more Zener diodes. Only the Zener diodes of the first branch conduct in normal operation, i.e. in the absence of any overcurrent. The supply voltage or voltages of the various subsystems of the same functional system are the voltage(s) across a common Zener diode or common Zener diodes of a common set of Zener diodes of the first branch.

Abstract: In one form of the invention, a circuit is disclosed, the circuit comprising: a transistor Q having an input terminal 14 with an avalanche breakdown voltage to electrical ground; and one or more diodes 16 arranged in a series between the input terminal 14 and electrical ground, the diode series 16 having a forward-biased voltage drop that is smaller than the avalanche breakdown voltage.

Abstract: A gate drive circuit for a bidirectional blocking MOSFET, the bidirectional blocking MOSFET being characterized in the source region is not shorted to the body region. In one embodiment, the gate drive circuit includes diodes connected between the source/drain regions and a charge pump, the charge pump generating a gate drive voltage applied to a gate of the bidirectional blocking MOSFET. In a second embodiment, a charge pump generates a gate drive voltage which is applied to the gate of the bidirectional blocking MOSFET, and is also connected to the source/drain regions through zener diodes. In the second embodiment, the potential applied to the gate of the bidirectional blocking MOSFET is limited to a zener diode drop above the lower of the voltages of the source/drain regions. In a fourth embodiment, a charge pump generates a floating gate drive voltage which is applied to gate of the bidirectional blocking MOSFET through first and second depletion mode MOSFETS.