Abstract: Circuits integrated or integrable with a photovoltaic panel to provide built-in functionality to the photovoltaic panel including safety features such as arc detection and elimination, ground fault detection and elimination, reverse current protection, monitoring of the performance of the photovoltaic panel, transmission of the monitored parameters and theft prevention of the photovoltaic panel. The circuits may avoid power conversion, for instance DC/DC power conversion, may avoid performing maximum power tracking to include a minimum number of components and thereby increase overall reliability.

Abstract: Storage apparatus (20) includes a memory (30) and an encryption processor (28), which is configured to receive and encrypt data transmitted from one or more computers (24) for storage in the memory. A one-way link (32) couples the encryption processor to the memory so as to enable the encryption processor to write the encrypted data to the memory but not to read from the memory.

Abstract: A semiconductor apparatus includes: a first transistor; a second transistor having a higher withstand voltage than the first transistor, a source of the second transistor coupled to a drain of the first transistor, a gate of the second transistor coupled to a source of the first transistor; a third transistor having a higher withstand voltage than the first transistor and a drain of the third transistor coupled to a drain of the second transistor; and a comparator that compares a source voltage of the first transistor with a source voltage of the third transistor, and controls a gate voltage of the first transistor.

Abstract: This document discusses, among other things, a system and method for offsetting reverse-bias leakage of a high impedance bias network. In an example, an apparatus includes an anti-parallel diode pair coupled between a signal node and a common-mode node. The anti-parallel diode pair can include a first diode and a second diode coupled to the first diode. A third diode can be coupled between a supply node and the signal node, and the third diode can be sized to compensate for a parasitic diode junction of the anti-parallel diode pair.

Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least two dopants are present in a spatially varying region of the active region prior to device actuation. The at least two dopants have opposite conductivity types and different mobilities.

Abstract: This document discusses, among other things, a system and method for offsetting reverse-bias leakage of a high impedance bias network. In an example, an apparatus includes an anti-parallel diode pair coupled between a signal node and a common-mode node. The anti-parallel diode pair can include a first diode and a second diode coupled to the first diode. A third diode can be coupled between a supply node and the signal node, and the third diode can be sized to compensate for a parasitic diode junction of the anti-parallel diode pair.

Abstract: The invention relates to a circuit arrangement for a current-controlled resistor having an enlarged linear range, using an arrangement of non-linear bipolar load elements wherein the resistance is generated between a first terminal (E) and a second terminal (F), having at least one control terminal (X) that is fed by a supply current source (I1), wherein the arrangement of the non-linear bipolar load elements comprises at least a third chain (C) comprising one or more of the load elements (DCl . . . DCi), the load elements being connected in series where there is more than one of them, and comprises a first chain (A) and a second chain (B) each comprising one or more load elements (DAl . . . DAj and DBl . . .

Abstract: A circuit configuration produces an at least approximately ideal diode characteristic on the basis of a diode. A power MOSFET has a control path connected in parallel with the diode, a load path forming connection terminals of the ideal diode, and a gate connection to which a predetermined voltage potential is applied, for turning on the power MOSFET in the forward-bias direction of the diode and turning off the power MOSFET in the reverse-bias direction.

Abstract: The present invention relates to a variable power-attenuation circuit whose attenuation is controlled electronically by a control voltage (Vc). This circuit includes resistive elements (R20, R21, D20, D21) of which at least two resistive elements are diodes (D20, D21), and a biasing device intended to set the direct current passing through the diodes. This circuit is characterized in that the biasing device includes means for independently setting the characteristic impedance of the circuit, the size of the dynamic range of the control voltage (Vc) and the position of the said dynamic range.Application to the production of transmission devices for directional radio.

Abstract: A high frequency clock signal generator (10) is disclosed. The clock signal generator includes a power supply (12, 14), a first resonant tunneling diode (18) coupled to a first terminal of the power supply and an output node (22), and a second resonant tunneling diode (20) coupled to the output node (22) and a second terminal of the power supply. A signal source is coupled to the output node (22) and periodically switches the first and second resonant tunneling diodes (18, 20) between a first state and a second state. The signal source comprises an oscillating signal generator (26) and a transmission line (28) coupled to the output node (22) of the clock signal generator. The oscillating signal generator (26) produces an oscillating input signal, which is reflected by the transmission line (28). The resonant tunneling diode configuration provides rapid voltage swings at the output, thus allowing the generation of a high frequency clock signal of 25 GHz or more.

Abstract: An apparatus for protecting an integrated circuit against damage from electrostatic discharges (ESD) includes a single ESD bus that is connected to multiple input pads through a respective diode. The ESD bus is isolated from the positive power supply bus V.sub.DD. The ESD bus is coupled to the negative power supply bus V.sub.SS by a FET-triggered SCR circuit. ESD charge on an input pad forward biases the respective diode and charges the ESD bus. When the voltage of the ESD bus reaches a predetermined threshold voltage, the FET breaks down, and triggers the SCR circuit to shunt the charge on the ESD bus to V.sub.SS. The threshold voltage is selected such that, in normal operation, voltages higher than V.sub.DD may be applied to the input pad without input leakage current.

Abstract: A bipolar radio frequency (RF) integrated circuit having a functional equivalent of a PIN diode. The RF integrated circuit includes a low frequency lateral PNP transistor having an emitter having a P+ region, a collector having a P+ region, a base having an N+ region and an N region having a current dependent stored charge having a relatively low level when no current is flowing between the emitter and a junction connecting the base and collector. An RF resistance between the emitter and the junction is controlled by a bias applied from the emitter to the junction. By varying the bias, the low frequency lateral PNP transistor from the emitter to the junction is used as a variable RF resistor or as an RF signal carrying component in a variable attenuator or RF switch.

Abstract: A large-area electronic device comprises an array (1) of device elements (2,3) coupled to row and column conductors (A and B). The column conductors (B) are arranged in groups, (e.g M, M+1, M+2), and a column multiplexer circuit (C) couples the column conductors (B) of a respective group to a respective common terminal (5). The present invention provides a compatible multiplexer circuit (C) for the array (1), the operation of the circuit (C) using electrical switching rather than optical switching. This multiplexer circuit (C) for each column conductor comprises a diode bridge (SD3 to SD6) and may include a clamping switch (SD1, SD2). A signal is transmitted between the column conductor (B) and a common output terminal (5) in a first state of the diode bridge (SD3 to SD6). The potential of the column conductor (B) is clamped by the clamping switch (SD1, SD2) in a second state of the diode bridge.

Abstract: The sampling phase detector whose output signal (fd) has a very broad-band and a very even frequency response characteristic includes a step-recovery-diode (SRD) to which a series circuit including at least two diodes (D1,D2) is connected in parallel by means of coupling capacitors (Ck1,Ck2). An input signal is fed to the diodes (D1,D2) by means of an R/C-network (R1,R2,C3,C4) and an output signal (fd) is taken off, which corresponds to the phase shift between an input signal (fo) and a reference signal (fr). The reference signal (fr) is fed to the step-recovery-diode (SRD) via a balancing transformer (Tr). Decoupling resistors (Rs1,Rs2) are included in the connecting lines from the balancing transformer (Tr) to the step-recovery-diode (SRD), which damp interfering resonances or reflections of the balancing transformer.

Abstract: An overvoltage limiting circuit having first and second terminals to produce a temperature-stable voltage proportional to an overvoltage condition. The overvoltage limiting circuit includes a first transistor having a first terminal connected to the first terminal of the circuit, a second terminal kept at a reference voltage relative to the second terminal of the circuit, and a control terminal coupled with the second terminal of the circuit through equivalent resistor means whose value depends on the value of the temperature-stable voltage so that the first transistor has a temperature-stable breakdown voltage.

Abstract: An integrated semiconductor circuit comprising an output terminal connected to a ground terminal via a series connection of a first switching transistor and a second switching transistor of inverse polarization with respect to the latter, each of said switching transistors having parasitic transistors. Whether the second semiconductor switch means is conducting or not, is dependent on the current flow through a resistor connected between gate and source of the second semiconductor switch means. Whether current flows through this resistor, is dependent on the switching condition of a further switching transistor, which in turn is also determined by the output signal of a comparator circuit by means of which a potential corresponding to the potential present at output terminal is compared to a reference potential.

Abstract: In a laser diode which forms read and write functions upon an electro-optic memory, a drive circuit provides power modulation during the read function and sufficient power to perform a write function. During a read function, transistors connected in an emitter coupled switch pair modulate the power delivered to the laser diode. At the emitters of each transistors are a pair of Schottky diodes which enhance the switching speeds of the transistors. Logic is provided to completely turn on the read switch during the time the write switch is on in order to provide sufficient power to the laser diode in order to perform a write function.

Abstract: A rectifying device comprising of a SRMOS, an inductor, and a control circuit is disclosed. The SRMOS has a gate, a drain, and a source. The gate of the SRMOS is connected to the output of the control circuit. The inductor is connected to the drain of the SRMOS. The control circuit uses two sense traces for determining the voltage (or current) passing between the inductor (that is connected to the drain) and the source of the SRMOS. Upon sensing a forward characteristic (voltage or current), the SRMOS forward biases to allow current to flow through the SRMOS. Upon sensing a reverse characteristic (voltage or current), the SRMOS reverse biases to cut off any current flow. Hysteresis is used in setting the forward biasing threshold voltage and the reverse biasing threshold voltage for the SRMOS. In reverse biasing and forward biasing the SRMOS, V.sub.gs is stepped (or curved) controlled to avoid false turn ON/OFF of the SRMOS.

Abstract: A method of designing improved CMOS input circuits by understanding and selecting appropriate drive strength for a CMOS output from a previous stage. The method involves modeling the net using HSPICE and including a transit time term to accurately model charge storage, then size drivers as needed to keep the V.sub.ss clamps out of forward conduction. Excessive ringing can cause data errors in the input stage if unterminated, falling edge transitions in such a net can turn on a receiver's V.sub.ss clamp diode (stored charge in the V.sub.ss clamp diode combined with the line's inductance and the receiver's capacitance form an energized resonant circuit which can release energy at a time to cause a data glitch). Currently, XNS simulation miscalculates the ring amplitude by a factor of three. Driver scaling and termination can eliminate the problem by keeping the receiver's V.sub.ss clamp out of forward conduction. Driver sizing can control the problem.

Abstract: A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.

Abstract: An output circuit is provided for obtaining an output signal at one of two voltages regardless of the relative difference between the voltage levels. The output circuit includes a first switching circuit that contains two current sources for selectively producing one of two constant currents. A second switching circuit receives one of the two constant currents. The first and second switches are connected by four series-connected forward biased diodes. There are also bypass connectors for selectively providing current around the first and fourth diodes. An output terminal is located between the second and third diodes. A high voltage source is located between the first switching circuit and the first diode. A low voltage source is located between the fourth diode and the second switching circuit. Depending which of the current sources are actuated, the signal present at the output terminal is either that of the high voltage source or that of the low voltage source.

Abstract: A laser diode driver chip is disclosed which has a circuit to substantially reduce a ringing on a laser diode driving current generated by the laser diode driver chip. This invention identifies that the ringing on the laser diode driving current is caused by three different resonances which are coupled together. This invention also suggests a model for the sources of these three different resonances and identifies the three main nodes which are common between the sources of resonances. Finally, this invention places a damping circuit between the three main nodes of the laser diode driver to substantially reduce the ringing on the laser diode driving current.

Abstract: A device compensated for an undesired capacitance includes a first and a second node between which nodes the undesired capacitance is present. A diode driven in breakthrough is coupled between the first and the second node. As a diode driven in breakthrough exhibits the characteristics of a negative capacitance, a compensation of the undesired capacitance is achieved.

Abstract: A controlled capacitor system, which includes a capacitor element (C1) and a forward-biased diode element (D2) connected in series with the capacitor element (C1). The system is such that the diode element (D2) has a capacitance which is less than the capacitance of the capacitance of the capacitor element (C1) when the diode element (D2) is under zero bias. The capacitance of the diode element (D2) is controlled by varying the forward current (I2) through the diode (D2). The forward current (I2) acting to control the capacitance of the diode element is selected such that the capacitance of the diode element (D2) is smaller than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) is below a minimum value. The capacitance of the diode element (D2) is bigger than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) exceeds a maximum value.

Abstract: A common dictionary definition of a "diode" is "any electronic device that restricts current flow chiefly to one direction." This definition covers not only the conventional two lead PN junction semiconductor device presently known in the prior art (referred to herein as a "conventional diode") but also the electronic device of this invention (referred to herein as a "low power diode"). A low power diode has a comparator for comparing the voltage present at the anode and cathode of the diode. When the comparator determines that the voltage present at the anode of the low power diode equals or exceeds the voltage present at the cathode of the low power diode by a predetermined forward voltage, a signal is generated. This signal turns on a transistor acting as a switch, which in turn electronically connects the anode and the cathode of the low power diode together. Unlike conventional diodes that have a forward voltage (dependent on the physical silicon junction property of the diode) of approximately 0.