Abstract: Aspects of the present disclosure provide an oscillating circuit. An example oscillating circuitry generally includes a differential control pair comprising a first control node and a second control node. The oscillating circuit further includes a first voltage-controlled oscillator (VCO) comprising a first differential varactor circuit having a first positive control input coupled to the first control node and a first negative control input coupled to the second control node. The oscillating circuit also includes a second differential varactor circuit having a second positive control input coupled to the second control node and a second negative control input coupled to the first control node.

Abstract: A low-noise amplifier system is disclosed. The low-noise amplifier system includes a low-noise amplifier having an input node and an output node in a receive path and a capacitance equalization network coupled to the output node. Compensation capacitance of the capacitance equalization network sums with non-linear capacitance of the low-noise amplifier such that a total capacitance at the output node varies by no more than ±5% over an output voltage range within voltage headroom limits of the low-noise amplifier for a given supply voltage of the low-noise amplifier. In at least some exemplary embodiments, the compensation capacitance of the capacitance equalization network is a function of output signal voltage at the output node.

Abstract: Disclosed herein are a hybrid variable capacitor, an RF apparatus, a method for manufacturing a hybrid variable capacitor, and a method for tuning a variable capacitor. The hybrid variable capacitor used in a tunable matching network includes: a metal-insulator-metal (MIM) cap array including one or more MIM capacitors and having varied capacitance equivalent to values of a lower-bit region among digital values corresponding to capacitance to be tuned; and a MOS varactor connected in parallel to the MIM cap array and having varied capacitance equivalent to values of an upper-bit region among the digital values.

Abstract: A receiving circuit with a simple circuit structure for performing wireless communication utilizing electromagnetic induction is provided. An LSI chip and a storage medium where wireless communication utilizing electromagnetic induction is performed and the circuit scale and circuit size can be reduced are provided. The following receiving circuit may be used: a parallel circuit where two diode elements whose directions are opposite are connected in parallel is used, one end of the parallel circuit is connected to the other end of a coil whose one end is connected to a ground potential line, and a capacitor is connected in series with the other end of the parallel circuit. A transistor whose leakage current is markedly reduced may be used as a diode in the receiving circuit. Such a receiving circuit may be used in an LSI chip or a storage medium.

Abstract: A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Abstract: Methods of fabricating an on-chip capacitor with a variable capacitance, as well as methods of adjusting the capacitance of an on-chip capacitor and design structures for an on-chip capacitor. The method includes forming first and second ports configured to be powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. The method includes configuring the first voltage-controlled unit to selectively couple the first electrode with the first port, and the second voltage-controlled unit to selectively couple the second electrode with the second port. When the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port, the capacitance of the on-chip capacitor increases.

Abstract: The LC tank of a VCO includes a main varactor circuit and temperature compensation varactor circuit coupled in parallel with the main varactor circuit. The main varactor is used for fine tuning. The temperature compensation varactor circuit has a capacitance-voltage characteristic that differs from a capacitance-voltage characteristic of the main varactor circuit such that the effects of common mode noise across the two varactor circuits are minimized. The LC tank also has a plurality of switchable capacitor circuits provided for coarse tuning. To prevent breakdown of the main thin oxide switch in each of the switchable capacitor circuits, each switchable capacitor circuit has a capacitive voltage divider circuit that reduces the voltage across the main thin oxide switch when the main switch is off.

Abstract: Implementations of differential variable capacitance systems are disclosed.

Abstract: A capacitive load driver includes a first switching element whose first end receives positive potential, an EL element arranged between a second end of the first switching element and the ground, a charge collecting capacitor whose first end is connected to a positive electrode terminal of the EL element, a voltage source connected between a second end of the charge collecting capacitor and the ground, and a controller. The controller charges a parasitic capacitance of the EL element and the charge collecting capacitor, and thereafter, applies negative potential from the voltage source to the second end of the charge collecting capacitor. Thereafter, the controller brings the output voltage of the voltage source to ground potential so that the charge collecting capacitor is discharged to charge the EL element. The capacitance of the charge collecting capacitor is set to be sufficiently greater than that of the parasitic capacitance.

Abstract: One exemplary tunable capacitive device includes a first tunable capacitive element, a first coupling capacitive element, a first coupling resistive element, and a first specific capacitive element. The first tunable capacitive element has a first node coupled to a first input voltage, and a second node. The first coupling capacitive element has a first node coupled to the second node of the first tunable capacitive element, and a second node coupled to a first connection terminal of the tunable capacitive device. The first coupling resistive element has a first node coupled to the second node of the first tunable capacitive element, and a second node coupled to a second input voltage, where the first input voltage and the second input voltage include a control voltage and a reference voltage. The first specific capacitive element is coupled between the first node and the second node of the first tunable capacitive element.

Abstract: An improved varactor diode (20, 50) having first (45) and second (44) terminals is obtained by providing a substrate (22, 52) having a first surface (21, 51) in which are formed isolation regions (28, 58) separating first (23, 53) and second (25, 55) parts of the diode (20, 50). A varactor junction (40, 70) is formed in the first part (23, 53) and having a first side (35, 66) coupled to the first terminal (45) and a second side (34, 54) coupled to the second terminal (44) via a sub-isolation buried layer (SIBL) region (26, 56) extending under the bottom (886) and partly up the sides (885) of the isolation regions (28, 58) to a further doped region (30, 32; 60, 62) ohmically connected to the second terminal (44). The first part (36, 66) does not extend to the SIBL region (26, 56). The varactor junction (40, 70) desirably comprises a hyper-abrupt doped region (34, 54).

Abstract: An improved varactor diode (20, 50) having first (45) and second (44) terminals is obtained by providing a substrate (22, 52) having a first surface (21, 51) in which are formed isolation regions (28, 58) separating first (23, 53) and second (25, 55) parts of the diode (20, 50). A varactor junction (40, 70) is formed in the first part (23, 53) and having a first side (35, 66) coupled to the first terminal (45) and a second side (34, 54) coupled to the second terminal (44) via a sub-isolation buried layer (SIBL) region (26, 56) extending under the bottom (886) and partly up the sides (885) of the isolation regions (28, 58) to a further doped region (30, 32; 60, 62) ohmically connected to the second terminal (44). The first part (36, 66) does not extend to the SIBL region (26, 56). The varactor junction (40, 70) desirably comprises a hyper-abrupt doped region (34, 54).

Abstract: A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Abstract: On-chip capacitors with a variable capacitance, as well as design structures for a radio frequency integrated circuit, and method of fabricating and method of tuning on-chip capacitors. The on-chip capacitor includes first and second ports powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. Each of the first and second voltage-controlled units is switched between a first state in which the first and second electrodes are electrically isolated from the first and second ports and a second state. When the first voltage-controlled unit is switched to the second state, the first electrode is electrically connected with the first port. When the second voltage-controlled unit is switched to the second state the second electrode is electrically connected with the second port. The on-chip capacitor has a larger capacitance value when the first and second voltage-controlled units are in the second state.

Abstract: An embodiment of the present invention provides an apparatus, comprising a first half cell comprising a circuit with two or more voltage variable capacitors (VVCs) configured in anti-series in which one or more of the two or more VVCs with the same bias voltage orientation as a signal voltage associated with the apparatus assume one capacitance and one or more of the two or more VVCs with the opposite bias voltage orientation as the signal voltage assume another capacitance, and a second half cell connected in parallel to the first half cell, comprising a circuit with two or more VVCs configured in anti series in which one or more of the two or more VVCs with the same bias voltage orientation as a signal voltage associated with the apparatus assume the same values as the anti-oriented VVCs in the first half cell and a one or more VVCs with the opposite bias voltage orientation as a signal voltage assume the same values as the like oriented VVCs in the first half cell.

Abstract: The invention specifically concerns a device for varying the apparent level of a capacity, said device being characterized in that it compromises: —a dipole (1) of a type known per se, comprising a semiconductor material (4) for electronic transfer via hopping situated between a first electrode (2) and a second electrode (6), with said dipole (1) situated parallel to said capacity (12); —a continuous voltage generator (13) electrically connected to the second electrode (6) and the first electrode (2) of the dipole (1); —and a means for varying the voltage generated by the generator (13).

Abstract: To avoid intermodulation interferences, a varactor diode alternative circuit has at least three varactor diodes connected in series alternatingly opposite to one another and a resistor and/or inductor network. At each of the varactor diodes, a control voltage supplied to the circuit for adjusting capacitance is at least approximately at full extent. An alternating voltage applied at the series connection, which is at a higher frequency than the control voltage, is distributed at least approximately uniformly to the varacter diodes. Even for an at least not substantially larger tuning voltage than the amplitude of a signal voltage to be processed in the oscillator circuit that has the alternative circuit, reactions of the signal voltage on the set capacitance of the varactor diode alternative circuit remain negligible, or at least low. The circuit may be used in an electrical, e.g., battery-operated, unit in which only one small operating voltage is available.

Abstract: Provided is a differential varactor using a gated varactor, which has a wider tuning range and a better linearity and minimum to maximum capacitance ratio than conventional PN-junction and MOS varactors. Thus, the differential varactor having a wider tuning range, and better linearity and common-mode rejection ratio may be implemented.

Abstract: A varactor device includes a capacitance circuit having a capacitor set and a first transistor connected across the capacitor set; a first variable resistor; and a second transistor coupled to the first transistor and connected in series to the first variable resistor for feeding an output signal generated by applying voltage to the capacitance circuit back to the first transistor, thereby controlling a gain of the first transistor by tuning the first variable resistor.

Abstract: A voltage-controlled capacitor circuit and related circuitry. The voltage-controlled capacitor circuit includes a metal-oxide semiconductor (MOS) varactor, a diode varactor, and/or a capacitor with fixed capacitance. The MOS varactor, the diode varactor and the capacitor are electrically connected in parallel or in series to form a capacitor with a preferred characteristic of voltage-controlled capacitance.

Abstract: A metal oxide semiconductor (MOS) varactor device has a source and a drain connected to each other, and a back gate, electrically separate from the source and drain, which is connected to a circuit common mode point.

Abstract: A composite rectifying charge storage device, consisting of a rectifier and a capacitor which share common elements, further includes a transistor.

Abstract: A rectifying charge storage device, consisting of a rectifier and capacitor which share common elements, includes a sensor responsive to a monitored parameter such as pressure or the presence of a target chemical agent, to produce a variable and detectable electronic signal representative of the monitored parameter.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A rectifying charge storage device, consisting of diode and capacitor components which share common elements, includes a bi-stable state element responsive to an input signal for opening or closing a circuit, as by changing to one of two definable stable states. The bi-stable state element may comprise the diode or capacitor components, or both, of the rectifying charge storage device, and may be designed for irreversible or reversible operation.

Abstract: A power diverter is presented. The power diverter includes a first ninety degree hybrid having one output coupled to a positive adjustable phase shifter and another output coupled to a negative adjustable phase shifter providing a negative phase shift. The value of the phase shift provided by the positive phase shifter and the negative phase shifter is the same amount of degrees but opposite. A second ninety degree hybrid combines the outputs of the phase shifters. The circuit is provided comprising only analog linear components such that no spurious signals are introduced, and the circuit is impedance matched on all ports such that no degradation of noise figure is introduced. The power diverter can also be configured as a programmable tap of a delay line.

Abstract: A CMOS line driver is made up of p- and nMOS transistors. A pMOS varactor is interposed between the source of the pMOS transistor and a power supply, while an nMOS varactor is interposed between the source of the nMOS transistor and ground. The sizes of each of these MOS varactors may be the same as those of the p- or nMOS transistor. Alternatively, each of these MOS varactors may have a channel area twice greater than that of the p- or nMOS transistor. The inverted version of a signal input to the line driver is supplied to the gates of the MOS varactors. In this manner, the MOS transistors, making up the line driver, can switch at a high speed.

Abstract: A capacitive element includes two or more voltage-variable capacitors (varactors). The varactors are configured so that they are coupled in series with respect to an applied AC signal and are coupled in parallel with respect to an applied DC bias voltage. The effective capacitance of the overall capacitive element can be tuned by varying the DC bias voltage.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and thus also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A voltage-controlled capacitor is configured in such a way that it contains two varactors connected in parallel. The varactors are connected in such a way that a capacitance is controlled by differential signals. This layout results in a voltage-controlled capacitor that has an optimally low sensitivity to interference.

Abstract: A voltage-controlled capacitor is configured in such a way that it contains two varactors connected in parallel. The varactors are connected in such a way that a capacitance is controlled by differential signals. This layout results in a voltage-controlled capacitor that has an optimally low sensitivity to interference.

Abstract: A semiconductor device includes a signal line and two adjacent wirings formed on a first substrate layer, an adjacent wiring formed on a second substrate layer, and an adjacent wiring formed on a third substrate layer. A logical level on the signal line is set constant, a first line capacitance is formed between the signal line and one of the adjacent wirings on the first substrate layer, and a second line capacitance is formed between the signal line and the other of adjacent wirings on the first substrate layer. Also, a signal is supplied to the adjacent wiring on the second substrate layer and the adjacent wiring on the third substrate layer. As a result, noise from the other adjacent wirings to the signal line can be reduced.

Abstract: A CMOS line driver is made up of p- and nMOS transistors. A pMOS varactor is interposed between the source of the pMOS transistor and a power supply, while an nMOS varactor is interposed between the source of the nMOS transistor and ground. The sizes of each of these MOS varactors may be the same as those of the p- or nMOS transistor. Alternatively, each of these MOS varactors may have a channel area twice greater than that of the p- or nMOS transistor. The inverted version of a signal input to the line driver is supplied to the gates of the MOS varactors. In this manner, the MOS transistors, making up the line driver, can switch at a high speed.

Abstract: In order to provide a variable capacitance circuit having very small voltage dependability, this circuit is constituted by two variable capacitance diodes. An input signal is applied to each of said diodes with backward polarity and a capacitance control voltage is applied to each of said diodes with the same polarity.

Abstract: A phase shifter circuit shifts the phase of a voltage varying RF signal at high RF power levels by using a diode arrangement of back to back diode sets connected in series to reduce the change in capacitive reactance of the diode arrangement. The diode arrangement is connected to a phase adjustment port of a phase shifting device which shifts the phase of the RF signal according to the capacitive reactance level at the phase adjustment port. A control circuit for each back to back diode set can be used to provide independent adjustment of each diode set to balance capacitive reactance responses between the diode sets to further reduce the change in capacitive reactance. In certain embodiments, the phase shifter circuit uses a ninely (90) degree hybrid coupler with two phase adjustment ports, a zero (0) degree port and a -90 degree port.

Abstract: A device compensated for an undesired capacitance includes a first and a second node between which nodes the undesired capacitance is present. A diode driven in breakthrough is coupled between the first and the second node. As a diode driven in breakthrough exhibits the characteristics of a negative capacitance, a compensation of the undesired capacitance is achieved.

Abstract: A controlled capacitor system, which includes a capacitor element (C1) and a forward-biased diode element (D2) connected in series with the capacitor element (C1). The system is such that the diode element (D2) has a capacitance which is less than the capacitance of the capacitance of the capacitor element (C1) when the diode element (D2) is under zero bias. The capacitance of the diode element (D2) is controlled by varying the forward current (I2) through the diode (D2). The forward current (I2) acting to control the capacitance of the diode element is selected such that the capacitance of the diode element (D2) is smaller than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) is below a minimum value. The capacitance of the diode element (D2) is bigger than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) exceeds a maximum value.

Abstract: An output stage device for an enhanced differential current switch. The output stage receives a differential signal pair from a prior logic stage and must shift the output signals to the levels necessary for the next stage. The output stage has a differential pair of emitter followers that are capacitively cross coupled. Capacitors couple the collector of a first transistor to the emitter of the second. The capacitors can be formed from forward biased diodes or transistors. The result is a more rapid falling output transition while reducing power requirements.

Abstract: To compensate for nonlinear signal distortions in analog optical communication transmission systems, caused by laser chirps and the chromatic dispersion of the optical fiber, an equalizer in the form of an LC component is known, whose capacitance is formed by a variable capacitance diode. However, the known equalizer functions only when the capacitance has the proper polarity, which cannot be predicted because of possible polarity inversion during signal transmission. According to the invention, the variable capacitance diode (C.sub.a) has another variable capacitance diode (C.sub.b), with the opposite polarity, connected in parallel, and is equally biased in the high-resistance direction. By adjusting the bias voltage of both capacitances, it can be achieved that one of the two variable capacitance diodes takes over the equalization function, and the other is practically inoperative.