Abstract: A circuit may include a controller, at least one bridge circuit, and a plurality of switches. The plurality of switches may be connected parallel to each other, each may have a switch output connected to the bridge circuit. The bridge circuit, upon receiving a current from the plurality of switches, may generate an output based on a reference voltage. The controller may generate a plurality of control signals, based on a voltage transition range, to selectively turn on the plurality of the switches in more than one combination, to supply a current to the output.

Abstract: A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: The invention provides a switching system. The switching system comprises an H bridge, a current router, and a control circuit. The H bridge comprises a first switch and a second switch coupled to a first output node and a third switch and a fourth switch coupled to a second output node, wherein a load is coupled between the first output node and the second output node. The current router comprises a first shunt switch and a second shunt switch coupled between the first output node and the second output node. The control circuit generates a first control signal to control the first switch and the fourth switch, generates a second control signal to control the second switch and the third switch, generates a third control signal to control the first shunt switch, and generates a fourth control signal to control the second shunt switch.

Abstract: A semiconductor apparatus includes: a first transistor; a second transistor having a higher withstand voltage than the first transistor, a source of the second transistor coupled to a drain of the first transistor, a gate of the second transistor coupled to a source of the first transistor; a third transistor having a higher withstand voltage than the first transistor and a drain of the third transistor coupled to a drain of the second transistor; and a comparator that compares a source voltage of the first transistor with a source voltage of the third transistor, and controls a gate voltage of the first transistor.

Abstract: The invention related in cell interface is a circuit of diode D1 to D4, comprises: a first terminal connected to positive voltage terminal of first cell E1; a second terminal connected to positive voltage terminal of second cell E2; and a third terminal connected to external positive terminal VP, the external negative voltage terminal VN connected to negative voltage terminal of first cell E1 and second cell E2, can be not occur loop current in parallel circuit.

Abstract: An H-bridge circuit includes a lower-arm field-effect transistor and a current supplying element that turns on when the drain of the lower-arm field-effect transistor is negatively biased due to regenerative current. When turned on, the current supplying element conducts current from the source to the drain of the lower-arm field-effect transistor, in parallel with a parasitic diode inherent in the lower-arm field effect transistor. The current supplying element competes with other parasitic elements that conduct current from peripheral circuitry to the drain of the lower-arm field-effect transistor, thereby reducing the amount of such current drawn through the peripheral circuitry and lessening the impact of the regenerative current on the peripheral circuits.

Abstract: A semiconductor diode with integrated resistor has a semiconductor body with a front surface, a back surface and a diode structure with an anode electrode and a cathode electrode.

Abstract: A pre-driver for driving a high-side transistor of a bridge driver is connected to a bridge driver including first and second drive transistors connected in series between a high voltage power supply and ground. A reference circuit generates a reference voltage that varies depending on the output voltage of the bridge driver. In response to the reference voltage, the regulator circuit generates an internal power supply voltage that is substantially higher than the output voltage by a constant value. A buffer circuit generates a drive voltage for driving the first drive transistor based on the internal power supply voltage and the output voltage.

Abstract: A medium voltage adjustable frequency drive includes an input isolation transformer having a three-phase input and a three-phase output, a converter having a three-phase input electrically connected to the three-phase output of the input isolation transformer and an output providing a direct current bus, an inverter having an input electrically connected to the output of the converter and a three-phase output, and a pre-charge circuit. The pre-charge circuit includes a ferro-resonant transformer circuit having a primary winding structured to input a low voltage and a secondary winding structured to output a medium voltage and provide a constant current source. The pre-charge circuit also includes a medium voltage diode bridge having an input receiving the medium voltage from the secondary winding of the ferro-resonant transformer circuit and an output structured to provide the constant current source to the direct current bus.

Abstract: A resonate gate drive circuit for driving at least one power switching devices recovers energy loss for charging and discharging the input capacitance of the power switching devices. The gate drive circuit charging and discharging the gate capacitor with a high level current, so the switching loss of the power switching devices can also be reduced. The gate drive circuit can clamp and keep the voltage across the gate capacitor to a certain level while the power switching devices turn on, and it can also clamp and keep the voltage across the gate capacitor to almost zero while the power switching devices turn off. The gate drive circuit comprises four small semiconductor bidirectional conducting switching devices connected in full-bridge configuration. An inductor is connected to the two junctions of the full-bridge configuration to help switching the current direction. A capacitor in series with the inductor is necessary for some applications.

Abstract: A resonate gate drive circuit for driving at least one power switching device recovers energy loss for charging and discharging the gate capacitance of the power switching devices. The gate drive circuit uses a current source to charge and discharge the gate capacitance with a high current, reducing the switching loss of the power switching device. The gate drive circuit comprises four semiconductor bidirectional conducting switching devices connected in a full-bridge configuration. An inductor connected across the bridge configuration provides the current source. The gate drive circuit may be used in single and dual high-side and low-side, symmetrical or complementary, power converter gate drive applications.

Abstract: A matrix converter that can be used as part of a two-stage power converter has three ac three ac voltage lines AC1, AC2 and AC3 and two dc voltage lines DC1 and DC2. An array of six semiconductor switches 10a to 10f are arranged such that each of the three ac voltage lines AC1, AC2 an AC3 can be connected to one of the two dc voltage lines DC1 and DC2 when the associated switch is closed. A freewheel path is provided between the two dc voltage lines DC1 and DC2, which provides a fifth state of operation when all the switches 10a to 10f are open.

Abstract: A high-speed receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The high-speed receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the high-speed receiver assembly.

Abstract: A self-oscillating full-bridge driver IC, in which the high-side drivers each have a bootstrap capacitor, and a bootstrap circuit for pre-charging the bootstrap capacitors before starting up the oscillator or supplying control signals to the high-side drivers.

Abstract: A driving circuit for switches of direct current fan motor is disclosed. The driving circuit includes a plurality of switches, a first control circuit, and a second circuit. The switches are driven by a first pulse width modulation signal and a second pulse width modulation signal, and they are electrically connected with the direct current fan motor in a bridge manner. A third pulse width modulation signal is used to drive the first control circuit connected to at least one of the switches driven by the first pulse width modulation signal. A fourth pulse width modulation signal is used to drive the second control circuit connected to at least one of the switches driven by the second pulse width modulation signal. Especially, either the first pulse width modulation signal or the second pulse width modulation signal is selected as the third pulse width modulation signal or the fourth pulse width modulation signal.

Abstract: An H-bridge driver has a drive signal generating circuit for generating a square-wave signal as a drive signal. The H-bridge driver also has a waveform shaping circuit for blunting the waveform of the drive signal at the rising and trailing edges thereof. The waveform shaping circuit has a first circuit for generating, in a rising period of the square-wave signal fed thereto, a first current having a positive peak at the center of the rising period, a second circuit for generating, in a trailing period of the square-wave signal fed thereto, a second current having a negative peak at the center of the trailing period, and a capacitor to which the first and second currents are fed. The waveform shaping circuit outputs the voltage across the capacitor as its output voltage.

Abstract: A system and apparatus for controlling a motor or other multi-directional load using an H-bridge circuit having self-latching, high side switches. Thyristors are used as high side switches, and arranged to self-latch. The H-bridge thyristors are also arranged to automatically discontinue the triggering gate current upon the thyristor switch closing to conduct current, which advantageously terminates the flow of gate current as soon as it is no longer required.

Abstract: The circuit has a push-pull end stage which acts as an amplifier stage for digital signals. The push-pull end stage has two n-channel MOS transistors which function as source followers and two p-channel MOS transistors which also function as source followers. The gate terminals of the respective n-channel MOS transistors and p-channel MOS transistors are each controlled by an operational amplifier through drivers. A voltage that determines the setpoint value of the high level of the output of the push-pull end stage is present at the non-inverting input of one operational amplifier and a voltage that determines the low level of the output of the push-pull end stage is present at the inverting input of the other operational amplifier.

Abstract: A sensing device includes a Wheatstone bridge and a source of a stimulation configured to apply the stimulation across two electrodes of the Wheatstone bridge. The device also includes a timing sensitive circuit configured to detect timing of a signal appearing across one of the other electrodes of the bridge as a result of the stimulation being applied. The timing provides a way to read the sensor. The device can be powered remotely and data so read can be transmitted using the remote power. The timing sensitive circuit includes a comparator. The comparator provides a high logic signal for a time related to the reactance of one leg of the Wheatstone bridge, and that provides a reading of a differential sensor having elements in each leg of the bridge.

Abstract: A circuit (41) to provide drive voltages to a voice coil motor (VCM) (50) of a hard disk drive (10) has identical high and low side drivers (42, 44, 46, and 48) connected to the VCM (50). Each driver has an output FET (52) selectively connecting the VCM (50) to a control voltage (58). A Class-AB output pair (54 and 54′) in parallel with the output FETs (52 and 52′) provides continuous and linear Class-AB operation at the output node (60) around the crossover point, while the output FETs (52 and 52′) are kept not conducting. This approach offers extremely low level of crossover harmonic distortion. Each FET of the Class-AB pair (54 and 54′) is connected to a biasing FET (56 and 56′) to provide the desired Class-AB quiescent current. Preferably the output FET (52), quiescent current controlling FET (54), and biasing FET (56) are fully integrated.

Abstract: In a write driver circuit for switching the direction of a write current passing through a magnetic head or the like having an inductance component, an H-shaped bridge circuit is formed by using four NPN transistors in order to switch the write current at a high speed. Four switching means for controlling the base potentials of the four NPN transistors are provided and two switching means for rapidly decreasing the base potential of one of the two NPN transistors on the power source side, which is turned off when the write current passing through the magnetic head is switched are provided, thereby widening a voltage difference occurring between both terminals of the magnetic head.

Abstract: A method and circuit for driving power transistors arranged in series in a half bridge configuration allowing for excessive negative swing of an output node between the transistors in the half bridge configuration. The series transistors are connected between a first voltage source and a common potential. A second voltage reference source is also provided. A terminal is connected to a common point coupled to anodes of intrinsic diodes of driver circuits for the power transistors. The second voltage source is connected between the common potential and the terminal so as to shift the level of the common point such that the intrinsic diodes will not forward bias due to negative output node transients generated by diode forward recovery and stray inductances. The circuit of the invention can also be incorporated in an integrated circuit including a single chip, e.g., a silicon chip.

Abstract: A programmable load circuit operable to generate a plurality of test signals is described. The programmable load circuit comprises a diode bridge coupled between an input and an output. The diode bridge compares the voltage on the input to the voltage on the output. The programmable load circuit also comprises a plurality of current sources. A first set of the plurality of current sources are coupled to intermediate nodes of the diode bridge. Additionally, the programmable load circuit comprises a switching circuit coupled between the intermediate nodes of the diode bridge and a second set of the plurality of current sources. Furthermore, the programmable load circuit also comprises a load regulator coupled to the output and the intermediate nodes of the diode bridge. The load regulator is configured to reduce leakage current on the output.

Abstract: In a circuit for supplying a load with a direct voltage, a diode is connected in a current path for supplying the load, a step-up converter is connected in the current paths parallel with the diode, and a control unit drives the step-up converter according to predetermined criteria in order to supply the load at least partially via the step-up converter. Such a circuit has advantageous power consumption characteristics. In comparison to conventional circuits that require an expensive filter, this circuit is more economical and/or has a smaller structural size.

Abstract: A large-area electronic device comprises an array (1) of device elements (2,3) coupled to row and column conductors (A and B). The column conductors (B) are arranged in groups, (e.g M, M+1, M+2), and a column multiplexer circuit (C) couples the column conductors (B) of a respective group to a respective common terminal (5). The present invention provides a compatible multiplexer circuit (C) for the array (1), the operation of the circuit (C) using electrical switching rather than optical switching. This multiplexer circuit (C) for each column conductor comprises a diode bridge (SD3 to SD6) and may include a clamping switch (SD1, SD2). A signal is transmitted between the column conductor (B) and a common output terminal (5) in a first state of the diode bridge (SD3 to SD6). The potential of the column conductor (B) is clamped by the clamping switch (SD1, SD2) in a second state of the diode bridge.

Abstract: A half-bridge circuit where the transistors comprising the half-bridge are electronically interlocked--precluding cross-conduction; and high-side voltage generation and logic level translation are integral to the interlock mechanism.

Abstract: A driver circuit for a semiconductor test system generates test signals having predetermined voltage levels without being affected by stray capacitances.

Abstract: A multi-level driver circuit comprises: (a) an output buffer; (b) a first switch for applying a first analog level to the output buffer when in a closed state; (c) a second switch for applying a second analog level to the output buffer when in a closed state; (d) a third switch for applying a third analog level to the output buffer when in a closed state, wherein the third switch applies to the output buffer a capacitance which is dependent upon level when the third switch is in an open state and is unclamped; and (e) a clamping circuit for clamping the third switch such that the third switch applies to the output buffer a capacitance which is substantially independent of the third analog level when the third switch is in an open state and is clamped by the clamping circuit. The switches can be solid-state switches, such as diode bridges. Any number of switches can be provided, and more than one of the switches can be provided with a clamping circuit.

Abstract: A rectifying device comprising of a SRMOS, an inductor, and a control circuit is disclosed. The SRMOS has a gate, a drain, and a source. The gate of the SRMOS is connected to the output of the control circuit. The inductor is connected to the drain of the SRMOS. The control circuit uses two sense traces for determining the voltage (or current) passing between the inductor (that is connected to the drain) and the source of the SRMOS. Upon sensing a forward characteristic (voltage or current), the SRMOS forward biases to allow current to flow through the SRMOS. Upon sensing a reverse characteristic (voltage or current), the SRMOS reverse biases to cut off any current flow. Hysteresis is used in setting the forward biasing threshold voltage and the reverse biasing threshold voltage for the SRMOS. In reverse biasing and forward biasing the SRMOS, V.sub.gs is stepped (or curved) controlled to avoid false turn ON/OFF of the SRMOS.