Abstract: A circuit includes, in series between a first terminal and a second terminal of application of a power supply voltage, and first and second branches. The first branch includes a first transistor and a first current source coupled to the first transistor. The second branch includes a resistive element, a second transistor coupled to the resistive element and forming a current mirror with the first transistor and a second current source coupled to the second transistor. The resistive element conditions a threshold of detection of a variation of the power supply voltage.

Abstract: A peak detector for synchronized switch harvesting on inductor converter includes a comparator and a filter for filtering an input signal to the peak detector and for providing a filtered signal to an input of the comparator. The filter has differentiating and integrating transfer characteristics for low and high frequency ranges, respectively, of the input signal so that peaks of the input signal to the peak detector which have primarily frequency components in the low range cause a relatively strong variation of the filtered signal and peaks of the input signal to the peak detector which have primarily frequency components in the high range are substantially integrated and cause a relatively weak variation of the filtered signal. The relatively strong variation of the filtered signal crosses a threshold of the comparator, which is configured to generate an output signal indicating a relation of the filtered signal regarding the comparator threshold.

Abstract: An object of the invention is to reduce the power consumption of a semiconductor device that requires a plurality of reference potentials and a method of driving the semiconductor device. Disclosed is a semiconductor device having a potential divider circuit in which a potential supplied to a power supply line is resistively divided by resistors connected in series to the power supply line so that a desired potential is output through a switch transistor electrically connected to the power supply line. A drain terminal of the switch transistor is electrically connected to a gate terminal of a transistor provided in a circuit on the output side (or to one terminal of a capacitor) to form a node. The switch transistor has an off current low enough to hold the desired voltage in the node even when the potential is no more supplied to the power supply line.

Abstract: Methods and apparatus for detection and tracking of a signal envelope. The circuit comprises absolute value circuitry configured to receive data samples and output a first value corresponding to the magnitude of said data samples. An envelope tracker maintains an envelope output value and compares the first value to the current envelope output value and modifies the envelope output value based on said comparison to provide the envelope output value with predetermined attack and decay characteristics. The absolute value circuitry has a first input for receiving a first digital signal at a first sample rate and a second input for receiving an interpolated version of the first digital signal at a second sample rate which is higher than the first sample rate and outputs the first value based on the magnitudes of the samples received at the first input and the samples received at the second input.

Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.

Abstract: An envelope detector includes an input receiving a digital input signal indicative of a magnitude of a signal to be amplified by a power amplifier. A circuit is provided for generating an analog envelope signal based on the digital input signal. The envelope detector includes an output for outputting the analog envelope signal.

Abstract: Provided is a voltage regulator having low current consumption, which is capable of preventing a reverse current from flowing thereto from an output terminal (122), irrespective of a magnitude of a voltage of a VDD terminal (121). The voltage regulator has a circuit configuration in which voltage dividing resistors are not used for a comparator circuit for comparing the voltage of the VDD terminal (121) with a voltage of the output terminal (122), to thereby achieve lower current consumption.

Abstract: A serial data transmission system, includes a transmitting terminal for transmitting a data, a receiving terminal for receiving the data transmitted by the transmitting terminal, a first connecting capacitor connected between the transmitting terminal and the receiving terminal, and a second connecting capacitor connected between the transmitting terminal and the receiving terminal, wherein the transmitting terminal comprises a transmitting terminal driver unit and an amplitude detection unit connected with the transmitting terminal driver unit, the transmitting terminal driver unit outputs a pair of differential signals, the amplitude detection unit detects an amplitude variation of the differential signals output by the transmitting terminal driver unit, and outputs an indication signal indicating whether the transmitting terminal and the receiving terminal are properly connected with each other. A serial data transmission method is further provided.

Abstract: A cable detector includes one or more peak detectors that detect when a termination impedance is missing from the output of a line driver. A peak detection signal is asserted when signals on a transmission line exceed a threshold level. A fault condition is asserted when the peak detection signal is asserted for a sufficient length of time to indicate that an actual fault is detected. The time period required for detecting a lost or missing line termination is longer than the time periods for any one of the pathological conditions to avoid a false positive detection. After the peak detection signal is de-asserted, the fault condition will be maintained until another sufficient length of time has expired without a peak detection.

Abstract: Provided is a voltage regulator capable of securely preventing a reverse current from an output terminal (122) with lower current consumption, irrespective of magnitude of a voltage of a VDD terminal (121). Such a configuration is adopted that the voltage of the VDD terminal (121) and a voltage of the output terminal (122) of the voltage regulator are compared with each other with the use of a voltage generated between a transistor and a constant current circuit, to thereby reduce current consumption of a backup battery. Besides, such a configuration is also adopted that a gate of an output transistor is connected with the output terminal (122) based on an output of a comparator circuit, to thereby prevent the reverse current securely.

Abstract: A charge pump with a MOS-type capacitor, where the MOS-type capacitor is operated in an inversion region in which capacitance varies as a function of the frequency of the applied signal. The charge pump is switched to transfer charge from an input node to the capacitor and from the capacitor to an output node. During a transition interval, a relatively high frequency switching signal is used to lower the capacitance and increase efficiency. During a settling interval, a relatively low frequency switching signal is used, in which case the capacitance is higher, but similar to a level which would be seen if the capacitor was operated in an accumulation region. MOS capacitor dimensions and switching intervals are mutually optimized to provide high efficiency and required throughput. The charge pump may be configured as a voltage multiplier, divider, inverter or follower, for instance.

Abstract: A power detection system is disclosed that includes a detector circuit and a comparator circuit. The detector circuit includes a first transistor, a second transistor that is not identical to the first transistor, and a third transistor that is substantially identical to the first transistor. Each of the transistors is commonly coupled to a current source and is coupled to a differential input voltage. The comparator circuit is for providing an output that is representative of whether the input voltage is above or below a threshold voltage responsive to a difference between the first transistor and the second transistor.

Abstract: A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.

Abstract: A peak detector capable of rapidly detecting a peak value of a signal is provided. The peak detector includes first and second operational amplifiers and an auxiliary current source to detect two rail to rail signals. The first operational amplifier outputs a detection signal by buffering a first rail to rail input signal. The second operational amplifier outputs a control signal in response to a second rail to rail input signal and the detection signal. The auxiliary current source includes a terminal connected to an output terminal of the first operational amplifier and the other terminal connected to the first or second source voltage. The auxiliary current source operates in response to the control signal. The auxiliary current source supplies a current from the first source voltage to the output terminal in response to the control signal or supplies a path for discharging a current from the output terminal to the second source voltage.

Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.

Abstract: Disclosed is a signal output circuit comprising: a first transistor of an emitter follower configuration, which receives an input signal; a second transistor of an emitter follower configuration, which receives the input signal, and has an output connected to an external load (106); a comparator circuit which has an input pair connected via resistors to emitters of the first and the second transistors; a first current mirror circuit which has an input connected to an output of a first current source transistor and an output connected to an emitter of the first transistor; and a second current mirror circuit which has an input connected to a connection node of an output of a second current source transistor and an output of the comparator circuit, and has an output connected to an emitter of the second transistor.

Abstract: Aspects of the present invention include a method, apparatus and device for generating a power on reset (POR) signal in relation to the crossing point of two currents wherein at least one current is a quadratic function and the other is an exponential function, where each has a mathematical correlation to a function of a predetermined power supply voltage.

Abstract: To detect the peaks level of an incoming signal, the difference between the voltage level of the incoming signal and a voltage developed across a capacitor is amplified. The amplified difference signal is applied to a transconductor adapted to vary its output current in response to changes in the amplified difference signal. The variations in the current generated by the transconductor are used to change a current flowing through a current mirror that charges the capacitor. The voltage developed across the capacitor represents the detected peak. The capacitor is discharged to a predefined voltage level during the reset periods. A second amplifier receiving the capacitor voltage is optionally used to develop a voltage across a second capacitor that is not reset and thus carries only the detected peak levels.

Abstract: A peak detector provides repeatable and accurate measurements of the signal amplitude for variable frequencies of input signals. The peak detector includes a pulse edge generator circuit that generates a pulse edge signal in response to the signal peaks of an input signal and a sampler circuit that is triggered to sample the input signal by the pulse edge signal. The pulse edge generator circuit compares the input signal with a delayed version of the input signal to produce a differential signal and generates the pulse edge signal using the differential signal. An analog or digital sampler is triggered by the pulsed edge signal to measure the information, e.g., peak value, of the input signal. One or more delay circuits may be used to align the edges of the pulsed edge signal with the peaks of the input signal.

Abstract: Systems and methods for determining a slicing level which is used as a threshold to determine whether timeslots of an incoming data signal contain ones or zeros. The method of one embodiment comprises receiving a data signal, identifying a maximum level of the data signal, identifying a minimum level of the data signal, determining an average of the minimum and maximum levels, and then using the average of the minimum and maximum levels as a slicing level to identify bits of a data packet embodied in the data signal.

Abstract: Apparatus comprising a charge pump (20) with multiple independently regulated outputs (V1, V2) for providing different voltage levels at each of said outputs. The charge pump (20) comprises a low voltage input (12), on/off regulation (30), and at least two charge stages (11, 21) which arc arranged in a cascaded manner. Each charge stage (11, 21) comprises a stage capacitor (16, 26), a switch (S1, S3), and a buffer (15, 25) for pumping a bottom plate of the stage capacitor (16, 26).

Abstract: A peak voltage detector is used to detect the absolute value of the peak differential amplitude of a differential input signal. The peak voltage detector includes a differential amplifier receiving the differential input signal and generating a corresponding pair of differential output signals. The voltage detector also includes a capacitor on which an output signal is generated. A first differential comparator generates a first signal whenever the differential voltage from the differential amplifier is greater than the voltage of the output signal. A second differential comparator generates a second signal whenever the negative of the differential voltage from the differential amplifier is greater than the voltage of the output signal. A current source applies current to the capacitor responsive to receiving either the first or second signal. The amplitude of the feedback voltage is thus equal to the absolute value of the peak differential amplitude of the input signal.

Abstract: A peak detector is provided. Current switches are utilized and controlled by output of a plurality of error amplifiers respectively, such that charging currents are adjusted for a charge element in response to operations of the current switches respectively. Therefore, the overshooting charge is avoided and the time for charge is optimized.

Abstract: A peak detector can advantageously increase its bandwidth, i.e. its charging and discharging speed, while minimizing the ripple of its output signal by sensing the charging current of a storage device. In response to that charging current, the peak detector can control a discharge current, thereby accelerating its response. For example, the peak detector can reduce a discharge current in response to an increased charging current (which indicates a charging phase) and increase the discharge current in response to a decreased charging current (which indicates a discharge phase).

Abstract: A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.

Abstract: An exposure apparatus including a pulse light source, an exposure unit which exposes a substrate to a pattern with light from the pulse light source, a determination unit which determines necessity of maintenance for the pulse light source based on a pulse rate of the pulse light source within a predetermined period of time, and a decision unit which decides a timing of the maintenance based on a determination result of the determination unit.

Abstract: A diode-less peak detector comprises first and second comparators (U1, U2) for comparing an input signal (V) with a peak signal. The first comparator (U1) is connected such that the peak signal functions as a reference and the second comparator (U2) is connected such that the input signal functions as a reference. An inverter (U4) is provided for inverting the output of one of the first and second comparators. Means, such as an AND gate (U3) is provided responsive to the output of the inverter and the other of the first and second comparators so as to provide a switching signal. A MOSFET (Q1) is provided responsive to the switching signal and adapted to adjust the magnitude of the peak signal towards the magnitude of the input signal only when the magnitude of the input signal is greater than the magnitude of the peak signal.

Abstract: A peak detection circuit with double peak detection stages includes an analog peak detector, an analog-to-digital converter (ADC), and a digital peak detector. The analog peak detector receives an analog input signal, detects a peak value of the analog input signal with a first period, and outputs an analog peak signal. The ADC receives the analog peak signal and converts it into a digital signal. The digital peak detector receives the digital signal, detects the peak value of the digital signal with a second period longer than the first period, and outputs a digital peak signal. Therefore, the analog peak signal will not decay seriously due to the leakage and the digital peak signal can hold the digital peak value for a long time.

Abstract: A receiver portion of a radio includes an analog circuit for determining a peak amplitude in a way that eliminates or reduces the effects of frequency errors that are introduced by crystals within filters and other devices. A voltage follower and a current mirror in which a MOSFET coupled to an output node produces a voltage across its gate to source terminals whose value is a function of a sum of the gate to source voltages of two MOSFET devices that receive a logarithm of an I modulated channel and a logarithm of a Q modulated channel, respectively.

Abstract: An envelope detector system is disclosed for detecting an envelope in a system input signal. The envelope detector system includes an input node for receiving an input voltage signal, a transconducting amplifier for receiving the input voltage signal and producing an input current signal, a current mirror network for receiving the input current signal and for producing a current output signal, a capacitor for receiving the current output signal, and a rectifier output node for providing a rectifier output current signal. The capacitor is coupled to an input of the transconducting amplifier. The rectifier output current signal is fed into the current-mode wide-dynamic-range peak detector. The peak detector produces the envelope detector output current signal.

Abstract: In a serial interface unit (10) for the transmission and reception of data under the control of clock signals, the data are output from a data source to a data output (24) via an output driver (22). A transmit monitor (52) compares the data supplied by the data source with the data received at the data output (24) via the output driver (22). The transmit monitor outputs an error signal when the data so compared do not coincide.

Abstract: There is provided a signal detection circuit capable of detecting a signal at a high speed having small amplitude, and a data transfer control device and electronic equipment using the same. The signal detection circuit includes a peak hold circuit, a constant potential setting circuit, and a comparison circuit. The peak hold circuit holds a peak value of an input signal at a given node. The constant potential setting circuit always returns the potential at the given node changed by holding the peak value by the peak hold circuit to a constant potential at a time constant greater than the potential change caused by holding the peak value. The comparison circuit compares the potential at the node at which the peak value is held and which is slowly returned to the constant potential with a given reference level, and outputs the comparison result as a detection signal.

Abstract: A peak hold circuit that can operate to follow changes in peak value even if the changes are abrupt. The peak hold circuit (1) of the present invention has current control circuit (31), auxiliary switch element (25), and auxiliary constant current circuit (26). Current control circuit (31) counts the number of reference clock pulses RCK after output signal Vout becomes higher than analog voltage DI. When the number of clock pulses counted reaches a prescribed number or larger, auxiliary switch element (25) is turned on to operate auxiliary constant current circuit (26) to increase the amount of drop of output signal Vout per unit time. Consequently, even if output signal Vout becomes higher than the peak value of analog voltage DI, it is possible, by increasing the amount of drop of output signal Vout to make output signal Vout lower than analog voltage DI in a shorter amount of time than in the case in the conventional technology.

Abstract: An input buffer circuit for use with an analog-to-digital converter is provided. The input buffer circuit comprises a first amplifier configured with a second amplifier to improve the overall gain of the input buffer circuit. The first amplifier comprises a differential pair of transistors configured with a second pair of transistors comprising a current mirror arrangement, wherein one of the differential pair of transistors of the first amplifier is configured in a diode-connected arrangement to provide a first feedback loop, while the second amplifier comprises a differential pair of transistors configured with another pair of transistors also comprising a current mirror arrangement, with the second amplifier and the current mirror arrangement of the first amplifier comprising a second feedback loop.

Abstract: A peak detector circuit for detecting a peak output signal including an input circuit for inputting an input signal, a comparator for comparing the input signal and said peak output signal to generate a difference signal, a current source to generate a current in response to the difference signal, and a comparator to generate the peak output signal based on said current.

Abstract: A peak detector circuit providing a comparator that produces a low voltage output by pulling the output to common when an input signal exceeds a reference voltage and that produces a floating output by not conducting when the input signal does not exceed the reference voltage. A low output from the comparator generates a base current sufficient to drive a PNP transistor, which in turn drives current to a DC output capacitor. Until the input signal exceeds the reference voltage, neither the comparator nor the PNP transistor need to conduct and, consequently, the peak detector consumes relatively little power. The peak detector can be beneficially employed in a network interface unit or other transmission line unit.

Abstract: A peak detect-and-hold circuit eliminates errors introduced by conventional amplifiers, such as common-mode rejection and input voltage offset. The circuit includes an amplifier, three switches, a transistor, and a capacitor. During a detect-and-hold phase, a hold voltage at a non-inverting in put terminal of the amplifier tracks an input voltage signal and when a peak is reached, the transistor is switched off, thereby storing a peak voltage in the capacitor. During a readout phase, the circuit functions as a unity gain buffer, in which the voltage stored in the capacitor is provided as an output voltage. The circuit is able to sense signals rail-to-rail and can readily be modified to sense positive, negative, or peak-to-peak voltages. Derandomization may be achieved by using a plurality of peak detect-and-hold circuits electrically connected in parallel.

Abstract: Disclosed is a peak hold circuit wherein output current corresponding to the peak value of input current is obtained for input currents with little change in magnitude, at essentially higher speeds. Detected drain current and input current of a P-MOS FET are compared, a first reference potential is applied to an NPN transistor, and a second reference potential lower than the first reference potential by a predetermined voltage such that the NPN transistor and a PNP transistor are not simultaneously turned on, is applied to the PNP transistor. In the event that the detected current is greater than the drain current, the NPN transistor is turned on and the PNP transistor is turned off, in the event that the detected current is smaller than the drain current, the NPN transistor is turned off and the PNP transistor is turned on, and in the event that the detected current and the drain current are equal, the NPN transistor and the PNP transistor are both turned off.

Abstract: A system and method for temperature-compensated small signal peak detection. A small amplitude signal peak detector includes an exponential operator for generating a modulated signal through the application of an exponential function to the input signal. The peak detector also includes an averaging circuit for obtaining the average value of the modulated signal and an inverting offset stage for inverting the signal and removing an offset component. The resulting signal is directly proportional to the peak value of the input signal. The peak detector further includes a temperature compensation circuit for canceling the temperature-dependent effects introduced by the exponential operator and averaging means. The temperature compensation circuit is a thermistor with temperature-dependent characteristics matched to the temperature-dependent characteristics of the circuit when operated without a temperature compensation circuit.

Abstract: An improved crossover circuit for a V/I source includes a selector and a measurement circuit. The selector and measurement circuit both receive error signals indicative of differences between programmed and actual values of output voltage and current of the V/I source. In response to occurrences of predetermined events among the error signals, the measurement circuit activates the selector to pass one of the error signals to a control circuit for establishing a feedback loop. Different events cause different error signals to be selected, and hence cause different feedback loops of the V/I source to be activated. The improved crossover circuit provides increased control over the selection of feedback mode, and enhances the ability to individually optimize dynamic behavior of different feedback modes.

Abstract: An apparatus for tracking a peak level of an input signal includes a comparator for comparing the peak level of the input signal with a reference peak voltage signal. A sample and block circuit is coupled to the output of the comparator and is capable of sampling a portion of the input signal. The sampled portion of the input signal is defined by a smart window (timing window) which is received by the sample and block circuit. The sample and block circuit controls a charge pump that determines the level of the reference peak voltage signal. A method of generating a reference peak voltage signal includes receiving an input data, generating a timing window based upon the input data to define a sampling portion in the input data, comparing a level of the reference peak voltage signal with a level of the sampling portion in the input data, and determining a level of the reference peak voltage signal based upon the comparing step.

Abstract: A peak detector comprises a device for storing a value representing the currently detected peak amplitude (Cp,Cn), a circuit for detecting whether the input signal amplitude exceeds the stored value (D1 to D4), an apparatus for updating the stored value at a fast rate if the input signal amplitude exceeds the stored value by more than a given value (D1/V1, D3/V4), and an apparatus for updating the stored value at a slow rate if the input signal amplitude exceeds the stored value by less than the given value (D2/R2, D3/R3). Analogue and digital versions are described together with their application to data slicers in, for example, teletext decoders.

Abstract: A magnetic-field-to-voltage transducer includes a Hall element and a digitally gain-controlled Hall-voltage amplifier that produces an analog signal voltage Vsig having excursions of one polarity corresponding to the passing of magnetic articles. The gain of an AGC Vsig amplifier is only decreased in small sequential gain increments during an initial interval defined as that in which two excursions in Vsig have occurred, and the gain remains unchanged thereafter. Vsig is applied to the input of a peak-referenced-threshold signal detector that generates a binary output voltage, Vout, having transitions of one direction and the other direction corresponding respectively to the approach and retreat of the passing articles. The peak-referenced-threshold signal detector includes a dual-threshold-voltage comparator which is set to a large threshold at start-up.

Abstract: A detector circuit may detect a peak value of at least one input voltage and may provide the peak value as an output for use by other circuitry capable of being coupled to the detector circuit. Pairs of differential inputs may be employed, using n-channel transistors (in one example), and using diodes to capture the peak at a shared output node. Each differential pair has two constant current devices connecting the source/drain paths to the terminal of a voltage supply. This circuit enables the use of high input voltages which may be at or near the upper power supply (e.g., V.sub.DD). The circuit is in effect a negative peak detector, capturing the most negative value of at least one input level and holding that level, with a slow leakage of the held value back toward the upper voltage supply with a time constant that is generally set much slower than the input signal transition frequency. A similar circuit may be implemented using p-channel transistors in the differential pairs, to detect positive peaks.

Abstract: A data slicer which effectively compensates for wobble and asymmetrical phenomena due to optical and electrical characteristics of a disk. The data slicer includes a comparator for outputting a pulse signal by comparing an RF signal detected by an pickup device with a slice reference value, a low pass filter for low-pass-filtering the pulse signal output from the comparator, a first differential amplifier for detecting the difference between the output of the low pass filter and a predetermined reference value (Vref), and providing the detected difference as the slice reference value of the comparator, a peak detector for detecting a peak value of the RF signal, a bottom detector for detecting a bottom value of the RF signal, and an average value detection portion for detecting an average value of the peak value detected by the peak detector and the bottom value detected by the bottom detector, and adding the detected value to the slice reference value of the comparator.

Abstract: It is an object of the invention to provide a peak detector with improved precision for low amplitude AC signals for a broad range of input frequencies.

Abstract: A peak detector is provided with a comparator and a storage capacitor coupled to the output of the comparator. An analog input signal is supplied via an input capacitor to the inverting input of the comparator. The non-inverting input of the comparator receives an output signal produced by an output buffer arranged in a feedback loop of the comparator. A level shifter is coupled in the feedback loop to dynamically adjust an input signal supplied to the output buffer in accordance with application requirements. The operation of the peak detector is controlled by non-overlapping clock signals supplied to switches at the input and inner feedback loop of the comparator to cancel offset caused by the comparator and output buffer.

Abstract: A precision analog circuit ensures precision matching between two or more resistive elements. In order that the two or more resistive elements are truly matched, a first electrical value, such as V.sub.DS, of the two or more resistive elements are equal and a second electrical value, such as V.sub.GS, of the two or more resistive elements are equal so that a ratio of the first resistive element to the second resistive element is a predetermined value regardless of the voltage coefficients of the resistive elements.

Abstract: A peak detector that is particularly suitable for measuring the peak value of an RSSI-signal in a digital communication device. The peak detector includes a peak value storage capacitor which is charged by a high current or by a low current. When the RSSI-signal is greater than the output voltage of the peak detector, the storage capacitor is charged with the low current. When the RSSI-signal is substantially greater than the output voltage of the peak detector, the storage capacitor is charged with the high current. Herewith, it is achieved that the peak value of the RSSI-signal is determined quickly, without any overshoot, i.e. the peak value is determined accurately.

Abstract: A quad burst servo demodulator with adjustable slew rate for hard disk drives. The quad burst servo demodulator includes a peak voltage detecting system for detecting the peak voltages of an input signal, a plurality of storage capacitors for holding voltages proportional to the peak voltages observed by the peak voltage detecting system, and a programmable current source for charging (via an adjustable slew rate) the storage capacitors to voltages proportional to the detected peak voltages of the input signal.