Maximum Or Minimum Amplitude Patents (Class 327/58)
  • Patent number: 10190890
    Abstract: A capacitance-to-voltage conversion circuit including a variable capacitance element, an integration circuit, and first and second sample and hold circuits. Capacitance value of the variable capacitance element varies depending on a physical quantity. The integration circuit outputs a voltage as a result of integration. The first sample and hold circuit samples and holds the voltage. The second sample and hold circuit samples and holds the sampled voltage and performs a simultaneous sampling operation in synchronism with the first sample and hold circuit at the same period as at least an initial sampling period. The second sample and hold circuit performs a sampling operation at a rear-end period in a sampling period of the first sample and hold circuit other than the sampling period.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 29, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tsuyoshi Okami
  • Patent number: 10024153
    Abstract: A peak hold circuit configured for use in a downhole sensor includes a long tail pair circuit, a correction circuit, and a current mirror circuit. The current mirror circuit includes two current mirrors connected to a long tail pair formed by a first transistor and a second transistor. The current mirror also includes a first resistor and a second resistor connected to a third transistor. The first transistor is connected to a correction transistor of the correction circuit. The value of the first resistor is selected to be essentially equal to the same value as the second resistor so that when the long tail pair is balanced, the current flowing through a collector of the second transistor is equal to the current flowing through the first transistor, causing the correction transistor to switch off.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: July 17, 2018
    Assignee: Sondex Wireline Limited
    Inventor: Kenneth Tomkins
  • Patent number: 9973095
    Abstract: The present disclosure is directed to a high power factor quasi resonant converter. The converter converts an AC power line input to a DC output to power a load, generally a string of LEDs. The power input is fed into a transformer being controlled by a power switch. The power switch is driven by a controller having a shaping circuit. The shaping circuit uses a current generator, switched resistor and capacitor to produce a sinusoidal reference voltage signal. The controller drives the power switch based on the voltage reference signal, resulting in a sinusoidal input current in a primary winding of the transformer, resulting in high power factor and low total harmonic distortion for the converter.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: May 15, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Claudio Adragna, Giovanni Gritti
  • Patent number: 9954485
    Abstract: A circuit including an amplitude detector. The amplitude detector includes an input to receive a signal having an amplitude voltage and a first pair of transistors configured in parallel. The input is coupled to the control terminal of at least one transistor of the first pair. The amplitude detector includes a first node providing a voltage indicative of the amplitude voltage. The first node is in series with each of the first pair of transistors. The circuit includes a compensation circuit. The compensation circuit includes a second pair of transistors configured in parallel and a second node. The second node is coupled in series with each transistor of the second pair. The circuit includes an amplifier including a first amplifier input coupled to the first node and a second amplifier input coupled to the second node.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: April 24, 2018
    Assignee: NXP USA, INC.
    Inventor: Edevaldo Pereira Da Silva, Jr.
  • Patent number: 9939467
    Abstract: An RF peak-detector circuit can operate over a wide range and can compensate or correct an output voltage error term that depends on the thermal voltage and the input signal voltage. At or near a minimum value of the input signal voltage range, such compensation can include a scaled base-emitter ratioing of bipolar junction transistors used to generate the output voltage, each of which can be biased by a primary current. At or near a maximum value of the input signal voltage range, this can include using an auxiliary bias current circuit that can shift auxiliary bias current between these bipolar junction transistors. The auxiliary bias current circuit can include scaled bipolar junction transistors in a cross-coupled configuration and an equivalent resistance circuit between emitters of the cross-coupled BJTs. This can provide a robust approach for improving the accuracy of an RF peak-detector circuit over a wide range.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: April 10, 2018
    Assignee: Analog Devices, Inc.
    Inventor: Alexandru Aurelian Ciubotaru
  • Patent number: 9817041
    Abstract: A peak detector circuit comprises a first output coupled to ground by a first load and to emitter terminals of first and second switching devices. A second output is coupled to ground by a second load and to emitter terminals of third and fourth switching devices. A third output is coupled to a supply voltage node by a third load and to collector terminals of the first and second switching devices. A fourth output is coupled to the supply voltage node by a fourth load and to collector terminals of the third and fourth switching devices. The first, second, third, and fourth switching devices have control terminals which are biased with a common bias voltage. The first, second, third and fourth load are selected so that R1=R2=?f*R3=?f*R4, with R1, R2, R3, R4 being a resistance of the first, second, third and fourth loads, respectively, and ?f a common-base current gain of the switching devices.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: November 14, 2017
    Assignee: NXP USA, Inc.
    Inventor: Yi Yin
  • Patent number: 9673797
    Abstract: A peak detector using a charge pump is provided. The peak detector includes a differential amplifier configured to receive an input signal to be detected through an input node and amplify the received signal; a current control logic configured to create two or more current control signals by comparing a signal output from the differential amplifier with two or more reference voltages; a mirror current source portion comprising two or more mirror current sources configured to be driven respectively by the current control signals from the current control logic; a capacitor configured to be charged or discharged by currents output from the mirror current sources; and a reset circuit configured to reset a voltage of the capacitor.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: June 6, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young Ho Kim, Eui Suk Jung
  • Patent number: 9585194
    Abstract: A system and method for controlling the output power of a heat source. The system includes a user interface so that a user may select the power required from the heat source, a power supply, and a controller that receives a rectified signal having a work ratio that corresponds to a nominal voltage of an alternating voltage signal corresponding to a phase of a power supply. The controller is configured to control the output power of the heat source in accordance with the power selected by the user, and modifies, if necessary, the work cycle of a power signal linked to the heat source in accordance with the work ratio in order to compensate possible differences in the nominal voltage between different power supplier.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: February 28, 2017
    Assignee: COPRECITEC, S.L.
    Inventor: Gonzalo Fernández Llona
  • Patent number: 9525571
    Abstract: A method for calibrating signal swing and a trip reference voltage. The signal swing of a system can be calibrated in a symmetric or asymmetric technique through adjustment of a drive parameter such as a supply voltage for a transmitter or a drive termination. The trip reference voltage of the system can also be calibrated in a symmetric or asymmetric technique through sampling of a data pattern to determine an ideal level of the trip reference voltage.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 20, 2016
    Assignee: Lattice Semiconductor Corporation
    Inventors: Alan T. Ruberg, Srikanth Gondi
  • Patent number: 9515705
    Abstract: A near field communications (NFC) device is disclosed that detects an envelope of a radio frequency (RF) signal. The NFC device includes a peak detector that determines the envelope of the RF signal. The peak detector compares a first differential signal voltage to a second differential signal voltage. The peak detector delays a rising edge of a first differential signal and provides the first differential signal voltage to the peak detector output when the first differential signal voltage is greater than the second differential signal voltage. The peak detector delays a falling edge of a second differential signal and provides the second differential signal voltage to the peak detector output when the second differential signal voltage is greater than the first differential signal voltage.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: December 6, 2016
    Assignee: Broadcom Corporation
    Inventors: Humberto Andrade da Fonseca, Lance Rhys Trodd, Robin Wyndham John Wilson, David John Miles
  • Patent number: 9509285
    Abstract: Aspects of the disclosure provide a circuit having a pulse latch circuit and an enable circuit. The latch circuit is configured to receive a first signal at an input lead and drive the first signal to an output lead in response to an enable signal. The enable circuit is configured to be active to generate the enable signal to enable the latch circuit to receive the first signal when the first signal is different from a second signal on the output lead and is configured to default the enable signal to suppress the first signal so as not to be received at the latch circuit when the first signal is the same as the second signal.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: November 29, 2016
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Gideon Paul
  • Patent number: 9470725
    Abstract: By powering an electronic component operating in an ultra-low power mode from a pre-charged measuring capacitor and measuring the time to discharge the capacitor to a trip voltage level, measurement data can be obtained. In some implementations, the capacitance of the capacitor can be obtained by adding a known current to the unknown current drawn from the capacitor and calculating the capacitance using a mathematical formula.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: October 18, 2016
    Assignee: Atmel Corporation
    Inventor: Ingar Hanssen
  • Patent number: 9369147
    Abstract: An analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: June 14, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Peter Spevak
  • Patent number: 9319041
    Abstract: A squelch detector receives a first input signal, a second input signal VM, a first reference voltage and a second reference voltage. The first input signal and the second input signal are collaboratively defined as a differential input signal. The difference between the first reference voltage and the second reference voltage is defined as a squelch threshold. According to the squelch threshold, the squelch detector generates a detected signal to indicate whether the differential input signal is valid.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: April 19, 2016
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO.
    Inventors: Ju-Chieh Wang, Ting-Hsu Chien, Da-Rong Huang
  • Patent number: 9276567
    Abstract: A detection circuit includes a differential circuit including a pair of differential transistors configured to receive the input differential signal and a first current source, the pair of the differential transistors having a common output terminal connected to the first current source, a hold capacitor connected between the common output terminal and a reference potential for generating a hold potential, a level sensing circuit configured to sense a voltage level of the input differential signal and output a switching signal, and a switch configured to receive the switching signal and electrically connect the common output terminal and a second current source when the switching signal exceeds a threshold level being lower than the hold potential by a predetermined amount, and electrically disconnect the common output terminal and the second current source when the switching signal stays lower than the threshold level.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: March 1, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Taizo Tatsumi
  • Patent number: 9209763
    Abstract: A differentiator generates a time derivative signal from a time-variable signal. A transconductance amplifier generates a biasing control signal as a function of the time derivative signal. A supply network functions to supply the differentiator and transconductance amplifier. The supply network is driven by the biasing control signal output from the transconductance amplifier. With this configuration, speed of operation of the differentiator and transconductance amplifier vary with the supply provided by the supply network, and the supply is modulated as a function of the received time-variable signal.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: December 8, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Valeria Bottarel, Giulio Ricotti, Sandro Rossi
  • Patent number: 9178476
    Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: November 3, 2015
    Assignee: Broadcom Corporation
    Inventors: Amir Hadji-Abdolhamid, Janice Chiu
  • Patent number: 9172563
    Abstract: A circuit can include multiple data input ports and data output ports, pickoff tees coupled therebetween, and a resistive network coupled between the pickoff tees. A differential signal generator can be coupled with the resistive network and the pickoff tees. Resistances of the pickoff tees and resistive network can be selected such that impedances looking into the data input ports and data output ports are matched to a desired system impedance.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: October 27, 2015
    Assignee: Tektronix, Inc.
    Inventor: Keith J. Bertrand
  • Patent number: 9083319
    Abstract: An oscillator and the control method thereof. The oscillator includes an oscillation unit to receive a first current and to generate an oscillating signal according to the first current, a frequency-to-voltage converter to receive the oscillating signal and to generate a converted voltage according to a frequency of the oscillating signal, and a voltage-to-current converter to receive the converted voltage and to generate the first current according to the converted voltage, wherein the first current is modulated from a first value to a second value after the initiation of the oscillation unit.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: July 14, 2015
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Ming-Yuh Yeh, Chen-Chih Huang, Tay-Her Tsaur
  • Patent number: 9059807
    Abstract: The invention provides a linear burst mode receiver comprising a first amplifier connected to a photodiode adapted to detect an optical input burst signal, a second amplifier connected to said photodiode; and means for deriving the peak input current of the detected burst signal using said second amplifier. The invention further provides means for using the derived peak input current to adjust the gain of the first amplifier during the preamble of each burst, such that the output voltage swing of the first amplifier equals a given reference, independent of the strength of the optical input burst signal. The usage of the fast feed-forward automatic gain control mechanism solves the problems with gain switching and non-linearity prevalent in today's burst-mode receivers.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: June 16, 2015
    Assignee: UNIVERSITY COLLEGE CORK—NATIONAL UNIVERSITY OF IRELAND
    Inventors: Peter Ossieur, Paul Townsend
  • Publication number: 20150123711
    Abstract: A method of peak detection applicable to complex in-phase and quadrature phase signals in a digital radio receiver where the incoming signal is divided into a plurality of frames. Each frame is then further divided into a plurality of smaller blocks, and the signal peak is determined in each block individually followed by selecting the peak signal value from the said blocks.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Venkateswara Rao Mandela, Thomas Sojan PJ
  • Patent number: 8988112
    Abstract: An activity detector for a differential signal formed by two components may include a current source connected to a power supply line, and a first transistor has a drain being powered by the current source, and has a source that forms a first input terminal receiving a first component of the differential signal. A second transistor has a drain being powered by the current source, and has a source forms a second input terminal receiving the second component of the differential signal. A bias circuit applies a potential to the gates of the first and second transistors, establishing a balance condition where all the current from the current source is distributed between the two transistors when the first and second input terminal potential is equal to a threshold value. An activity indication terminal is taken from the drains of the first and second transistors.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 24, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Fouad Bissane, Hugo Gicquel
  • Patent number: 8988111
    Abstract: Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: March 24, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jeff Rysinski, Yibing Michelle Wang, Sang-Soo Lee
  • Patent number: 8890510
    Abstract: Circuits and methods for fast detection of a low voltage in the range of few ?Volts have been achieved. In a preferred embodiment the low voltage represents a current via a shunt resistor and the circuit is used to generate a digital wake-up signal. In regard of the wake-up application the circuit invented is activated periodically and in case of a certain level of the voltage drop, e.g. 50 ?V, at the shunt resistor. The time required for a measurement of the voltage drop is inclusive calibration and integration time far below 1 ms. It is obvious that the circuit invented can be used for any measurements of very small voltages.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: November 18, 2014
    Assignee: Dialog Semiconductor GmbH
    Inventors: Horst Knoedgen, Francesco Marraccini
  • Patent number: 8884654
    Abstract: A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mirko Gravati, Claudio Cantoro
  • Patent number: 8872550
    Abstract: An apparatus and a method for processing a signal, and for estimating a point corresponding to a maximum slope from an envelope of an input signal, are provided. A signal processing apparatus includes an envelope detecting unit configured to detect an envelope of an input signal. The signal processing apparatus further includes a correcting unit configured to correct slopes, each of the slopes being between respective points of the envelope, based on information on a clipping interval of the envelope. The signal processing apparatus further includes an estimating unit configured to estimate a point, of the envelope, in which a corrected slope, among the corrected slopes, includes a maximum value.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ui Kun Kwon, Sang Joon Kim, Seung Keun Yoon
  • Patent number: 8872549
    Abstract: A circuit includes multiple input sub-circuits coupled to a common output node. Each input sub-circuit includes a transconductance cell. A diode is coupled between the output of the transconductance cell and a common output node. A feedback circuit is coupled between the common output node and a second input of the transconductance cell. A voltage follower is coupled between the common output node and a reference voltage, with an input coupled to the output of the transconductance cell.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: October 28, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Sandro Herrera, Moshe Gerstenhaber
  • Patent number: 8842722
    Abstract: Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Timothy O. Dickson, Rui Yan Matthew Loh
  • Patent number: 8823417
    Abstract: A device and method for current detecting and discriminating is disclosed. The device includes a differential receiver configured to receive a current input, a positive-side Schmitt trigger in communication with the input stage, wherein the positive-side Schmitt trigger is configured to receive an output provided by the input stage, and wherein the positive-side Schmitt trigger is configured to create a positive-side Schmitt trigger output representative of the current input, and a negative-side Schmitt trigger in communication with the input stage, wherein the negative-side Schmitt trigger is configured to receive the output provided by the input stage, and wherein the negative-side Schmitt trigger is configured to create a negative-side Schmitt trigger output representative of the current input.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: September 2, 2014
    Assignee: Siemens Industry, Inc.
    Inventor: Lev Michael Barsky
  • Publication number: 20140232435
    Abstract: A circuit includes multiple input sub-circuits coupled to a common output node. Each input sub-circuit includes a transconductance cell. A diode is coupled between the output of the transconductance cell and a common output node. A feedback circuit is coupled between the common output node and a second input of the transconductance cell. A voltage follower is coupled between the common output node and a reference voltage, with an input coupled to the output of the transconductance cell.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 21, 2014
    Applicant: Analog Devices, Inc.
    Inventors: Sandro HERRERA, Moshe GERSTENHABER
  • Patent number: 8791691
    Abstract: A signal detector includes a summation unit connected to offset first and second input signals representing a differential input signal into two offset pairs of first and second signals. The signal detector also includes a detection unit connected to select the first signal from one of the offset pairs of first and second signals and the second signal from the other of the offset pairs in an overlap portion of the first and second signals to form a complementary pair of overlap signals and provide a differentially peak-detected output signal from the complementary pair of overlap signals. Additionally, the signal detector includes a comparator connected to provide a detection output signal corresponding to the differentially peak-detected output signal and a reference signal. A method of operating a signal detector is also included.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: July 29, 2014
    Assignee: LSI Corporation
    Inventor: Zichuan Cheng
  • Patent number: 8786297
    Abstract: A circuit and method for detecting a brown-out condition and providing a feed-forward transfer function in a power supply circuit. A comparison circuit is coupled to a delay element through a latch. A second delay element is connected between the first delay element and an input of the latch. The output of the first delay element is connected to a clamping circuit via a logic circuit. A first voltage is compared with a reference voltage to generate a comparison voltage, which is transmitted through the latch and the first delay element. The comparison voltage is monitored at an output of the first delay element. A brown-out condition occurs if the comparison voltage being monitored at the output of the first delay element results from the first voltage being less than the reference voltage.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: July 22, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Joel Turchi, Karel Ptacek, Radim Mlcousek
  • Patent number: 8781414
    Abstract: An envelope detector includes an input receiving a digital input signal indicative of a magnitude of a signal to be amplified by a power amplifier. A circuit is provided for generating an analog envelope signal based on the digital input signal. The envelope detector includes an output for outputting the analog envelope signal.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: July 15, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Krzysztof Dufrene, Harald Pretl, Patrick Ossmann
  • Patent number: 8773168
    Abstract: A maximum voltage selection circuit and method and a sub-selection circuit are provided. The maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N channels of input voltages. The peripheral signal circuit provides an operating mode signal and a reference voltage to the selection circuit including N sub-selection circuits coupled to the N channels of input voltages respectively. A sub-selection circuit determines its operating mode according to the operating mode signal. In the operating mode, when an input voltage of a sub-selection circuit is larger than the reference voltage, the sub-selection circuit sets itself to the output enable state and sets other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: July 8, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Lei Huang
  • Patent number: 8761300
    Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 24, 2014
    Assignee: Broadcom Corporation
    Inventors: Ahmad Mirzaei, Hooman Darabi
  • Publication number: 20140077785
    Abstract: A method of maximum power point tracking for a photovoltaic module system is disclosed. The photovoltaic module system may comprise a photovoltaic module array comprising a plurality of identical photovoltaic modules, and the tracking method may comprise: detecting system parameters and environmental parameters of the photovoltaic module array; estimating a first voltage coefficient of one photovoltaic module according to the system parameters and the environmental parameters; estimating a plurality of second voltage coefficients of the photovoltaic module array according to the first voltage coefficient with different shading ratios; estimating a plurality of local maximum power point powers according to corresponding second voltage coefficients; and determining a whole maximum power point by comparing the local maximum power point powers with one another.
    Type: Application
    Filed: March 18, 2013
    Publication date: March 20, 2014
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Joe Air Jiang, Jen Cheng Wang, Yu Li Su, Kun-Chang Kuo, Jyh-Cherng Shieh
  • Publication number: 20140002139
    Abstract: A maximum voltage selection circuit and method and a sub-selection circuit are provided. The maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N channels of input voltages. The peripheral signal circuit provides an operating mode signal and a reference voltage to the selection circuit including N sub-selection circuits coupled to the N channels of input voltages respectively. A sub-selection circuit determines its operating mode according to the operating mode signal. In the operating mode, when an input voltage of a sub-selection circuit is larger than the reference voltage, the sub-selection circuit sets itself to the output enable state and sets other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS.
    Type: Application
    Filed: June 10, 2013
    Publication date: January 2, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventor: Lei Huang
  • Patent number: 8614592
    Abstract: To detect the peaks level of an incoming signal, the difference between the voltage level of the incoming signal and a voltage developed across a capacitor is amplified. The amplified difference signal is applied to a transconductor adapted to vary its output current in response to changes in the amplified difference signal. The variations in the current generated by the transconductor are used to change a current flowing through a current mirror that charges the capacitor. The voltage developed across the capacitor represents the detected peak. The capacitor is discharged to a predefined voltage level during the reset periods. A second amplifier receiving the capacitor voltage is optionally used to develop a voltage across a second capacitor that is not reset and thus carries only the detected peak levels.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: December 24, 2013
    Assignee: Marvell International Ltd.
    Inventors: Qiang Luo, Yingxuan Li, Sriharsha Annadore, Pantas Sutardja
  • Patent number: 8604837
    Abstract: A detector circuit, has a first diode, to an anode of which an AC signal is input and to which a constant voltage is supplied, a second diode, to an anode of which the constant voltage is supplied, and a difference current generation circuit, which generates the difference current between a first current flowing in the first diode and a second current flowing in the second diode.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: December 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroyuki Nakamoto
  • Patent number: 8604836
    Abstract: A detector circuit, has a first diode, to an anode of which an AC signal is input and to which a constant voltage is supplied, a second diode, to an anode of which the constant voltage is supplied, and a difference current generation circuit, which generates the difference current between a first current flowing in the first diode and a second current flowing in the second diode.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: December 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroyuki Nakamoto
  • Patent number: 8581633
    Abstract: A peak hold circuit includes an input node configured to receive an input waveform, a peak hold component coupled to the input node and configured to sample and hold a peak value of the input waveform at a peak value node, a reset node configured to receive a reset signal, a reset circuit coupled to the peak hold component and the reset node, the reset circuit configured to reset the peak hold value, and a voltage clamp coupled to the input node, the reset circuit, and the reset node, the voltage clamp configured to clamp the input node in response to the reset signal.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: November 12, 2013
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Evropej Alimi
  • Patent number: 8497711
    Abstract: An envelope detecting method performing squelch detection on a pair of differential signal includes: by a voltage divider, providing a real-time reference signal according to a sum of the pair of differential signals; and comparing two comparison signals associated with the real-time reference signals and the pair of differential signals to generate a squelch detection signal.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 30, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventor: Yi-Cheng Hsieh
  • Publication number: 20130181744
    Abstract: A peak hold circuit includes an input node configured to receive an input waveform, a peak hold component coupled to the input node and configured to sample and hold a peak value of the input waveform at a peak value node, a reset node configured to receive a reset signal, a reset circuit coupled to the peak hold component and the reset node, the reset circuit configured to reset the peak hold value, and a voltage clamp coupled to the input node, the reset circuit, and the reset node, the voltage clamp configured to clamp the input node in response to the reset signal.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 18, 2013
    Applicant: HAMILTON SUNDSTRAND CORPORATION
    Inventor: Evropej Alimi
  • Publication number: 20130162296
    Abstract: A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 27, 2013
    Applicant: STMICROELECTRONICS S.R.L.
    Inventor: STMICROELECTRONICS S.R.L.
  • Publication number: 20130162297
    Abstract: A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 27, 2013
    Applicant: STMICROELECTRONICS S.R.L.
    Inventor: STMICROELECTRONICS S.R.L.
  • Patent number: 8421504
    Abstract: A microcomputer includes a first comparator which compares a voltage to be monitored, with a first reference voltage, a second comparator which compares the voltage to be compared, with a second reference voltage, and an interrupt control circuit which monitors the voltage to be monitored by the first and second comparators in parallel and, when a preset condition is satisfied, generates an interrupt signal.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: April 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Masahide Ouchi
  • Publication number: 20130090075
    Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching to devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.
    Type: Application
    Filed: November 29, 2012
    Publication date: April 11, 2013
    Applicant: Broadcom Corporation
    Inventor: Broadcom Corporation
  • Patent number: 8405438
    Abstract: In a semiconductor circuit, a high frequency level detecting unit detects a level of a high frequency component adjusted with a first adjusting unit, and a first control unit controls a first gain of the adjusting unit according to the level of the high frequency component thus detected. Further, a low frequency level detecting unit detects a level of a low frequency component adjusted with a second adjusting unit. A second control unit controls a second gain according to the level of the high frequency component and the level of the low frequency component thus adjusted, so that a difference between the level of the high frequency component adjusted with the first adjusting unit and the level of the low frequency component adjusted with the second adjusting unit becomes smaller than a specific level determined in advance.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: March 26, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Norihiko Satani, Yuichi Matsushita, Takahiro Imayoshi
  • Patent number: 8405427
    Abstract: A circuit design configured to process a differential input signal is provided. A first floating capacitor ladder is configured to receive the positive of the differential input signal and is connected to a first switched capacitor network through phase one controlled switches. A second floating capacitor ladder configured to receive the negative of the differential input signal and is connected to a second switched capacitor network through other phase one controlled switches. A reference resistor ladder is connected to the first switched capacitor network through phase two controlled switches to provide voltage references and connected to the second switched capacitor network through other phase two controlled switches to provide the voltage references.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventor: Pier Andrea Francese
  • Patent number: 8373445
    Abstract: This transmission input circuit is provided with an adjustment processing section which turns ON a switch at an empty timing where transmission current from a slave device is not flowing, to allow a reference current to flow from a constant current circuit to a current detection resistor, generates in the current detection resistor a target adjustment voltage, in which a threshold voltage corresponding to the reference current is added to a load current detection voltage corresponding to the load current, and adjusts a digital value so that a reference voltage output from a digital variable resistor matches with the target adjustment voltage.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: February 12, 2013
    Assignee: Hochiki Corporation
    Inventor: Mitsuhiro Kurimoto