Abstract: A power supplying circuit includes a first high-voltage switch, a first low-voltage switch, a second high-voltage switch, a second low-voltage switch, and a controller circuit. The first high-voltage switch receives a first input voltage and generates a first node voltage. The first low-voltage switch is coupled between the first high-voltage switch and an output terminal. The second high-voltage switch receives a second input voltage and generates a second node voltage. The second low-voltage switch is coupled between the second high-voltage switch and the output terminal. The controller circuit controls the first high-voltage switch, the first low-voltage switch, the second high-voltage switch, and the second low-voltage switch according to the first node voltage and the second node voltage such that an output voltage is outputted to the output terminal.

Abstract: A device performing a power gating operation includes a switch control signal generation circuit and a power gating circuit. The switch control signal generation circuit controls an operation that generates a first switch control signal and a second switch control signal from a mode signal based on a comparison result of a first power source voltage and a second power source voltage until a mode register set operation is performed after a power-up period ends. The power gating circuit drives a power source voltage to the first power source voltage or the second power source voltage based on the first switch control signal and the second switch control signal.

Abstract: Disclosed is technology for controlling a bias using an integrated circuit (IC) instead of using a pilot tone. A bias control apparatus includes a photodetector configured to convert at least a portion of data included in an output from an optical modulator to an electrical signal; a power detector configured to convert a root mean square (RMS) value of an amplitude of the converted data to an analog voltage; a comparator configured to compare the output voltage and a pre-stored track hold value; and a bias controller configured to control a bias voltage to be within a preset range from an optimal voltage based on the comparison result.

Abstract: A chopper comparator with a novel structure is provided. The comparator includes an inverter, a capacitor, a first switch, a second switch, and a third switch. An input terminal and an output terminal of the inverter are electrically connected to each other through the first switch. The input terminal of the inverter is electrically connected to one of a pair of electrodes of the capacitor. A reference potential is applied to the other of the pair of electrodes of the capacitor through the second switch. A signal potential input is applied to the other of the pair of electrodes of the capacitor through the third switch. A potential output from the output terminal of the inverter is an output signal. A transistor whose channel is formed in an oxide semiconductor layer is used as the first switch.

Abstract: An integrated circuit (IC) with voltage regulation includes high power and low power domains, low and high voltage regulators and a low power regulator. The low voltage regulator powers the high and low power domains when the IC is in a HIGH power mode. The low power regulator receives a voltage from a high voltage regulator and powers the low power domain when the IC is in a LOW power mode. The IC includes a switching module that disconnects the low voltage regulator from the low power domain when the output voltage of the high voltage regulator is lower than a threshold voltage during power-up and connects the low voltage regulator to the low power domain when the voltage regulated by the high voltage regulator exceeds the threshold voltage.

Abstract: A guided wave radar level measurement instrument comprises a probe defining a transmission line for sensing material level. A probe interface circuit is connected to the probe for generating pulses on the transmission line and receiving reflected signals from the transmission line. The probe interface circuit comprises a transmit pulse generator for generating a transmit pulse, a sample pulse generator for generating a sample pulse, and a delay lock loop for controlling the transmit and sample pulse generators. The delay lock loop is controlled by a pulse repetition frequency having a duty cycle less than 50%.

Abstract: A comparator having first and second stages can provide component offset compensation and improved dynamic range. The first stage can receive first and second input signals and produce first and second output signals. The second stage can be coupled to the first stage to receive the first and second output signals at first and second input terminals of the second stage. The second stage can provide a voltage to the first and second terminals that differs from the supply voltage by less than a voltage of a diode drop. The comparator is operable to receive input voltages that reach the supply voltage.

Abstract: An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.

Abstract: An apparatus is provided. The apparatus comprises backend circuitry and pairs of redundant input circuits. Each pair of redundant input circuits is configured to form a differential pair of transistors, and each redundant input circuit includes a multiplexer and a set of transistors. The multiplexer is coupled to the backend circuitry, and each transistor from the set of transistors has a first passive electrode, a second passive electrode, and a control electrode. The first passive electrode of each transistor from the set of transistors is coupled to the multiplexer, and the control electrodes from the set of transistors are coupled together.

Abstract: A system and method for processing an analog signal output by a sensor. The system and method converting, using at least one analog-to-digital converter (ADC), the analog output signal to a digital signal, the digital signal including a plurality of samples at a predetermined resolution, detecting whether a trigger condition is met by analyzing the digital signal, detecting an event based on trigger information from the detecting whether a trigger condition is met, generating event information having time information included therein when the event is detected, defining one or more time windows based on the time information included in the event information, performing decimation on the digital signal based on the defined one or more time windows to generate a decimated signal, and outputting the decimated signal.

Abstract: A voltage comparator, comprises: a first branch comprising a first transistor, a first resistor (R1), and a first current dependent voltage source (VA), wherein a first voltage (V1) is applied across the first branch to generate a first current and wherein the first transistor is a diode-connected transistor; a second branch comprising a second resistor (R2), a second current dependent voltage source (VB), and a second transistor having a control voltage (V3), wherein a second voltage (V2) is applied on an end of the second branch to generate a second current; and a third branch for generating a comparator output, wherein a trip point of the comparator output is set to when the first current and the second current are equal and wherein the trip point is a function of the transistors, the resistors, and the current dependent voltage sources of the first branch and the second branch.

Abstract: In an exemplary aspect of the invention, a clock signal amplifier circuit includes an amplifier circuit, a first switch part, and a second switch part. The amplifier circuit amplifies a clock signal. The first switch part controls ON/OFF of the amplifier circuit according to a select signal. The second switch part opens and closes complementarily to the first switch part according to the select signal. The amplifier circuit receives a test clock signal used in a test mode operation state through the second switch part. Further, the amplifier circuit outputs a signal generated by amplifying an input signal serving as the clock signal, or the test clock signal, according to the select signal.

Abstract: In some embodiments related to a smart edge detector, the smart edge detector uses a second clock in a receiver domain (e.g., clock CLK_D2) to trigger a first flip-flop having a first clock in a transmitter domain (e.g., clock CLK_D1) as input data for the first flip-flop. The clock CLK_D2 through a delay cell also triggers a second flip-flop having the same clock CLK_D1 as input data for the second flip-flop. Based on the output of the first flip-flop (e.g., output S1) and of the second flip-flop (e.g., output S2), the embodiments determine whether the rising and or falling edge of clock CLK_D2 should be used for triggering in a transmitting and receiving application. The embodiments are applicable in both situations where the rising edge or falling edge of clock CLK_D1 is used as a triggering edge. Other embodiments are also disclosed.

Abstract: New sensors and different embodiments of multi-channel integrated circuit are provided. The new high energy and spatial resolution sensors use both solid state and scintillator detectors. Each channel of the readout chip employs low noise charge sensitive preamplifier(s) at its input followed by other circuitry. The different embodiments of the sensors and the integrated circuit are designed to produce high energy and/or spatial resolution two-dimensional and three-dimensional imaging for widely different applications. Some of these applications may require fast data acquisition, some others may need ultra high energy resolution, and a separate portion may require very high contrast. The embodiments described herein addresses all these issues and also other issues that may be useful in two and three dimensional medical and industrial imaging.

Abstract: A conversion circuit for converting a differential signal into a single-phase signal 1 has a source-follower amplifier 10 and a source-grounded amplifier 20. The source-follower amplifier 10 outputs a non-inverted signal IN of the differential signal the phase of which is not inverted. The source-grounded amplifier 20 inverts an inverted signal INX of the differential signal and adjusts its phase to that of the non-inverted signal IN. At point A, differential signals IN, INX are added and output as a single-phase signal OUT.

Abstract: A switching matrix has a first number of inputs and a second number of outputs as well as a conductor arrangement and controllable switching elements by means of which the inputs can be connected with the outputs. The controllable switching elements are fashioned such that at least two independent control signals are required to trigger a switching event.

Abstract: Methods and apparatus for properly biasing differential comparators are provided. Using a feedback relationship, a bias for a main stage that receives a first differential input of the comparator is produced. Separately, a feedback relationship produces a bias for a main stage that receives a second differential input. These biases, produced as a result of the feedback relationship between bias stages and stages that replicate the main stages, are applied to the main stages. The outputs of the differential comparator are differential outputs with improved common-mode rejection as a result of the feedback and replica biasing.

Abstract: According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude compensation circuit also includes a feedback circuit coupled to respective outputs of the first and second composite programmable buffers. According to this embodiment, the feedback circuit compares a first output amplitude of the first composite programmable buffer with a reference voltage and a second output amplitude of the second composite programmable buffer with the reference voltage and provides first and second control signals for adjusting the respective gains of the first and second composite programmable buffers so as to reduce respective differences between the first and second output amplitudes and the reference voltage.

Abstract: A comparator, comprising at least one current stage for providing a first current proportional to a difference between first and second comparator inputs, the first current being provided to an amplifier input; an amplifier for amplifying a current provided to the amplifier input and providing a comparator output; apparatus for introducing hysteresis, comprising at least one of a current source and a current sink, the current source being arranged to selectively source a source current to the amplifier input such that the comparator output changes from a first state to a second state when a difference between the first and second inputs rises above a first value, and the current sink being arranged to selectively sink a sink current from the amplifier input such that the comparator output changes from the second state to the first state when the difference between the first and second inputs falls below a second value; and apparatus for controlling at least one of the source current and the sink current to be

Abstract: Methods and systems are provided for comparing currents. The method includes driving a first current through a first X leg of a first current conveyor circuit and a second current through a second X leg of a second current conveyor circuit. The method further includes draining a third current from a first X terminal of the first current conveyor circuit to produce a first positive transistor current and a first negative transistor current, and draining a fourth current from a second X terminal of the second current conveyor circuit to produce a second positive transistor current and a second negative transistor current. The method further includes summing the first positive transistor current and the second negative transistor current to produce a first current output, the first negative transistor current and the second positive transistor current to produce a second current output, and the first current output and the second current output to produce a summed current output.

Abstract: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: Methods and apparatus for properly biasing differential comparators are provided. Using a feedback relationship, a bias for a main stage that receives a first differential input of the comparator is produced. Separately, a feedback relationship produces a bias for a main stage that receives a second differential input. These biases, produced as a result of the feedback relationship between bias stages and stages that replicate the main stages, are applied to the main stages. The outputs of the differential comparator are differential outputs with improved common-mode rejection as a result of the feedback and replica biasing.

Abstract: According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude compensation circuit also includes a feedback circuit coupled to respective outputs of the first and second composite programmable buffers. According to this embodiment, the feedback circuit compares a first output amplitude of the first composite programmable buffer with a reference voltage and a second output amplitude of the second composite programmable buffer with the reference voltage and provides first and second control signals for adjusting the respective gains of the first and second composite programmable buffers so as to reduce respective differences between the first and second output amplitudes and the reference voltage.

Abstract: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: A signal compensation circuit compensates for direct-current offset of an input signal by amplifying the input signal with an amplifier having a variable direct-current offset. A low-speed negative feedback loop charges and discharges a capacitor in an integrating circuit according to the direct-current component of the amplified signal. A high-speed negative feedback loop charges and discharges the same capacitor at a faster rate when the amplified signal goes outside an allowable amplitude range. The capacitor potential is used to control the direct-current offset of the amplifier. The allowable amplitude range is adjusted according to the amplitude of the amplified signal. High-speed compensation can thus be combined with a tolerance for runs of identical code levels in the input signal.

Abstract: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: A voltage comparing circuit of the invention includes a first and a second capacitor terminals on one side of which are respectively connected to a positive side voltage of an analog input signal and a negative side voltage of a reference voltage via a first and a second switch and terminals on other side of which are commonly connected, a third and a fourth capacitor terminals on one side of which are respectively connected to a positive side voltage of the reference voltage and a negative side voltage of the analog input signal via a third and a fourth switch and terminals on other side of which are commonly connected, a first and a second inverter respectively connected to a common connection terminal of the first and the second capacitors and a common connection terminal of the third and the fourth capacitors and connected with a fifth and a sixth switch respectively between input and output terminals thereof, a seventh and an eighth switch respectively connected between the input terminal of the first in

Abstract: There is provided a signal transmission system, wherein when a control signal which puts an output terminal of an output circuit 12A into a high-impedance state is supplied to the output circuit 12A and an input circuit 14A, power is fed to the input circuit 12A to operate it and, at the same time, power-feeding to the output circuit 12A is stopped; and when the control signal is not supplied to the output circuit 12A nor the input circuit 14A, power is fed to the output circuit 12A to operate it and, at the same time, power-feeding to the input circuit 12A is stopped. Also, a signal of an expected value of the output circuit 12A based on the control signal is generated from an OR circuit 45.

Abstract: A Kerr-lens mode-locked Cr:fosterite laser 15 operated with negative nonlinear phase shift. The nonlinear phase shift is induced by the cascade x(2) x(2) process in a lithium triborate crystal. Employing the cascade process at large phase mismatch produces a nearly linear frequency chirp. Transform-limited pulses as short as 60 fs are generated with positive cavity dispersion.

Abstract: A multi-channel readout chip is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier inputs with self triggering output. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are readout. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: A test circuit operable to examine both differential outputs and single outputs of a device under test (DUT), the circuit comprises a first circuit having as inputs a first output of the DUT and a first set of independent reference voltages, and an output of the first circuit coupled to a plurality of comparators. The test circuit further comprises a second circuit having as inputs a second output of the DUT and a second set of independent reference voltages, and an output of the second circuit coupled to the plurality of comparators. The test circuit further comprises a select circuit coupled to outputs of the comparators, the output of the first circuit and the output of the second circuit. The select circuit outputting the outputs of the first circuit and the second circuit or outputting the outputs of the comparators.

Abstract: DC components are removed by a first and a second capacitor from a normal signal and its inverted signal from a first and a second input terminal, and the signals are input to a DC level generating circuit. The DC level generating circuit newly adds a DC component to the respective signals from which the DC components are removed by the first and the second capacitors, and extracts only a DC voltage from a feedback voltage with a low-pass filter using the fist and the second capacitors. The circuit of the DC level generating circuit which includes the low-pass filter using the first and the second capacitors is configured so that a high-frequency cut-off frequency other than that included into a loop gain by the low-pass filter is not included. Consequently, only one high-frequency cut-off frequency exists in the loop gain, thereby preventing a feedback circuit from oscillating.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first current in response to a first input signal. The second circuit may be configured to generate a second current in response to a second input signal. The third circuit may be configured to present a first pulse of current at a first output or a second pulse of current at a second output in response to the first and second currents.

Abstract: A semiconductor integrated circuit having a plurality of input first stage circuits, each performing a comparison of an individual input signal level to a reference voltage level, wherein a plurality of different reference voltage lines having different reference voltage levels are provided to allow selection of any one of the different reference voltage levels for each of the input first stage circuits.

Abstract: An analog circuit is provided to output the maximum voltage from among the set of analog voltages produced by a set of voltage sources connected to the input terminals of the circuit. The circuit has a number of output terminals equal to the number of input terminals. For each input terminal there is one corresponding output terminal. From among the set of analog voltages at the input terminals of the circuit, the analog circuit finds which voltage is the maximum voltage, and it produces this voltage at the output terminal corresponding to the input terminal having the maximum voltage, while setting the other output terminal voltages to zero volts. Through parallel processing of the input voltages, the analog circuit finds the largest input voltage. The analog circuit is made from inexpensive and readily available components suitable for large scale integration fabrication.

Abstract: A multi-channel readout chip is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier inputs with self triggering output. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are readout. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: A switched capacitor sorter based on magnitude includes a plurality of input units, a winner-take-all (WTA) circuit for finding a maximum voltage level, and an output unit. A plurality of input voltages are simultaneously input to the respective input units, and the sorted results are output in a time-shared manner.

Abstract: An improved circuit and method of making precise time of arrival measurements on optical pulse data of relatively varying widths. The invention provides an analog input pulse representing received optical pulse data, along with a delayed version of the analog input pulse. The time of delay is set such that the original analog pulse and the delayed analog pulse cross each other at a predetermined point. This cross-over consistently occurs at the same point on the signal independent of the size or shape of the analog pulse. Preferably, the cross-over occurs at approximately 70% of the analog pulse amplitude. The cross-over point between the original pulse and the delayed pulse triggers the generation of the leading edge of a time of arrival pulse.

Abstract: A winner-take-all circuit for judging a channel receiving an analog signal having the largest or smallest value among multiple channels upon input of analog signals. Each basic circuit includes a detecting unit for comparing an input voltage with a reference voltage, and a feedback current generating unit for outputting a feedback current that determines a judging range in response to an output voltage from the detecting unit. The winner-take-all circuit also includes a tenth transistor serving as a common transistor to all the basic circuits. The tenth transistor secures, even when an input voltage is small, a current that should flow through a sixth transistor serially connected to the seventh transistor that determines an amount of a feedback current from the feedback current generating circuit.

Abstract: A multi-channel readout chip is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge amplifiers with self trigger and calibration capabilities to provide timing information with better than 20 nanosecond precision. The trigger threshold can be adjusted to provide energy discrimination. The chip has a sparse readout function in which only the channels which have received signals greater than a preselected threshold value are readout, thus providing fast data acquisition capabilities.

Abstract: Switch circuits 21 and 22 are opened before switch circuits 31 and 32 are opened so that clock field through-noises inputted from the switch circuits 31 and 32 are not inputted to a differential amplifier circuit, and also switch circuits 11, 12, 51 and 52 are closed immediately before a comparison operation is started by the switch circuit 21 and 22 so that the differential amplifier circuit remains balanced, thereby to realize a high-speed comparator circuit.

Abstract: A power supply circuit selectively provides various voltage signals to memory devices, such as EPROM or EEPROM for example. The power supply circuit receives voltage signals at input terminals and selectively outputs a voltage signal, in accordance with the requirement for reading, writing and erasing operations, while preventing leakage current between voltage signals. Among other things, the power supply circuit provides a relatively low impedance and does not require high voltage levels for performing the above memory operations. The selection of voltage signals at an output terminal is effected by control means for controlling conductivity and non-conductivity of MOS transistors based on a control signal supplied from a control signal input terminal.

Abstract: A very dense polarity detection circuit which detects the polarity of a dc voltage on a transmission line. When incorporating such a very sense detection circuit, a semiconductor integrated circuit device is formed of a reduced number of parts. The polarity detection circuit for detecting the polarities of dc voltages on transmission lines (51) and (52) includes an input circuit (4), a clamp circuit (5), a comparison circuit (6) and a control circuit (7). The input circuit (4) has a high input impedance and receives a voltage-divide potential at a predetermined ratio. The clamp circuit (5) clamps outputs of the input circuit (4) at a predetermined voltage so that outputs from the clamp circuit (5) are not each smaller than a ground potential by a preselected voltage. The outputs of clamp circuit (5) are supplied to the comparison circuit (6) and the control circuit (7).

Abstract: An integrated high voltage differential sensor which uses the inverse gain of a pair of parasitic JFETs to provide a low power circuit for translating a differential high voltage signal down to a lower voltage level that can be easily sensed by the low voltage control circuitry in a power IC and without the use of a resistive voltage divider. The IC includes, between a first high voltage input and ground, a first series circuit of a first JFET, a first voltage level shifting resistor and a bias current source (I.sub.B). A second series circuit of a reference resistor (R.sub.L), a second JFET, a second voltage level shifting resistor and a bias current source (I.sub.B) is coupled between a second high voltage input and ground. A feedback circuit including an operational amplifier is coupled between a low voltage point of the first series circuit and the gates of both JFETs so as to adjust the bias voltages of the JFETs.