Abstract: A voltage comparator circuit for a power source having an energy harvester and an energy storage. The circuit comprises a first voltage input node and a second voltage input node arranged to respectively receive a first voltage level of a first output of the energy harvester and a voltage level of a second output of the energy storage; an output node arranged to switch in response to a comparison of the first and second first voltage levels; and a plurality of semiconductor junction devices arranged to provide a floating local ground arranged to vary in response to a change of the first and/or the second voltage level, wherein the floating local ground has a voltage level higher than an absolute ground connected to the voltage comparator circuit; wherein the floating local ground is arranged to prevent a breakdown of circuit components due to a voltage difference connected at terminals of each of the circuit component exceeding a breakdown voltage of the respective circuit component.

Abstract: A method and processing device for image demosaicing is provided. The processing device comprises memory and a processor. The processor is configured to, for a pixel of a Bayer image which filters an acquired image using three color components, determine directional color difference weightings in a horizontal direction and a vertical direction, determine a color difference between the first color component and the second color component and a color difference between the second color component and the third color component based on the directional color difference weightings, interpolate a color value of the pixel from the one color component and the color differences and provide a color image for display.

Abstract: A device includes a driver circuit and diagnostic circuitry coupled to the driver circuit. The diagnostic circuitry includes an on-state diagnostic circuit and an off-state diagnostic circuit. The diagnostic circuitry, in operation: generates a configuration signal associated with an operative condition of the driver circuit based on a comparator output of the off-state diagnostic circuit; diagnoses conditions associated with the driver circuit; and controls operation of the on-state diagnostic circuit based on the configuration signal.

Abstract: The present disclosure discloses a display driving device insensitive to external noise. The display driving device may include first and second data wires configured to connect a transmitter of a timing controller and a receiver of a source driver, first and second terminating resistors configured to connect the first and second data wires, and a noise reduction circuit configured to detect a lock fail, generate a common voltage when detecting the lock fail, and provide the common voltage to a node between the first and second terminating resistors. The display driving device can prevent an image failure by minimizing the influence of external noise.

Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

Abstract: The present invention discloses a comparator circuit having false-alarm preventing mechanism. An input pair circuit receives a first and a second input voltages from a first and a second input terminals in an the operation state. The input pair circuit and a latch circuit cooperate to perform comparison thereon in the operation state to generate a first and a second output voltages at a first and a second output terminals. A gate and a drain of a first latch transistor are electrically coupled to the first and the second output terminals respectively. A gate and a drain of a second latch transistor are electrically coupled to the second and the first output terminals respectively. A conduction adjusting circuit enhances the conduction of the latch circuit when being triggered. A voltage detection circuit triggers the conduction adjusting circuit when the first and the second output voltages are not within a predetermined range.

Abstract: In examples, an apparatus includes a FET, first and second voltage-to-current circuits, a current selection circuit, and a comparator. The FET has first and second segments. The first segment has a first gate coupled to the first voltage-to-current circuit, a first source, and a first drain. The second segment has a second gate coupled to the second voltage-to-current circuit, a second source coupled to the first source, and a second drain coupled to the first drain. The current selection circuit has a current selection circuit output and first and second current selection inputs. The first current selection circuit input is coupled to the first voltage-to-current circuit. The second current selection circuit input is coupled to the second voltage-to-current circuit. The comparator has a comparator output and first and second comparator inputs, the first comparator input is coupled to the current selection circuit output.

Abstract: A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

Abstract: A method and an integrated circuit for limiting a switchable load current. The integrated circuit includes a main transistor, through which in the conductive state a load current flows for supplying a load and a mirror transistor, a gate terminal of the mirror transistor being electrically connected to a gate terminal of the main transistor and a source terminal of the mirror transistor being electrically connected to a source terminal of the main transistor. The integrated circuit further includes a coupling circuit, which is configured to track a source drain voltage of the mirror transistor as a function of the source drain voltage of the main transistor. A gate control circuit is further provided, which limits the load current through the main transistor on the basis of a drain current through the mirror transistor.

Abstract: In various embodiments, a comparison circuit compares voltages within an integrated circuit. The comparison circuit includes a comparison capacitor, an inverter, and multiple switches. A first terminal of the comparison capacitor is coupled to both a first terminal of a first switch and a first terminal of a second switch. A second terminal of the comparison capacitor is coupled to both a first terminal of a third switch and an input of the inverter. An output of the inverter is coupled to both a second terminal of the third switch and a first terminal of a fourth switch. A second terminal of the fourth switch is coupled to a first terminal of a fifth switch and a first output of the comparison circuit. At least a portion of the switches are turned on during a comparison model and are turned off during a reset mode.

Abstract: An input/output circuit including: an input circuit configured to load differential input data to setup nodes based on a data strobe clock; an output circuit configured to compare and amplify the data loaded to the setup nodes, and output differential output data; and a voltage retention circuit configured to retain the setup nodes at voltage levels corresponding to the differential output data, based on the data strobe clock and the differential output data.

Abstract: A method of controlling first and second switches of a switching cell, including measuring a current flowing through the first switch when the first switch is controlled to the off state, and setting a switching dead time according to the measurement.

Abstract: A multi-level voltage generator includes P-type metal-oxide-semiconductor (PMOS) transistors that generate corresponding positive voltages and a common voltage respectively, each PMOS transistor having a source connected to corresponding generated voltage, and a drain connected to an output node to provide the corresponding generated voltage; N-type metal-oxide-semiconductor (NMOS) transistors that generate corresponding negative voltages and the common voltage respectively, each NMOS transistor having a source connected to corresponding generated voltage, and a drain connected to the output node to provide the corresponding generated voltage; and body-voltage selectors that adaptively select a body voltage for the plurality of PMOS transistors and NMOS transistors respectively, except PMOS transistor associated with a highest positive voltage and NMOS transistor associated with a lowest negative voltage with body and source connected together.

Abstract: Various embodiments relate to a mode detector configured to determine a mode of a circuit based upon an attached power source, including: a first latch configured to hold an first input value and output the first held value and an inverse of the first held value; a second latch configured to hold a second input value and output the second held value and an inverse of the second held value; a first output switch connected between a first power source line and a power source output of the mode detector, wherein the first output switch is configured to be controlled by the output of the first latch; a second output switch connected between a second power source line and the power source output of the mode detector, wherein the second output switch is configured to be controlled by the output of the second latch; a first AND gate with a first input and a second input connected to the inverse output of the second latch, wherein the first input is configured to receive a first power on reset signal based upon the f

Abstract: A device for hooking up a signal-outputting mechanism with two potential sensors each of which has allocated to it two evaluation terminals, wherein the potentials of the evaluation terminals depend inversely on the resistances between the respective evaluation terminals.

Abstract: A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

Abstract: A dynamic comparator includes a differential amplifier stage, a switching unit and a switching charge storage unit. The switching charge storage unit includes a plurality of switching transistors, and a charge storage capacitor electrically connected to the plurality of switching transistors. When an operational mode of the dynamic comparator is switched from a comparison state to a reset state, a voltage on one of a first terminal and a second terminal of the charge storage capacitor is increased from a half of the system voltage to a system voltage, so as to implement a charge recycle effect. The dynamic comparator of the present invention can have lower power consumption and lower charge-discharge current.

Abstract: Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Abstract: A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

Abstract: This application relates to sensing circuits for sensing a physical property or quantity of interest. The sensing circuit has an oscillator comprising a hysteretic comparator and a loop filter configured to output an oscillation signal. The loop filter comprises a first component with an electrical property that varies with the physical property or quantity of interest. A time constant of the loop filter depends on the electrical property of the first component. A decoder is configured to receive the oscillation signal and provide an indication of any change in frequency of the oscillation signal as an indication of a change in the physical property or quantity of interest. The electrical property may be an impedance, such as a resistance.

Abstract: Apparatus for managing high speed Universal Serial Bus 2.0 (USB2) communications is presented. The apparatus may include a combination differential difference detector to receive first and second input signals, the combination differential difference detector to, in a first mode: sense a first voltage difference between the first and second input signals and output a squelch signal when the first voltage difference is less than or equal to a pre-defined value. The combination differential difference detector is to, in a second mode, sense a second voltage difference between the first and second input signals and output a disconnect signal when the second voltage difference is greater than or equal to a pre-defined value. Related methods may also be disclosed.

Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

Abstract: An information handling system includes a PSU current level combiner, a current level indication splitter, and a load element. The PSU current level combiner receives a PSU current level indication from each of a plurality of PSUs, and provides a system current level indication that indicates a total amount of current supplied by the PSUs. Each PSU current level indication is a current signal and wherein a current level of each PSU current level indication is proportional to the amount of current supplied by the associated PSU. The system current level indication is a current signal. A current level of the system current level indication is proportional to the total amount of current. The system current level indication splitter receives the system current level indication, and provides copies of the system current level indication.

Abstract: A voltage clamping circuit includes a first detection circuit, a second detection circuit, and a discharge circuit. The first detection circuit detects a voltage level of a power voltage during a first operation period of a semiconductor apparatus. The second detection circuit detects the voltage level of the power voltage during a second operation period of the semiconductor apparatus. The discharge circuit changes the voltage level of the power voltage based on the detection results of the first and second detection circuits.

Abstract: A disconnecting device for interrupting a direct current between a direct current source and an electric apparatus, having a current-conducting mechanical switch, a power electronics unit connected thereto, and an energy store which is charged by an arcing voltage generated on the switch by an arc as the switch is being disconnected. A pulse generator that is connected to the energy store triggers at least one semiconductor switch of the power electronics unit in such a way that the power electronics unit short-circuits the switch and the arc is extinguished.

Abstract: The present application relates to a hysteresis comparator, which comprises a hysteresis comparator circuit and a hysteresis generating circuit. The hysteresis comparator circuit two comparator legs each with a differential transistor and a load transistor. The differential transistors receive a comparator biasing current, which is variably divided based on the relative levels of the voltage signals applied to control terminals of the differential transistors. An output stage is provided for developing an output voltage signal based on currents flowing through the load transistors. The hysteresis generating circuit is arranged for selectively injecting a hysteresis current in or selectively drawing a hysteresis current from either one of the two comparator legs depending on the level of the output voltage signal.

Abstract: Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.

Abstract: This application discusses techniques for reducing the energy of an output ripple in a voltage converter at a switching frequency of the voltage converter. In certain examples, an amplitude of a reference voltage can be modulated with a time-varying random value or pseudo-random value to provide a reduction in the energy of the output ripple at the switching frequency of the voltage converter.

Abstract: A method of gain calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*RES) and a calibration bit (B*LSB), analyzing a least significant bit of the digital signal (COUT) and the calibration bit (B*LSB), determining an indication of a presence of gain error in the gain module, and calibrating the gain error. As the determination of the calibration bit (B*LSB) requires only one additional comparison, as compared to normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Abstract: Apparatuses and methods for image sensors with increased analog to digital conversion range are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to a ramp voltage input of the comparator, increasing, by a ramp generator, an auto-zero voltage level of a ramp voltage provided to the ramp voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to a bitline input of the comparator.

Abstract: The invention provides a control circuit of a switch device. A single output pin of the control unit outputs an enable signal to control terminals of two switch units to control an on-state of the two switch units, and adjust a current size of a control current of the on-state of the switch device. One of the switch units after receiving the enable signal for a predetermined time is switched to an off-state, so as to reduce power consumption of the switch device.

Abstract: A receiver for an N-wire digital interface, where N is any integer exceeding two, has N input terminals, a common node and N detection stages. Each of the N detection stages has a resistive element coupled between the common node and a respective one of the N input terminals, and a comparator having a first input coupled to the respective one of the N input terminals and a second input coupled to the common node.

Abstract: A signal transmission system includes a transmitter configured to encode a transmission signal to generate 2N (N: integer larger than or equal to two) binary signals among which a number of 0s and a number of 1s are equal to each other, and to transmit the 2N binary signals, 2N signal lines configured to transmit the 2N binary signals, respectively, and a receiver configured to detect a bit pattern among a plurality of possible bit patterns of the 2N binary signals in response to a plurality of differential components between 2N received signals received through the 2N signal lines, and to decode the detected bit pattern.

Abstract: A signal transmission system includes a transmitter configured to encode a transmission signal to generate 2N (N: integer larger than or equal to two) binary signals among which a number of 0s and a number of 1s are equal to each other, and to transmit the 2N binary signals, 2N signal lines configured to transmit the 2N binary signals, respectively, and a receiver configured to detect a bit pattern among a plurality of possible bit patterns of the 2N binary signals in response to a plurality of differential components between 2N received signals received through the 2N signal lines, and to decode the detected bit pattern.

Abstract: In one embodiment, a method for increasing speed of a differential input pair. The method comprises applying a first boost current to a first input of the differential input pair during a transition of a first signal applied to the first input; storing the first boost current; ending the application of the first boost current in response to the stored first boost current exceeding a first threshold; applying a second boost current to a second input of the differential input pair during a transition of a second signal applied to the second input; storing the second boost current; and ending the application of the second boost current in response to the stored second boost current exceeding a second threshold.

Abstract: A level shift circuit includes a first resistor connected to a level shift power source, a first transistor having a drain connected to a second end of the first resistor and a source to the ground, a second resistor connected to the level shift power source, a second transistor having a drain connected to a second end of the second resistor and a source to the ground, a pulse generator controlling ON/OFF of the first and second transistors according to an input signal, a control part generating a set signal if the first transistor is ON, a reset signal if the second transistor is ON, and no signal if there is no voltage difference between a voltage at the drain of the first transistor and a voltage at the drain of the second transistor, and a flip-flop providing an output signal according to the set and reset signals.

Abstract: A device for comparing voltage levels of a pair of input signals is presented. The device may include a pre-amp circuit and a differential amplifier. The pre-amp circuit may be configured to receive a first input signal and a second input signal, adjust a voltage level of each of the pair of input signals, and assert a control signal after a pre-determined period of time from the assertion of an enable signal. The differential amplifier may be configured to amplify a voltage difference between the first input signal and the second input signal dependent upon the adjusted voltage level of the pair of input signals in response to the assertion of the control signal.

Abstract: A method of establishing a look-up table for an electrophoretic display is disclosed. The method is for establishing a plurality of driving waveforms of the electrophoretic display to the look-up table. The method includes dividing the plurality of driving waveforms to a plurality of time intervals according to a plurality of voltage values of the plurality of driving waveforms. The method also includes preparing a plurality of voltage waveform records according to the plurality of the voltage values and numbers of a unit times of the corresponding time intervals, and storing the plurality of voltage waveform records into the look-up table. Therefore, the storing capacity occupied by the look-up table of the electrophoretic display may be saved.

Abstract: Two semiconductor switches are arranged in parallel in a load circuit for connecting a power source with a load. Further, the semiconductor switches are controlled so as to be alternately tuned on and off. As a result, since a current flows through only either of the semiconductor switches, an offset error detected by current sensors includes only an offset error of either of the semiconductor switches, the detection of current with high accuracy can be accomplished. Therefore, when performing the control of shutting off the circuit to cope with the occurrence of an overcurrent flowing through the load, the shutoff control with high accuracy can be accomplished.

Abstract: A signal transmission device includes a differential driver, a first single-ended driver circuit block, a second single-ended driver circuit block, a control circuit, and a common-mode filter. In the case where two-channel single-ended transmission is performed by using the first and second single-ended driver circuit blocks, the control circuit controls a driving capability of the first single-ended driver circuit block and a driving capability of the second single-ended driver circuit block in accordance with a combination of a change in a logical value of an output signal of the first single-ended driver circuit block and a change in a logical value of an output signal of the second single-ended driver circuit block.

Abstract: The disclosure provides a clamp circuit and a method for clamping voltage. The clamp circuit includes: a first switch control unit, connected with the high-potential terminal of the first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to VGate1 when the voltage of the high-potential terminal is lower than a first pre-set value V1, and a second switch control unit, connected to the low-potential terminal of the first stage output of the comparator and configured to clamp the voltage of the low-potential terminal to VGate2 when the voltage of the low-potential terminal is higher than a second pre-set value V2, wherein the voltages of the first stage output of the comparator are between VGND and VCC. By the disclosure, the output voltage swings of the first stage of the comparator are limited, and thereby the processing speed of the comparator is improved.

Abstract: An electronic circuit includes: a weighting circuit configured to generate a first current by weighting and combining a first input signal and a second input signal in accordance with a modifiable coefficient and to generate a second current by weighting and combining a first inverted signal and a second inverted signal in accordance with the coefficient, the first inverted signal being an inverted signal of the first input signal, the second inverted signal being an inverted signal of the second input signal; and a decision circuit configured to decide on an output signal by comparing the first current with the second current.

Abstract: A comparator has a first terminal, a second terminal, and an output terminal. A selection circuit is coupled to the first terminal. A calibration circuit is coupled to the output terminal and the second terminal. The comparator is configured to operate in a first mode when the selection circuit provides a first input signal to the first terminal and the calibration circuit provides a second input signal to the second terminal. The comparator is configured to operate in a second mode when the selection circuit provides a first calibration signal to the first terminal and the calibration circuit provides a second calibration signal to the second terminal based on an output signal at the output terminal. The comparator generates the output signal based on the first calibration signal and the second calibration signal.

Abstract: A circuit comprises a first path, a second path, a current generating circuit, and a sense amplifier. The first path has a first current having a first current value. The second path has a second current having a second current value. The current generating circuit is configured to generate a reference current having a reference current value based on the first current value and the second current value. The sense amplifier is configured to receive a third current having a third current value and to generate a logical value based on the reference current value and the third current value.

Abstract: A comparator used in a clock signal generation circuit compares two input signals and generates an output signal. The comparator has first and second input transistors coupled to the input signals. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals. First and second hysteresis control transistors are coupled between the input transistors and the hysteresis transistors to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal. The comparator is operable in a first mode or a second mode based on a hysteresis enable signal. In the first mode the comparator applies hysteresis to the comparison of the input signals and in the second mode, compares the input signals without hysteresis.

Abstract: A comparator circuit comprising an operational amplifier configured to compare a difference between a switching voltage and a reference voltage, and a dynamically adjustable bias current generator coupled to the operational amplifier. A method of conserving power in a comparator circuit includes estimating a switching regulator load current value, communicating the value to a current bias generator, enabling the bias generator with a signal from a switching regulator PFM logic circuit, and establishing a bias current at an operational amplifier of the comparator circuit on the basis of the enabling.

Abstract: An electronic device comprising a first node to be coupled to a first antenna, a second node coupled to a second antenna, a third node to be coupled to a third antenna, a first comparator coupled with a first input to the first node and with a second input to a second node, a second comparator coupled with a first input to the first node and with a second input to the third node, a third comparator coupled with a first input to the second node and with a second input to the third node. Each of the first, the second and the third comparators are configured to compare a first current and a second current at the first input and the second input.

Abstract: Embodiments related to electrically characterizing a semiconductor device are provided. In one example, a method for characterizing a pin of a semiconductor device is provided, the method comprising providing a test pattern to the semiconductor device. Further, the method includes adjusting a selected electrical state of a pin of the semiconductor device and measuring a value for a dependent electrical state of the pin responsive to the selected electrical state. The example method also includes generating an electrical characterization for the pin by correlating the dependent electrical state with the selected electrical state and outputting the electrical characterization for display.

Abstract: A low-power method and apparatus is provided for adapting to time-varying limitations of a power source, such as a vehicle power source which is in a more-limited state when the engine is off. The supply voltage is monitored for changes using an unclocked, low-power first stage having an analog section, a voltage comparator. Upon detecting voltage changes reflective of a potential power source state change, the first stage generates an interrupt. In response, a second stage transitions from a low-power standby mode to a higher-power active mode. The second stage may include a microprocessor and is configured to confirm or disconfirm the state change. Upon confirmation, further operations are triggered. Upon disconfirmation, the second stage returns to standby mode. The first stage may include an operational amplifier whose two inputs are indicative of the supply voltage, one input having a different response rate to voltage variations than the other.