Comparison Between Plural Varying Inputs Patents (Class 327/63)
  • Patent number: 10333749
    Abstract: Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: June 25, 2019
    Assignee: KANDOU LABS, S.A.
    Inventor: Amin Shokrollahi
  • Patent number: 10305369
    Abstract: This application discusses techniques for reducing the energy of an output ripple in a voltage converter at a switching frequency of the voltage converter. In certain examples, an amplitude of a reference voltage can be modulated with a time-varying random value or pseudo-random value to provide a reduction in the energy of the output ripple at the switching frequency of the voltage converter.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: May 28, 2019
    Assignee: Analog Devices Global
    Inventors: Bin Shao, Sean Kowalik, Alan S. Walsh, Danzhu Lu
  • Patent number: 10050638
    Abstract: A method of gain calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*RES) and a calibration bit (B*LSB), analyzing a least significant bit of the digital signal (COUT) and the calibration bit (B*LSB), determining an indication of a presence of gain error in the gain module, and calibrating the gain error. As the determination of the calibration bit (B*LSB) requires only one additional comparison, as compared to normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: August 14, 2018
    Assignee: Stichting IMEC Nederland
    Inventors: Ming Ding, Pieter Harpe, Hanyue Li
  • Patent number: 9774811
    Abstract: Apparatuses and methods for image sensors with increased analog to digital conversion range are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to a ramp voltage input of the comparator, increasing, by a ramp generator, an auto-zero voltage level of a ramp voltage provided to the ramp voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to a bitline input of the comparator.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: September 26, 2017
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hiroaki Ebihara, Zheng Yang
  • Patent number: 9741503
    Abstract: The invention provides a control circuit of a switch device. A single output pin of the control unit outputs an enable signal to control terminals of two switch units to control an on-state of the two switch units, and adjust a current size of a control current of the on-state of the switch device. One of the switch units after receiving the enable signal for a predetermined time is switched to an off-state, so as to reduce power consumption of the switch device.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: August 22, 2017
    Assignee: FSP TECHNOLOGY INC.
    Inventors: Han-Wei Chen, Chun-Hao Yu, Chia-Hua Liu
  • Patent number: 9641362
    Abstract: A receiver for an N-wire digital interface, where N is any integer exceeding two, has N input terminals, a common node and N detection stages. Each of the N detection stages has a resistive element coupled between the common node and a respective one of the N input terminals, and a comparator having a first input coupled to the respective one of the N input terminals and a second input coupled to the common node.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: May 2, 2017
    Assignee: OPTIS CIRCUIT TECHNOLOGY, LLC
    Inventor: Kimmo Koli
  • Patent number: 9559872
    Abstract: A signal transmission system includes a transmitter configured to encode a transmission signal to generate 2N (N: integer larger than or equal to two) binary signals among which a number of 0s and a number of 1s are equal to each other, and to transmit the 2N binary signals, 2N signal lines configured to transmit the 2N binary signals, respectively, and a receiver configured to detect a bit pattern among a plurality of possible bit patterns of the 2N binary signals in response to a plurality of differential components between 2N received signals received through the 2N signal lines, and to decode the detected bit pattern.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 31, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Win Chaivipas
  • Patent number: 9531568
    Abstract: A signal transmission system includes a transmitter configured to encode a transmission signal to generate 2N (N: integer larger than or equal to two) binary signals among which a number of 0s and a number of 1s are equal to each other, and to transmit the 2N binary signals, 2N signal lines configured to transmit the 2N binary signals, respectively, and a receiver configured to detect a bit pattern among a plurality of possible bit patterns of the 2N binary signals in response to a plurality of differential components between 2N received signals received through the 2N signal lines, and to decode the detected bit pattern.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: December 27, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Win Chaivipas
  • Patent number: 9496873
    Abstract: In one embodiment, a method for increasing speed of a differential input pair. The method comprises applying a first boost current to a first input of the differential input pair during a transition of a first signal applied to the first input; storing the first boost current; ending the application of the first boost current in response to the stored first boost current exceeding a first threshold; applying a second boost current to a second input of the differential input pair during a transition of a second signal applied to the second input; storing the second boost current; and ending the application of the second boost current in response to the stored second boost current exceeding a second threshold.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: November 15, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Shengyuan Li, Iulian Mirea
  • Patent number: 9350352
    Abstract: A level shift circuit includes a first resistor connected to a level shift power source, a first transistor having a drain connected to a second end of the first resistor and a source to the ground, a second resistor connected to the level shift power source, a second transistor having a drain connected to a second end of the second resistor and a source to the ground, a pulse generator controlling ON/OFF of the first and second transistors according to an input signal, a control part generating a set signal if the first transistor is ON, a reset signal if the second transistor is ON, and no signal if there is no voltage difference between a voltage at the drain of the first transistor and a voltage at the drain of the second transistor, and a flip-flop providing an output signal according to the set and reset signals.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: May 24, 2016
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Kengo Koike
  • Patent number: 9324386
    Abstract: A device for comparing voltage levels of a pair of input signals is presented. The device may include a pre-amp circuit and a differential amplifier. The pre-amp circuit may be configured to receive a first input signal and a second input signal, adjust a voltage level of each of the pair of input signals, and assert a control signal after a pre-determined period of time from the assertion of an enable signal. The differential amplifier may be configured to amplify a voltage difference between the first input signal and the second input signal dependent upon the adjusted voltage level of the pair of input signals in response to the assertion of the control signal.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: April 26, 2016
    Assignee: Apple Inc.
    Inventors: Ajay Kumar Bhatia, Amrinder S Barn
  • Patent number: 9196200
    Abstract: A method of establishing a look-up table for an electrophoretic display is disclosed. The method is for establishing a plurality of driving waveforms of the electrophoretic display to the look-up table. The method includes dividing the plurality of driving waveforms to a plurality of time intervals according to a plurality of voltage values of the plurality of driving waveforms. The method also includes preparing a plurality of voltage waveform records according to the plurality of the voltage values and numbers of a unit times of the corresponding time intervals, and storing the plurality of voltage waveform records into the look-up table. Therefore, the storing capacity occupied by the look-up table of the electrophoretic display may be saved.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 24, 2015
    Assignee: E Ink Holdings Inc.
    Inventor: Chun Ta Chien
  • Patent number: 9130569
    Abstract: Two semiconductor switches are arranged in parallel in a load circuit for connecting a power source with a load. Further, the semiconductor switches are controlled so as to be alternately tuned on and off. As a result, since a current flows through only either of the semiconductor switches, an offset error detected by current sensors includes only an offset error of either of the semiconductor switches, the detection of current with high accuracy can be accomplished. Therefore, when performing the control of shutting off the circuit to cope with the occurrence of an overcurrent flowing through the load, the shutoff control with high accuracy can be accomplished.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: September 8, 2015
    Assignee: YAZAKI CORPORATION
    Inventors: Akinori Maruyama, Keisuke Ueta, Yoshihide Nakamura, Yoshinori Ikuta
  • Patent number: 9093733
    Abstract: A signal transmission device includes a differential driver, a first single-ended driver circuit block, a second single-ended driver circuit block, a control circuit, and a common-mode filter. In the case where two-channel single-ended transmission is performed by using the first and second single-ended driver circuit blocks, the control circuit controls a driving capability of the first single-ended driver circuit block and a driving capability of the second single-ended driver circuit block in accordance with a combination of a change in a logical value of an output signal of the first single-ended driver circuit block and a change in a logical value of an output signal of the second single-ended driver circuit block.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: July 28, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroshi Suenaga, Yutaka Taguchi, Atsushi Shinkai, Takaharu Yoshida, Osamu Shibata, Chie Sasaki
  • Patent number: 9077324
    Abstract: The disclosure provides a clamp circuit and a method for clamping voltage. The clamp circuit includes: a first switch control unit, connected with the high-potential terminal of the first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to VGate1 when the voltage of the high-potential terminal is lower than a first pre-set value V1, and a second switch control unit, connected to the low-potential terminal of the first stage output of the comparator and configured to clamp the voltage of the low-potential terminal to VGate2 when the voltage of the low-potential terminal is higher than a second pre-set value V2, wherein the voltages of the first stage output of the comparator are between VGND and VCC. By the disclosure, the output voltage swings of the first stage of the comparator are limited, and thereby the processing speed of the comparator is improved.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 7, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Lei Huang, Eric Li
  • Patent number: 8994408
    Abstract: An electronic circuit includes: a weighting circuit configured to generate a first current by weighting and combining a first input signal and a second input signal in accordance with a modifiable coefficient and to generate a second current by weighting and combining a first inverted signal and a second inverted signal in accordance with the coefficient, the first inverted signal being an inverted signal of the first input signal, the second inverted signal being an inverted signal of the second input signal; and a decision circuit configured to decide on an output signal by comparing the first current with the second current.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 31, 2015
    Assignee: Fujitsu Limited
    Inventors: Takayuki Hamada, Sanroku Tsukamoto
  • Patent number: 8988113
    Abstract: A comparator has a first terminal, a second terminal, and an output terminal. A selection circuit is coupled to the first terminal. A calibration circuit is coupled to the output terminal and the second terminal. The comparator is configured to operate in a first mode when the selection circuit provides a first input signal to the first terminal and the calibration circuit provides a second input signal to the second terminal. The comparator is configured to operate in a second mode when the selection circuit provides a first calibration signal to the first terminal and the calibration circuit provides a second calibration signal to the second terminal based on an output signal at the output terminal. The comparator generates the output signal based on the first calibration signal and the second calibration signal.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Soenen, Alan Roth, Justin Shi
  • Publication number: 20150071002
    Abstract: A circuit comprises a first path, a second path, a current generating circuit, and a sense amplifier. The first path has a first current having a first current value. The second path has a second current having a second current value. The current generating circuit is configured to generate a reference current having a reference current value based on the first current value and the second current value. The sense amplifier is configured to receive a third current having a third current value and to generate a logical value based on the reference current value and the third current value.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Tien-Chun YANG
  • Patent number: 8975926
    Abstract: A comparator used in a clock signal generation circuit compares two input signals and generates an output signal. The comparator has first and second input transistors coupled to the input signals. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals. First and second hysteresis control transistors are coupled between the input transistors and the hysteresis transistors to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal. The comparator is operable in a first mode or a second mode based on a hysteresis enable signal. In the first mode the comparator applies hysteresis to the comparison of the input signals and in the second mode, compares the input signals without hysteresis.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Wenzhong Zhang, Chris C. Dao, Jehoda Refaeli, Yi Zhao
  • Patent number: 8947125
    Abstract: A comparator circuit comprising an operational amplifier configured to compare a difference between a switching voltage and a reference voltage, and a dynamically adjustable bias current generator coupled to the operational amplifier. A method of conserving power in a comparator circuit includes estimating a switching regulator load current value, communicating the value to a current bias generator, enabling the bias generator with a signal from a switching regulator PFM logic circuit, and establishing a bias current at an operational amplifier of the comparator circuit on the basis of the enabling.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: February 3, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Vijayakumar Dhanasekaran
  • Patent number: 8941473
    Abstract: An electronic device comprising a first node to be coupled to a first antenna, a second node coupled to a second antenna, a third node to be coupled to a third antenna, a first comparator coupled with a first input to the first node and with a second input to a second node, a second comparator coupled with a first input to the first node and with a second input to the third node, a third comparator coupled with a first input to the second node and with a second input to the third node. Each of the first, the second and the third comparators are configured to compare a first current and a second current at the first input and the second input.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Oliver Nehrig, Dirk Preikszat
  • Patent number: 8907697
    Abstract: Embodiments related to electrically characterizing a semiconductor device are provided. In one example, a method for characterizing a pin of a semiconductor device is provided, the method comprising providing a test pattern to the semiconductor device. Further, the method includes adjusting a selected electrical state of a pin of the semiconductor device and measuring a value for a dependent electrical state of the pin responsive to the selected electrical state. The example method also includes generating an electrical characterization for the pin by correlating the dependent electrical state with the selected electrical state and outputting the electrical characterization for display.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: December 9, 2014
    Assignee: Teseda Corporation
    Inventors: Jack Frost, Joseph M. Salazar
  • Publication number: 20140347100
    Abstract: A low-power method and apparatus is provided for adapting to time-varying limitations of a power source, such as a vehicle power source which is in a more-limited state when the engine is off. The supply voltage is monitored for changes using an unclocked, low-power first stage having an analog section, a voltage comparator. Upon detecting voltage changes reflective of a potential power source state change, the first stage generates an interrupt. In response, a second stage transitions from a low-power standby mode to a higher-power active mode. The second stage may include a microprocessor and is configured to confirm or disconfirm the state change. Upon confirmation, further operations are triggered. Upon disconfirmation, the second stage returns to standby mode. The first stage may include an operational amplifier whose two inputs are indicative of the supply voltage, one input having a different response rate to voltage variations than the other.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Applicant: Sierra Wireless, Inc.
    Inventors: Christophe SEVEAU, Lik King AU-YEUNG
  • Patent number: 8884656
    Abstract: A zero-crossing detection circuit includes a comparator and circuitry. The comparator produces an output signal that is indicative of zero-crossing events in an input Alternating Current (AC) waveform. The circuitry may be configured to feed the comparator with first and second rails voltages, and to progressively increase the rails voltages during time intervals derived from the input AC waveform, so as to feed the comparator with target values of the rails voltages in time-proximity to the zero-crossing events. The circuitry may be configured to compensate for an error in detecting the zero crossing events caused by differences in amplitude of the input AC waveform, by correcting the input AC waveform provided to the comparator. The circuitry may be configured to activate the comparator during time intervals preceding respective anticipated times of the zero-crossing events, and to deactivate the comparator at least once during time periods other than the time intervals.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: November 11, 2014
    Assignee: Sigma Designs Israel S.D.I. Ltd.
    Inventor: Danny Braunshtein
  • Patent number: 8878570
    Abstract: An integrated circuit includes a configurable interface. The configurable interface includes an operational amplifier, a programmable gain amplifier, an analog-to-digital converter and a first select circuit. The first select circuit is configured to selectively couple the operational amplifier to the analog-to-digital converter in response to a first control signal. The first select circuit is further configured to selectively couple the programmable gain amplifier to the analog-to-digital converter in response to the first control signal.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 4, 2014
    Assignee: Silicon Laboratories Inc.
    Inventor: Axel Thomsen
  • Publication number: 20140285239
    Abstract: Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.
    Type: Application
    Filed: March 21, 2013
    Publication date: September 25, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Pedro Barbosa Zanetta, Ivan Carlos Ribeiro Nascimento
  • Publication number: 20140266309
    Abstract: A correlated double sampling circuit includes a first input terminal receiving a ramp signal having first and second ramp sections, a second input terminal receiving a pixel signal, and a comparing circuit comparing the ramp signal with the pixel signal to generate an output signal, wherein the comparing circuit changes a point in time at which the output signal logically transitions during the first ramp section and the second ramp section in response to an applied dithering enable signal.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: CLAUDIO JAKOBSON
  • Patent number: 8831752
    Abstract: The disclosed exemplary embodiments relates to a control system and a control method for identifying corresponding position. The control system includes a plurality of electronic control modules, each electronic control module having a microcontroller electrically coupled to at least one joint, and the joint is configured for connecting to a joint of neighboring electronic control module. The electronic control modules include a main-control-terminal electronic control module, an assembling electronic control module and at least one detecting electronic control module. The main-control-terminal electronic control module is configured for assigning one of the electronic control modules to be the assembling electronic control module, and assigning the rest of the electronic control modules to be the detecting electronic control module.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 9, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Ching Huang, Yu-Wei Hung
  • Patent number: 8803619
    Abstract: A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: August 12, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anand Kumar Sinha, Sanjay K. Wadhwa
  • Patent number: 8803556
    Abstract: Some of the embodiments of the present disclosure provide a method comprising receiving a first signal and a second signal; generating a first digital count corresponding to a characteristic of the first signal; subsequent to generating the first digital count, generating a second digital count corresponding to a characteristic of the second signal; and comparing the first digital count with the second digital count. Other embodiments are also described and claimed.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: August 12, 2014
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Shimon Avitan
  • Patent number: 8791691
    Abstract: A signal detector includes a summation unit connected to offset first and second input signals representing a differential input signal into two offset pairs of first and second signals. The signal detector also includes a detection unit connected to select the first signal from one of the offset pairs of first and second signals and the second signal from the other of the offset pairs in an overlap portion of the first and second signals to form a complementary pair of overlap signals and provide a differentially peak-detected output signal from the complementary pair of overlap signals. Additionally, the signal detector includes a comparator connected to provide a detection output signal corresponding to the differentially peak-detected output signal and a reference signal. A method of operating a signal detector is also included.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: July 29, 2014
    Assignee: LSI Corporation
    Inventor: Zichuan Cheng
  • Patent number: 8761300
    Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 24, 2014
    Assignee: Broadcom Corporation
    Inventors: Ahmad Mirzaei, Hooman Darabi
  • Patent number: 8736310
    Abstract: A comparator having first and second stages can provide component offset compensation and improved dynamic range. The first stage can receive first and second input signals and produce first and second output signals. The second stage can be coupled to the first stage to receive the first and second output signals at first and second input terminals of the second stage. The second stage can provide a voltage to the first and second terminals that differs from the supply voltage by less than a voltage of a diode drop. The comparator is operable to receive input voltages that reach the supply voltage.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: May 27, 2014
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Chee Weng Cheong, Dianbo Guo, Kien Beng Tan
  • Publication number: 20140132240
    Abstract: A timer to provide pulses at a comparator output wherein a frequency of the pulses is dependent on temperature, wherein providing each pulse includes biasing a first input of the comparator at a voltage and operating a transistor in a subthreshold region of operation to change the voltage of the first input of a comparator at a rate dependent upon temperature. The output of the comparator changes state when the voltage of the first input crosses a voltage of a second input of the comparator.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 15, 2014
    Inventors: DALE J. MCQUIRK, MICHAEL T. BERENS, MITEN H. NAGDA
  • Publication number: 20140118028
    Abstract: A zero-crossing detection circuit includes a comparator and circuitry. The comparator produces an output signal that is indicative of zero-crossing events in an input Alternating Current (AC) waveform. The circuitry may be configured to feed the comparator with first and second rails voltages, and to progressively increase the rails voltages during time intervals derived from the input AC waveform, so as to feed the comparator with target values of the rails voltages in time-proximity to the zero-crossing events. The circuitry may be configured to compensate for an error in detecting the zero crossing events caused by differences in amplitude of the input AC waveform, by correcting the input AC waveform provided to the comparator. The circuitry may be configured to activate the comparator during time intervals preceding respective anticipated times of the zero-crossing events, and to deactivate the comparator at least once during time periods other than the time intervals.
    Type: Application
    Filed: October 24, 2013
    Publication date: May 1, 2014
    Applicant: Sigma Designs Israel S.D.I Ltd.
    Inventor: Danny Braunshtein
  • Patent number: 8704552
    Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 22, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James B. Boomer, Oscar W. Freitas
  • Patent number: 8686757
    Abstract: An apparatus and a method are provided for selectively enabling and disabling a squelch circuit in a Serial Advanced Technology Attachment (SATA) host or SATA device while maintaining proper operation of the host and device. An apparatus and method are provided which allow the squelch circuit to be selectively enabled and disabled across SATA power states (PHY Ready, Partial, and Slumber) and in Advanced Host Controller Interface (AHCI) Listen mode.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: April 1, 2014
    Assignee: Intel Corporation
    Inventors: Jien-Hau Ng, Tea M. Lee
  • Patent number: 8680891
    Abstract: A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: March 25, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Ankit Srivastava, Xuhao Huang, Xiaohong Quan
  • Publication number: 20140055167
    Abstract: An earphone connection interface is provided.
    Type: Application
    Filed: August 1, 2013
    Publication date: February 27, 2014
    Applicant: Samsung Electronics Co. Ltd.
    Inventors: Minwoo OH, Jungmin YANG, Byounghee LEE, Jaekyu LEE, Hwanho LEE, Suho JO
  • Patent number: 8648623
    Abstract: A single stage current sense amplifier is described that generates a differential output that is proportional to a current through a sense resistor. The voltage across the sense resistor is Vsense. The current sense amplifier includes a differential transconductance amplifier having high impedance input terminals. An on-chip RC filter filters transients in the Vsense signal. A feedback circuit for each leg of the amplifier causes a pair of input transistors to conduct a fixed constant current irrespective of Vsense, which stabilizes the transconductance. A gain control resistor (Re) is coupled across terminals of the pair of input transistors and has Vsense across it. The current through the gain control resistor is therefore Vsensex1/Re. A level shifting circuit coupled to each of the input transistors lowers a common mode voltage at an output of the amplifier. Chopper circuits at the input and output cancel any offset voltages.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: February 11, 2014
    Inventors: Hengsheng Liu, Edson Wayne Porter, Gregory Jon Manlove
  • Publication number: 20140028408
    Abstract: A relaxation oscillator has a comparator that includes first through third bias current transistors coupled to a first supply rail. First and second input transistors form a pair of parallel coupled transistors connected to the first bias current transistor. A first current mirror control transistor connects the first input transistor to a second supply rail. A first current mirror output transistor is coupled to the first current mirror control transistor, and connects the second bias current transistor to the second supply rail. A second current mirror control transistor connects the second input transistor to the second supply rail. A second current mirror output transistor is coupled to the second current mirror control transistor, and connects the third bias current transistor to the second supply rail. A transition time reduction transistor, coupled across the third bias current transistor, is coupled to the second bias current transistor, and provides a comparator output.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 30, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventor: Zhengxiang WANG
  • Patent number: 8633734
    Abstract: A bi-directional comparator compares two input signals and applies a hysteresis level to the smaller input signal only after the output signal switches logical states and when the two input signals are within a predetermined range of each other. In one embodiment, the hysteresis applied to the smaller input signal is removed when the two input signals are no longer within the predetermined range of each other.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: January 21, 2014
    Assignee: Micrel, Inc.
    Inventors: Charles A. Casey, Richard Zhu, Cameron Jackson
  • Publication number: 20130335119
    Abstract: A bi-directional comparator compares two input signals and applies a hysteresis level to the smaller input signal only after the output signal switches logical states and when the two input signals are within a predetermined range of each other. In one embodiment, the hysteresis applied to the smaller input signal is removed when the two input signals are no longer within the predetermined range of each other.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Applicant: MICREL, INC.
    Inventors: Charles Casey, Richard Zhu, Cameron Jackson
  • Patent number: 8610465
    Abstract: A comparator circuit (5) comprising a fully differential main amplifier unit (10, 10b). The main amplifier unit (10, 10b) comprises a control port and is adapted to control a bias current of a first branch of the main amplifier unit (10, 10b) and/or a bias current of a second branch of the main amplifier unit (10, 10b) in response to one or more control voltages supplied to the control port of the main amplifier unit (10, 10b). The comparator circuit (5) comprises circuitry (60) for balancing the voltages at the positive and negative input terminals (12a, 12b) of the main amplifier unit (10, 10b) during a first clock phase of the comparator circuit (5). Furthermore, the comparator circuit (10, 10a) comprises a switched-capacitor accumulator unit with a differential input.
    Type: Grant
    Filed: May 25, 2009
    Date of Patent: December 17, 2013
    Assignee: CSR Technology Inc.
    Inventor: Christer Jansson
  • Patent number: 8604838
    Abstract: An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Robert F. Payne
  • Patent number: 8575968
    Abstract: A circuit method includes periodically increasing a tail current of a differential stage of a comparator to periodically power on the differential stage to a power-on state, and periodically decreasing the tail current of the differential stage to periodically power down the differential stage to a low-power state. The periodically increasing of the tail current and the periodically decreasing of the tail current are asynchronous operations for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state. Periodically increasing the tail current and the periodically decreasing the tail current asynchronously for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state provide for low noise and high speed during signal comparison.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: November 5, 2013
    Assignee: Marvell World Trade Ltd.
    Inventor: Sasan Cyrusian
  • Patent number: 8570072
    Abstract: A comparator circuit for providing hysteresis comprises first and second differentially coupled transistors. The first of the differentially coupled transistors provides drain current to first and second load transistors. The second of the differentially coupled transistors provides drain current to third and fourth load transistors. In one example embodiment, the drain of the first of the differentially coupled transistors also drives the gate of the first and third load transistors, while the drain of the second of the differentially coupled transistors drives the gate of the second and fourth transistors.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: October 29, 2013
    Assignee: Marvell International Ltd.
    Inventors: David Gozali, Hong Liang Zhang
  • Publication number: 20130258722
    Abstract: A power supply includes a phase-cut pre-regulator. The phase-cut pre-regulator comprises a switching device connected between a line voltage and an input voltage of a bulk capacitor and a comparator receiving the line voltage and a reference voltage, comparing the line voltage with hysteresis reference voltages based on the reference voltage, and switching the switching device according to the compared result.
    Type: Application
    Filed: May 21, 2013
    Publication date: October 3, 2013
    Inventors: Charlie WANG, Sang Cheol MOON, Young-Bae PARK
  • Publication number: 20130249600
    Abstract: An interpolation circuit includes: a generation circuit that generates interpolation data from a plurality of pieces of input data, using an interpolation coefficient, among input data inputted in time series including a data point and a transition point; a detection circuit that detects that the input data lacks at the data point; and a coefficient circuit that changes the interpolation coefficient for each given data interval, and skips a position for changing the interpolation coefficient to the transition point when the detection circuit detects the lack of the input data.
    Type: Application
    Filed: December 10, 2012
    Publication date: September 26, 2013
    Inventors: Takushi Hashida, Yoshiyasu Doi
  • Patent number: 8497709
    Abstract: An input/output circuit has a first load having one end coupled to a first standard voltage line, a first MOS transistor having a drain electrode coupled to another end of the first load, a second load having one end coupled to the first standard voltage line, a second MOS transistor having a drain electrode coupled to another end of the second load, a third MOS transistor having a source electrode each of which is coupled to source electrodes of the first and second MOS transistors, a first constant-current source coupled between the source electrode of the first MOS transistor and a second standard voltage line, and a second constant-current source coupled between the source electrode of the second MOS transistor and the second standard voltage line. The circuit size is reduced by transmitting a differential signal or a single-ended signal using a single input/output circuit.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Norihiko Fukuzumi, Toshie Kato