Abstract: Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.

Abstract: A radio-frequency peak amplitude detection circuit includes a load capacitor, a current source that charges the load capacitor and set the bias current for the field effect transistors, and a pair of field effect transistors. The gates of the field effect transistors are biased at a level below the threshold voltage of the transistors. The transistors are arranged in parallel with the capacitor and are operable to drain the capacitor at a rate determined by a differential input at the gates of the transistors. The voltage across the load capacitor is low-pass filtered and has a voltage level representative of the amplitude of the differential input signal.

Abstract: A level conversion circuit including a first level shifter and a second level shifter is provided. The first level shifter converts a first control voltage into a second control voltage during a voltage conversion period. The second level shifter is coupled to the first level shifter. The second level shifter converts the second control voltage into a third control voltage during the voltage conversion period to control a next stage circuit. The first level shifter is configured to detect a voltage level of a power domain where the third control voltage operates and generate a plurality of middle voltages based on the detection result. The second level shifter is configured to generate the third control voltage based on the middle voltages. Furthermore, a voltage level conversion method is also provided.

Abstract: Integrated circuits having analog-to-digital converters are provided. Analog-to-digital converters may contain latched comparators. A latched comparator may include inputs configured to receive a differential input voltage signal, a differential reference voltage signal, and a clock signal. The comparator may include a preamplifier, a latching circuit, a level shifter, and a flip-flop coupled in series. The preamplifier may include large input transistors for minimizing offset, stacked tail transistors, and diode-connected load transistors for minimizing kickback noise. The preamplifier may be used to generate amplified voltage signals. The latching circuit may include a first pair of cross-coupled pull-down transistors, a second pair of cross-coupled pull-up transistors, and precharge transistors.

Abstract: A voltage comparator, comprises: a first branch comprising a first transistor, a first resistor (R1), and a first current dependent voltage source (VA), wherein a first voltage (V1) is applied across the first branch to generate a first current and wherein the first transistor is a diode-connected transistor; a second branch comprising a second resistor (R2), a second current dependent voltage source (VB), and a second transistor having a control voltage (V3), wherein a second voltage (V2) is applied on an end of the second branch to generate a second current; and a third branch for generating a comparator output, wherein a trip point of the comparator output is set to when the first current and the second current are equal and wherein the trip point is a function of the transistors, the resistors, and the current dependent voltage sources of the first branch and the second branch.

Abstract: A voltage sensing device with which high-precision voltage sensing is possible without the need to obtain a unique correction constant for each device. A pair of voltage input nodes NCk and NCk-1 is selected from voltage input nodes NC0-NCn in switch part 10, and they are connected to sensing input nodes NA and NB in two types of patterns with different polarity (forward connection, reverse connection). Sensing input nodes NA and NB are held at reference potential Vm by voltage sensing part 20, and current Ina and Inb corresponding to the voltage at voltage input nodes NCk and NCk-1 flows to input resistors RIk and RIk-1. Currents Ina and Inb are synthesized at different ratios in voltage sensing part 20, and sensed voltage signal S20 is generated according to the synthesized current Ic. Sensed voltage data S40 with low error is generated according to the difference between the two sensed voltage signals S20 generated in the two connection patterns.

Abstract: A comparator circuit. A comparator circuit may include a differential amplifying unit to amplify a difference between a voltage at a first node and a voltage at a second node and/or output a resultant voltage, and/or a current source to supply a first bias current to a first node and/or supply a second bias current to a second node. A comparator may include a first bias switch to bias a current flowing from a first node to a ground voltage source, a second bias switch to bias a part of a current flowing from a second node to a ground voltage source, a third bias switch to bias a remaining part of a current flowing from a second node to a ground voltage source, and/or a bias converting unit to supply a third bias current to a second node.

Abstract: A method of detecting signal faults comprises sampling at least three redundant signals; calculating a difference signal for each unique pair-wise comparison of the at least three sampled redundant signals; comparing each difference signal to an expected distribution for the difference signals; and determining if one of the at least three redundant signals is faulty based on the comparison of each difference signal to the expected distribution.

Abstract: An integrated circuit comparator includes a pair of differential input transistors having gate terminals configured to receive a pair of differential input signals and a comparator output circuit electrically coupled to the pair of differential input transistors. A pair of differential offset compensation transistors are also provided. This pair of differential offset compensation transistors, which is electrically coupled to the pair of differential input transistors, has gate terminals that are configured to receive a pair of unequal dc offset voltages.

Abstract: An amplitude detection circuit using a sinusoidal input signal inputs to produce a digital output (a one or zero) is described. The circuit uses an input field effect transistor (FET) with a gate load coupled to a gate of the input FET. A drain load may be coupled to a drain of the input FET. A source load may be coupled to a source of the input FET. A controllable variable current generator provides a current to the source of the input FET, biasing the source of the input FET to a reference voltage. An input signal conductor may be coupled to the gate of the input FET. Other embodiments are described.

Abstract: In a signaling system, a first signal and a plurality of second signals are received via a signaling channel. A first received data value is generated in one of at least two states according to whether the first signal exceeds an average of the second signals.

Abstract: A method of detecting signal faults comprises sampling at least three redundant signals; calculating a difference signal for each unique pair-wise comparison of the at least three sampled redundant signals; comparing each difference signal to an expected distribution for the difference signals; and determining if one of the at least three redundant signals is faulty based on the comparison of each difference signal to the expected distribution.

Abstract: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with programmable hysteresis. Such circuits include a comparator input circuit that receives two inputs to be compared. The comparator input circuit provides a first differential current output based at least in part on a difference between the first voltage input and the second voltage input. The aforementioned circuits further include a hysteresis control circuit that is operable to receive a single programmable voltage input, and to provide a second differential current output based at least in part on the comparator output and the single programmable voltage input. An output circuit is also included that sums the first differential current and the second differential current, and provides a comparator output based at least in part on the sum of the first differential current and the second differential current.

Abstract: A differential signal transmission system includes m different voltage/current supplies, n transmission end, and a controller. The controller includes m×n switches. Each of the switches is coupled between a voltage/current supply and a transmission end. The controller controls the switches to turn on or off for coupling each transmission end to one of the different voltage/current supplies so as to carry the voltage of the coupled voltage supply onto the transmission end according to the transmitting data. The sum of the voltage differences among the transmission ends is 0.

Abstract: An integrated differential receiver includes a single gate oxide differential receiver and an associated switchable voltage supply circuit. The integrated differential receiver determines the desired receiver supply voltage and selects a supply voltage for the single gate oxide differential receiver. When a lower supply voltage is determined as the desired supply voltage, the integrated differential receiver automatically provides a supply voltage to the single gate oxide differential receiver with a voltage higher than the I/O pad supply voltage and higher than the maximum input signal voltage to increase the speed of operation for the differential receiver. The switchable voltage supply circuit is operatively responsive to a control signal which indicates the desired supply voltage for the I/O pad. In one embodiment, both the single gate oxide differential receiver and the switchable voltage supply circuit are single gate oxide circuits.

Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.

Abstract: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: A method and apparatus for interface signaling using single-ended and differential data signals improves performance of an interface. A differential pair of data signals and at least one single-ended data signal are transmitted over the interface. The differential pair of data signals is received by a differential receiver and the single-ended data signals are received by a receiver that uses the differential pair of data signals to improve the detection of the single-ended data signal. A novel receiver having a differential input and a single-ended input combines the differential pair of data signals with a single-ended data signal to detect the single-ended data signal providing improved common-mode rejection and reducing the error rate of the single-ended signal. Multiple single-ended signals may be associated with one differential signal, providing a scalable architecture grouping a number of single-ended signals with each differential pair of signals.

Abstract: Described is a differential clock receiver comprising a converter, a differential input stage, and a differential output stage. The converter converts a control signal indicative of a timing relationship into a DC offset signal. The differential input stage receives a differential clock signal and the DC offset signal. The differential input stage generates an intermediary differential signal from the differential clock. The intermediary differential signal has a DC offset resulting from the DC offset signal. The differential output stage receives the intermediary differential signal and generates at least two output signals from the intermediary differential signal. The output signals have a timing relationship determined by the DC offset of the intermediary differential signal.

Abstract: A data comparator using a dynamic reference voltage and an input buffer using the same. The data comparator comprises a comparator circuit for receiving a data signal and a pair of non-inverting/inverting signals, which are periodic and complementary. The output signal is generated by comparing twice the data signal with the sum of the non-inverting signal and the inverting signal. The non-inverting/inverting signals are used as a dynamic reference voltage in the data comparator.

Abstract: Circuitry is disclosed for detection of open inputs on an enhanced differential receiver. A pulldown terminator is coupled to the inputs of the enhanced differential receiver. If the differential inputs are not actively driven, the voltage on both differential inputs will be pulled to a predetermined voltage. When the voltage on the differential inputs reach a reference voltage, an active device detects that the reference voltage has been reached, and produces a predetermined logic value on an output of the enhanced differential receiver. The enhanced differential receiver is not subject to oscillation when not actively driven. Delay through the enhanced differential receiver is not substantially greater than delay through a conventional differential receiver consisting of only a differential amplifier.

Abstract: Frequency multiplying circuitry includes a couple of integrator circuits. The one integrator circuit charges a capacitor with a larger time constant via a resistor when an input clock signal is in its high level and then discharges it with a smaller time constant when the clock signal is in its low level. The other integrator circuit charges and discharges its capacitor in the opposite manner to the one integrator circuit as to the level of the clock signal. An output circuit compares the output voltages of both integrator circuits with a reference voltage and raises the level of its output signal when either one of the output voltages drops below the reference voltage. The duty ratio of the circuitry is therefore little susceptible to the frequency of the input signal and power supply voltage.

Abstract: The invention provides a NANO-ampere operable differential circuit by means of a few additional components. The multi-input differential circuit consists of more than three input elements that are connected to the same tail node, and an adaptive bias current control circuit. Applications of this multi-input differential circuit, which are, for instance comparators and voltage followers, do have a very low operation current at a normal operation mode. The proposed differential circuit is applicable for all kinds of analog complex circuits to attain nano-power operation.

Abstract: A differential voltage magnitude comparator to receive a differential input signal and a differential reference signal, in which a magnitude difference of the differential input signal is compared to the magnitude reference of the differential reference signal. An output state depends on the magnitude difference of the differential input signal to the magnitude difference of the differential reference signal. If the magnitude difference of the differential input signal is below the magnitude difference of the differential reference signal, the output is in one state, but if the magnitude difference of the differential input signal is above the magnitude difference of the differential reference signal, the output is in the other state. The comparison and logical operation to provide the output states are generated in single stage.

Abstract: A differential comparison circuit capable of easily obtaining desired circuit accuracy and comparing differential signals with reduced influences of fluctuation of a power source voltage. Input/output terminals I/O1 and I/O2 of a latch circuit 1 are connected to the drain terminals of MOS transistors M1 and M2 having the same characteristics. Input terminals IN1 and IN2 are provided to the gate and source terminals of the MOS transistor M2, and input terminals IN3 and IN4 are provided to the gate and source terminals of the MOS transistor M2. A bias circuit 2 brings the MOS transistors M1 and M2 into the same bias state. The difference of the input signals supplied to the input terminals IN1 and IN2 is compared with the difference of the input signals supplied to the input terminals IN3 and IN4. Since the comparison result is outputted from the first and second input/output terminals I/O1 and I/O2, the input offset voltage does not affect the differential comparison circuit.

Abstract: In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

Abstract: A multi-channel readout chip is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier inputs with self triggering output. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are readout. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: A complementary waveform driver is disclosed that generates output signals SOUT with arbitrary high and low drive states with respect to an independently controlled baseline signal SBL. Accordingly, the driver can generate very fast and flexible waveforms with multiple levels and baseline components. The driver implements complementary differential pairs of transistors that alternately source and sink programmable currents to an output port, creating an output waveform with excellent rising and falling edge symmetry, and greatly improved fidelity, especially at low level voltage swings. A complementary amplifier stage defines the baseline voltage level. When combined with a programmable active load and window comparator, the driver is particularly suited for pin electronics in automatic test equipment (ATE) applications.

Abstract: A current sorter for sorting a plurality of currents is disclosed. The current sorter comprises an input circuit unit for receiving a plurality of input currents to be sorted, a winner-take-all (WTA) circuit unit for finding the maximum current, a feedback control and voltage output circuit unit for generating feedback control signals and output voltages indicating the maximum current, and an output circuit unit for outputting sorted currents. A plurality of input currents are simultaneously input to the input circuit unit and the sorted results are output in a time-shared manner on the output circuit unit.

Abstract: A multi-input comparator determines a minimum or maximum signal value in a given set of signal values. In an illustrative embodiment, a multi-input comparator includes a number of interconnected inversion circuits, with each of the inversion circuits having an input node associated therewith. The input node of each of the inversion circuits is coupled to an output of at least one of the other inversion circuits. As a result, after activation of the inversion circuits, the voltages at the input nodes are indicative of the relative magnitude of the signal values previously applied thereto. The inversion circuits may be constructed using, for example, single-inverter or multiple-inverter building blocks. Additional inputs can be provided by replicating the corresponding single-inverter or multiple-inverter blocks.

Abstract: An analog circuit is provided to output the maximum voltage from among the set of analog voltages produced by a set of voltage sources connected to the input terminals of the circuit. The circuit has a number of output terminals equal to the number of input terminals. For each input terminal there is one corresponding output terminal. From among the set of analog voltages at the input terminals of the circuit, the analog circuit finds which voltage is the maximum voltage, and it produces this voltage at the output terminal corresponding to the input terminal having the maximum voltage, while setting the other output terminal voltages to zero volts. Through parallel processing of the input voltages, the analog circuit finds the largest input voltage. The analog circuit is made from inexpensive and readily available components suitable for large scale integration fabrication.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A three input comparator facilitates the comparison of a signal to the greater of two different reference voltages in a manner which mitigates propagation delay. A first differential pair of transistors facilitates comparison of the two reference voltages to one another, while second and third differential pairs of transistors facilitate comparison of the signal to the higher of the two reference voltages.

Abstract: A multi-channel readout chip is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier inputs with self triggering output. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are readout. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: A switched capacitor sorter based on magnitude includes a plurality of input units, a winner-take-all (WTA) circuit for finding a maximum voltage level, and an output unit. A plurality of input voltages are simultaneously input to the respective input units, and the sorted results are output in a time-shared manner.

Abstract: A comparator circuit performs at least three compare operations, wherein in each compare operation the comparator compares two of at least three reference voltages to one another and provides a signal to indicate which of the two reference voltages is greater. A decode logic circuit in response to the signals provided by the comparator circuit in the at least three compare operations selects the median reference voltage from among the at least three reference voltages, and causes a multiplexer to transfer the median reference voltage to an output terminal of the mux.

Abstract: To solve a problem that, as the number of signal sources for outputting peak values decreases, a peak output voltage decreases, and to improve detecting precision, there are provided a plurality of first buffer units ?Q.sub.11 .multidot.Q.sub.21 .multidot.M.sub.31 to Q.sub.13 .multidot.Q.sub.23 .multidot.M.sub.33 !, which are emitter-follower circuits, to each of which a signal is input, a plurality of second buffer units ?Q.sub.31 to Q.sub.33 ! which are respectively connected to the first buffer units and an output unit for outputting the detected peak signal.

Abstract: Control circuit for producing output voltages from a plurality of sensor signals, wherein each of the sensor signals are identical and mutually phase shifted. The control circuit comprises a plurality of comparators for producing the output voltages, wherein each comparator is respectively supplied with one of the sensor signals and with an amount of hysteresis which depends on the amplitude of one or more of the respective other sensor signals. The control circuit further comprises electronic circuitry for deriving the respective amount of comparator hysteresis for each of the comparators from the amplitude of one or more of the respective other sensor signals.

Abstract: The present invention provides a method and apparatus for detecting voltage drops on an IC chip. The device operates by using a reference voltage to detect the voltage range of a local voltage. A multiple number of reference voltages are used (or predetermined) between the reference voltage and the ground voltage. The voltage drop detecting device includes a multiple number of inverters having to the local voltage as its input. The inverters each have a trigger voltage corresponding to one of the reference positions. When the local voltage is smaller than the trigger voltage of the inverter, a low to high voltage switching is present at the output. A multiple number of positive-edge triggering devices, coupled to the reference voltage as one of its inputs, are each coupled to one of the inverters. A corresponding inverter presents a low to high switching to make the reference voltage present at the corresponding output terminal. The voltage range of the local voltage is detected at the output terminals.

Abstract: A winner-take-all circuit for judging a channel receiving an analog signal having the largest or smallest value among multiple channels upon input of analog signals. Each basic circuit includes a detecting unit for comparing an input voltage with a reference voltage, and a feedback current generating unit for outputting a feedback current that determines a judging range in response to an output voltage from the detecting unit. The winner-take-all circuit also includes a tenth transistor serving as a common transistor to all the basic circuits. The tenth transistor secures, even when an input voltage is small, a current that should flow through a sixth transistor serially connected to the seventh transistor that determines an amount of a feedback current from the feedback current generating circuit.

Abstract: A multi-channel readout chip is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge amplifiers with self trigger and calibration capabilities to provide timing information with better than 20 nanosecond precision. The trigger threshold can be adjusted to provide energy discrimination. The chip has a sparse readout function in which only the channels which have received signals greater than a preselected threshold value are readout, thus providing fast data acquisition capabilities.

Abstract: An inverter control circuit includes means for continuously computing and subtracting an average voltage from each of three modulating input waveforms. The average voltage is computed by determining the instantaneous maximum and minimum voltages of the three waveforms, summing these voltages, and then dividing them by an averaging factor. The shifted modulating waveforms are then compared with a high-frequency carrier wave to modulate the duty cycles of the inverter outputs to approximate desired output waveform characteristics.

Abstract: A comparator (10) provides a high speed comparison between at least two input signals and includes at least two stages (12) and (14). Each stage (12 and 14) includes a pair of transistors (24), a complementary pair of transistors (28) and an enabling transistor (26). The stages are coupled to provide positive feedback back to the first stage (12). A controller (15) operably couples to the enabling transistors. When the first input signal (16) is at a higher voltage level than the second input signal (18), the first comparison output (20) goes low. Conversely, when the second input signal (18) is at a higher voltage level than the first input signal (16), the second comparison output (22) goes low. When the first comparison output (20) goes low, the second enabling transistor (34) is disabled by the controller (15). When the second comparison output goes low, the first enabling transistor (26) is disabled by the controller (15).

Abstract: Comparator circuit (72) samples a differential input signal at switched capacitor circuit (100). The input signal is stored across capacitors (128, 130, 132, 134). Reference voltages are subtracted from the input signal to produce a difference signal. The difference is compared to a mid-supply reference VMID, and an amplified representation of the signal is produced at the output of differential gain stage (136). Latching output stage (138) uses feedback circuits (204, 211 and 202, 208) to process the amplified signal and to produce a rail to rail representation of the amplified signal at the inputs (146, 148) of SR latch (140). The feedback circuit also powers-down the output stage after processing the amplified signal. Buffer circuits (205, 213 and 214, 212) allow a new signal to be processed by capacitor circuit (100) while the previous signal is being stored in the SR latch.

Abstract: Voltage minimizer and maximizer circuits are provided for both single-ended and fully-differential analog input voltages. A single-ended analog voltage maximizer circuit includes a plurality of operational amplifiers (OP.sub.1, OP.sub.2 . . . OP.sub.N) wherein the number of operational amplifiers corresponds to the number of separate voltages (V.sub.1, V.sub.2 . . . V.sub.N) from which a maximum voltage is to be determined, each of the operational amplifiers receives a single-ended analog voltage at its non-inverting input, each output of the plurality of operational amplifiers is connected to a common output line where the maximum analog voltage output (V.sub.0) will be received, the common output line is also connected to the inverting input of each of the operational amplifiers. Each operational amplifier also has an operational amplifier circuit (FIGS.

Abstract: The median value of a set of voltage values is found by a technique that minimizes the circuitry while maximizing the speed, and also provides for dropouts. The voltage values, illustratively five in number, are applied in pairs to the inputs of ten comparators. The outputs of the comparators, and their complements, are formed into five "status words" of four bits each, such that each bit of a given status word represents the comparison of a given value with another of the values. The status word that contains two 1's and two 0's represents the median value. In a preferred circuit embodiment, this status word is rapidly determined in a series of three logic stages, wherein the highest and lowest values are eliminated in the first stage, the next highest and lowest are eliminated in the second stage, and the last stage determines the remaining status word that is associated with the median value. This technique also readily provides for dropouts by initializing the logic circuitry.

Abstract: A comparator for comparing the voltages of an address pair signals in complement with the voltages of bit pair signals in complement includes a pair of transistors for receiving the bit pair signals and a pair of MOSFETs for receiving the address pair signals. One transistor and one MOSFET are connected in series to define a first current path and other transistor and other MOSFET are connected in series to define a second current path. When the address signal and the bit signal are the same, both the first and second current paths close, but when they are different, either the first or the second current path opens to permit a current to pass therethrough. By detecting the current in the path, the coincidence and non-coincidence between the address pair signals and bit pair signals are detected.