Abstract: An integrated circuit (IC) includes a signal detection circuit having a signal detection circuit input and a signal detection circuit output. The IC further includes a reference voltage circuit having a reference voltage circuit input and a reference voltage circuit output. The IC also includes a comparator having a first comparator input and a second comparator input. The first comparator input is coupled to the reference voltage circuit output, and the second comparator input is coupled to the signal detection circuit output. The IC includes a clamp circuit having a clamp circuit input and a clamp circuit output. The clamp circuit input is coupled to the signal detection circuit, and the clamp circuit output is coupled to the reference voltage circuit output.

Abstract: An organic electroluminescent display panel includes: a first electrode, a pixel defining layer, an organic light emitting functional layer and a second electrode provided on a substrate; a conductive layer and a protection layer provided at a side of the second electrode away from the substrate, the conductive layer and the protection layer being provided in a single layer, a surface of the protection layer away from the substrate being parallel to that of the second electrode away from the substrate, the conductive layer being provided between the protection layer and the second electrode and in contact with the second electrode, the protection layer including a first portion provided in the pixel regions and a second portion provided on the conductive layer, and a sum of a thickness of the second portion and a thickness of the conductive layer being approximately equal to a thickness of the first portion.

Abstract: An organic light-emitting device including an anode electrode, a hole injection layer on the anode electrode, a hole transport layer on the hole injection layer, an emissive layer on the hole transport layer, and a cathode electrode on the emissive layer. A material of the hole injection layer includes a nitrogen-containing compound having a quinoid structure and a nitrogen-containing compound having a benzenoid structure. A ratio of a peak intensity IB to a peak intensity IA (IB/IA) in a Fourier transform infrared spectroscopy (FTIR) spectrum of the material of the hole injection layer ranges from 1.5 to 2.5, the peak intensity IA and the peak intensity IB being further defined.

Abstract: The present disclosure provides a display substrate, a manufacturing method thereof and a display device, belonging to the technical field of displaying. The display substrate includes a display area and a wiring area. The manufacturing method includes: forming a barrier structure at least between the wiring area and the display area; and forming a rheological organic material in the wiring area, so that the rheological organic material levels in the wiring area to form a protective film covering the wiring area.

Abstract: The object is providing an organic light emitting display device achieving a narrow bezel. A display device 10 has a first substrate 11, a second substrate 12, a sealant 25 sealing between the substrates, a display unit 15 including pixel circuits, a driving circuit 20 including a transistor for driving the pixel circuits, a first wiring unit for supplying voltage to the transistor, and a second wiring unit connecting between the transistor and the first wiring unit. The driving circuit 20 is disposed outside the display unit 15, the first wiring unit is disposed between the display unit 15 and the driving circuit 20, the display unit 15 and the first wiring unit are disposed between the first substrate 12 and the second substrate 12, the melting point of a second metal constituting the second wiring unit is higher than that of a first metal constituting the first wiring unit.

Abstract: Disclosed is a display device possessing: a plurality of pixels arranged in a matrix form over a substrate and each having a pixel electrode; a first wiring and a second wiring over the substrate and sandwiching the pixels; a first contact electrode and a second contact electrode respectively covering at least a part of the first wiring and at least a part of the second wiring; and an opposing electrode over and overlapping with the pixel electrodes, the first contact electrode, and the second contact electrode, the opposing electrode being shared by the plurality of pixels. The first wiring and the second wiring are spaced from each other and electrically connected to the opposing electrode through the first contact electrode and the second contact electrode, respectively.

Abstract: Aspects of the present disclosure are directed to apparatuses, systems and methods involving imaging providing pixel intensity ratios using circuitry. According to an example embodiment, an apparatus includes a photosensor array having an array of sensors and a circuitry. Each sensor of the photosensor array provides a signal value for a pixel that is indicative of an intensity of light detected. Further, the circuitry responds to the signal values from a plurality of sensors of the photosensor array, by converting signals indicative of a ratio of pixel intensity values to a digital signal that characterize at least an edge of an object corresponding to or associated with the intensity of the detected light. The circuitry provides digital signals, each indicative of a ratio of pixel intensity values, for respective sensors of the photosensor array.

Abstract: A transparent organic light-emitting display device may include a lower transparent substrate having a pixel region and a boundary region disposed between adjacent pixel regions, a solar cell disposed on the lower transparent substrate, a display structure disposed on the solar cell, and an overcoat layer disposed between the solar cell and the display structure, in which the overcoat layer electrically insulates the display structure from the solar cell.

Abstract: Disclosed is an organic light emitting display apparatus in which an anode electrode, an organic emission layer, a cathode electrode, and an auxiliary electrode connected to the cathode electrode and disposed on the same layer as that of the anode electrode are disposed in an active area of the substrate, a signal pad and a pad electrode connected to the signal pad and covering a top of the signal pad are disposed in a pad area of the substrate, and a top of the pad electrode has lower oxidation rate than the top of the signal pad.

Abstract: One embodiment of an analog-to-digital converter includes at least one comparator and a restriction circuit. The comparator has first and second input nodes and a connection node. The connection node is one of an internal node and an output node of the comparator. The restriction circuit is electrically connected to the connection node, and the restriction circuit is configured to restrict a voltage of the connection node.

Abstract: A EL display device has EL display panel including the a display area where a pixel is arranged in matrix, and a wiring pattern formed in a circumferential portion of the display area and supplying voltage to a pixel. The EL display panel includes a flexible substrate having an electrode connected to a source signal line or a gate signal line arranged thereon. The flexible substrate includes an anode reinforcement wiring and a cathode reinforcement wiring which are electrically parallel to the wiring pattern.

Abstract: An electric charge flow element including, on an insulating support, a stack of a first electrode, of a dielectric layer having at least one portion capable of letting charges flow by tunnel effect, and of a second electrode, wherein at least one of the electrodes is made of undoped polysilicon.

Abstract: USB apparatus suitable for interconnection with a USB host having a D? bus coupled to ground via a pull-down resistance, the USB apparatus including a microcontroller having a first port and a second port, the first port being coupled via a resistance to a voltage source and a switch, operated by the microcontroller via the second port, selectably interconnecting the first port and the bus of the USB host.

Abstract: A semiconductor device including a first function block operating at a first operation voltage having a first range and for generating a data signal, a second function block operating at a second operation voltage having a second range, and a voltage level control unit for performing or not performing a level shifting operation on a voltage level of the data signal depending on the existence or non-existence of a difference between the first operation voltage and the second operation voltage, and for transmitting a level-shifted data signal or the data signal to the second function block.

Abstract: A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.

Abstract: A power-up signal generation circuit of a semiconductor apparatus includes a driver configured to generate a power-up signal in response to a first voltage. The power-up signal generation circuit may also comprise a power control unit configured to provide the first voltage or a second voltage as a power supply voltage to the driver in response to the power-up signal.

Abstract: A voltage amplitude limiting circuit of a full differential circuit is provided for limiting voltage levels of a differential signal. The voltage amplitude limiting circuit includes a reference voltage generating unit and a replacing circuit. The reference voltage generating unit generates a high reference voltage and a low reference voltage. The replacing circuit is coupled to the reference voltage generating unit, a first input terminal and a second input terminal. When voltage at the first input terminal is greater than the high reference voltage, the replacing circuit uses the high reference voltage to replace the voltage at the first input terminal to serve as an output. When voltage at the first input terminal is less than the low reference voltage, the replacing circuit uses the low reference voltage to replace the voltage at the first input terminal to serve as an output.

Abstract: A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.

Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.

Abstract: Apparatus, systems and methods are provided for protecting a processing system from electromagnetic interference. An integrated circuit comprises a sensing arrangement configured to sense an interference signal and an interference detection module coupled to the sensing arrangement. The interference detection module is configured to detect when a power level associated with the interference signal is greater than a threshold value. In one embodiment, the interference detection module generates an interrupt for a processing system when the power level associated with the interference signal is greater than the threshold value.

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected between the first transistor and the fourth terminal, and a fourth transistor of the second conductivity type connected between the second transistor and the third terminal, the fourth transistor flowing a mirror current depending on a current passing through the third transistor.

Abstract: A resume and reset (RSMRST) signal output circuit, for outputting a low level voltage RSMRST signal, includes a first switch circuit, a delay circuit, and a second switch circuit. The first switch circuit receives a first voltage signal and converts the first voltage signal to a second voltage signal. The delay circuit is charged by the second voltage signal and outputs the second voltage signal it is when fully charged. The second switch circuit receives the second voltage signal and outputs the low level voltage RSMRST signal. The delay circuit is charged during a first state and discharged during a second state.

Abstract: A detection circuit is coupled to an output terminal of a driver circuit. The detection circuit includes a comparator to compare a signal at the output terminal to a reference signal corresponding to a signal that would be generated if a capacitive load having a relatively high capacitance value were connected to the output terminal. Output of the comparator is sampled at a predetermined time after the driver circuit provides the drive signal. An error signal is generated when the sampled output indicates that the capacitive load having the relatively high capacitance value is actually connected to the output terminal.

Abstract: In an embodiment, set forth by way of example and not limitation, a data slicer includes a signal input node, a comparator having a first input of a first polarity, a second input of a second polarity which is the opposite of the first polarity, and an output coupled to a data out node, the first input of the comparator being coupled to the signal input node, and a multi-mode threshold generator including a first threshold generator and second threshold generator, whereby the first threshold generator is selected firstly and the second threshold generator is selected secondly.

Abstract: The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register.

Abstract: An electronic device is provided that includes a power-on-reset (POR) circuit. The POR circuit includes a trigger stage configured to change an output if a first power supply voltage level exceeds a threshold voltage level and a first inverter and a second inverter being cross-coupled. An output of the second inverter is the POR output of the power-up reset circuit. The output is coupled to the trigger stage for switching the trigger stage off in response to a change of a signal at the output of the second inverter. The first inverter is dimensioned to follow with a voltage level at an output an initially rising slope of the first power supply voltage level and the second inverter is dimensioned to keep a voltage level at an output at a second power supply voltage level during the initially rising slope of the first power supply voltage level.

Abstract: A corner detector comprises a PMOS threshold voltage detector and an NMOS threshold voltage detector, the PMOS threshold voltage detector is composed of a first clock terminal, a first CMOS inverter, a first capacitor, a PMOS threshold voltage function generator and a first voltage output terminal, wherein the PMOS threshold voltage function generator is electrically connected to the first capacitor and applied to generate a first formula of voltage signal as a function of threshold voltage, the NMOS threshold voltage detector is composed of a second clock terminal, a second CMOS inverter, a second capacitor, an NMOS threshold voltage function generator and a second voltage output terminal, wherein the NMOS threshold voltage function generator is electrically connected to the second capacitor and applied to generate a second formula of voltage signal as a function of threshold voltage.

Abstract: A circuit arrangement for operating voltage detection has a detection block (1) and a control block (2). Detection block (1) has a first transistor (P1) that is connected between a first supply voltage terminal (VDD) and a first node (K1) and has a first control terminal (S1), a first resistor element (R1) that is connected between first node (K1) and second supply voltage terminal (VSS), a second transistor (P2) that is connected between first supply voltage terminal (VDD) and a second node (K2) and has a second control terminal (S2), a second resistor element (R2) that is connected between second node (K2) and second supply voltage terminal (VSS), a first switch (N1) that connects first node (K1) to second control terminal (S2), and a third resistor element (R3) that is connected between second control terminal (S2) and first supply voltage terminal (VDD).

Abstract: A host computer includes an enclosure, a motherboard mounted in the enclosure. The motherboard includes a battery, a reference voltage generating circuit, an electronic switch, an alarm unit mounted on the enclosure, and a comparator. The reference voltage generating circuit generates a reference voltage. The comparator is connected to the battery and the reference voltage generating circuit to receive the reference voltage and detect a voltage of the battery. The comparator compares the detected voltage of the battery with the reference voltage, and outputs a control signal to turn on the electronic switch to start the alarm unit when the voltage of the battery is less than the reference voltage.

Abstract: A power-on reset circuit includes a first circuit and a second circuit. The first circuit include a first NMOS transistor having a gate controlled by a low voltage supply VDD_L, a resistor connected between the source of the first NMOS transistor and a voltage supply VSS that is lower than VDD_L, and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor. The second circuit includes a first PMOS transistor having a source connected to VDD_L, a second PMOS transistor having a source connected to the drain of first PMOS transistor, a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, and an inverter configured to output a signal in response to the power on of the high voltage supply VDD_H and the low voltage supply VDD_L.

Abstract: Electronic equipment includes a battery, an interface portion to which a recording medium can be attached, a kind detection portion for detecting the kind of a recording medium, an access processing portion for executing a predetermined access process to a recording medium, a current consumption detection portion for detecting a value of current consumed by execution of the predetermined access process to the recording medium, an additional storage portion for storing a current consumption value corresponding to the detected kind into a storage portion, a power supply circuit for taking out and outputting electric power from the battery, and a power supply control portion for controlling the power supply circuit. The power supply control portion varies control on the power supply circuit in accordance with the current consumption value stored corresponding to the detected kind.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: According to one general aspect, an output driver configured to drive output signals from a core device may include a voltage convertor, an output stage, and a biasing unit. In various embodiments, the output driver is configured to operate in either a core device voltage mode or a high voltage mode. In some embodiments, the voltage convertor may be configured to receive a pair of differential input signals from a core device, wherein a maximum voltage of the input signals is equivalent to a core device voltage, and convert the input signals to a pair of intermediate input signals. In one embodiment, when in high voltage mode, the maximum voltage of the intermediate input signals may be equivalent to a high voltage that is higher than the core device voltage.

Abstract: An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level.

Abstract: A comparator circuit (300) has a first field effect transistor (FET) (307) with a supply voltage (301) connection and a diode connected FET (303) connected in series to form the first circuit leg of the comparator (300). A second diode connected FET (309) and a second FET (305) in series form the second circuit leg. The first FET (307) and said second FET (305) are approximately equal sized FETs. Another embodiment is an integrated circuit (401) with two n-channel FETs. A first diode connected FET (303) is connected to the first n-channel FET (307) in series to form the first circuit leg of a comparator (300) and a second diode connected FET (309) is connected to a second n-channel FET (305) in series to form the second circuit leg of the comparator. The two n-channel FETs that form the differential pair are approximately equal in size. The trip point is high with respect to the supply voltage.

Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.

Abstract: An object is to provide a semiconductor device within which a signal which can be used as a reset signal or a mode signal is produced at an arbitrary timing to reduce the number of pads of the semiconductor device. To achieve the object, in a semiconductor device (10), first and second pads (101, 102) are respectively supplied with an external supply voltage and a ground potential. A signal generating circuit (12) outputs a signal at a predetermined logic level when the voltage supplied to the first pad (101) reaches a predetermined voltage higher than a voltage supplied to the first pad (101) during a normal operation of the semiconductor device (10).

Abstract: A circuit for detecting noise peaks on the power supply of an electronic circuit, including at least a first transistor having its control terminal connected to a terminal of application of a first potential of a supply voltage of the circuit and having a first conduction terminal connected to a terminal of application of a second potential via at least one first resistive element, the second conduction terminal of the first transistor providing the result of the detection.

Abstract: An inverter circuit has a digital signal amplitude converter having an input coupled to an inverter circuit input node, and an amplitude converter output. A positive threshold voltage compensation generator has a positive threshold voltage compensation generator input coupled to the amplitude converter output. A negative threshold voltage compensation generator has a negative threshold voltage compensation generator input coupled to the inverter circuit input node, and a negative threshold voltage compensation generator output. A multiplexer has a first input coupled to the positive threshold voltage compensation generator output, a second input, coupled to the negative threshold voltage compensation generator output, and a multiplexer output. An inverter module has an output providing an inverter circuit output node, and an inverter module input is coupled to the multiplexer output.

Abstract: A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected in an identical configuration, as those contained in the comparison circuit to generate a comparison result based on the bias signal generated by the bias generator circuit. A transistor of the comparison circuit receiving the bias signal is connected to a corresponding transistor in the bias generator circuit, in a current mirror configuration. The same bias circuit may be shared by many comparison circuits of corresponding comparator components. The features can be extended to provide hysteresis.

Abstract: A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.

Abstract: A semiconductor device is capable of stably maintaining a voltage level of a shield line, even when a voltage level of an adjacent line is varied. The semiconductor device includes normal lines arranged for transfer of signals, a shield line arranged adjacently to the normal lines, a level shifting circuit for receiving an input signal swinging between a power supply voltage level and a ground voltage level, and shifting the input signal to an output signal swing between the power supply voltage level and a low voltage level lower than the ground voltage level by a predetermined level to output a shifted signal via the shield line, and a signal input unit for transferring the signal provided via the shield line to an output node.

Abstract: One of differential signals is inputted to a first input terminal. The other of the differential signals is inputted to a second input terminal. A first sample hold circuit samples the signal inputted to the first input terminal and hold it thereafter. A second sample hold circuit samples the signal inputted to the second input terminal and holds it thereafter. A comparison unit compares a signal corresponding to a difference between respective output signals from the first and the second sample hold circuits, with a predetermined threshold value. A latch circuit latches an output from the comparison unit. Sample timings of the first and the second sample hold circuits and a latch timing of the latch circuit can be adjusted independently.

Abstract: There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a semiconductor memory device, comprising: a voltage divider for generating detection voltage based on an inputted bulk voltage; and a CMOS circuit for generating a output signal having predetermined logic value determined by the detection voltage wherein the voltage divider includes a first transistor having a gate coupled to a ground voltage and a second transistor having a gate coupled to an internal power voltage and a bulk coupled to the inputted bulk voltage.

Abstract: A semiconductor storage device which includes a memory array including a plurality of memory cells for storing data by using a difference in a threshold voltage and at least one reference cell for storing data indicative of a state of a corresponding memory cell by using a difference in a threshold voltage, a control circuit for determining a read voltage based on data stored by a reference cell corresponding to a memory cell adjacent to a memory cell to be read, a read unit for executing reading from a memory cell to be read by using a determined read voltage, and a write unit for executing writing, when executing writing to a memory cell to be written to bring the memory cell into a written state, data indicating that the memory cell is in the written state to a reference cell corresponding to the memory cell.

Abstract: A wave detector circuit includes: a first transistor having its base and collector connected together, the first transistor receiving an AC signal and a reference voltage at its base and collector; a second transistor having its base connected to the base of the first transistor through a resistor, the second transistor outputting a detected voltage at its collector; and a diode-connected temperature compensation transistor connected between ground potential and the base and the collector of the first transistor.

Abstract: In order to monitor various types of noises which are to be introduced on signals through signal lines on a circuit board and automatically adjust the thresholds for signal state discriminations to make it possible to surely make a signal state discrimination without being affected by these noises even if the amplitude of a signal is reduced for higher-speed transmission and lowered electric power, there is provided a configuration comprising a signal generation unit generating a noise monitor signal; a noise monitor signal line receiving and propagating the noise monitor signal; a noise detection unit detecting a noise which has been introduced into that noise monitor signal propagated through the noise monitor signal line and which affects a state discrimination using a threshold; and a threshold adjustment unit, if the noise detection unit detects the noise, adjusting the threshold such that the state discrimination is not affected by the noise.

Abstract: A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.

Abstract: Example embodiments are directed to an over-voltage protection circuit and method thereof. The over-voltage protection circuit may include a voltage converter, a voltage comparator, a delay unit, and/or a switching unit. The voltage converter may be configured to generate first voltage and second voltages from a supply voltage. The voltage comparator may be configured to compare the first voltage with the second voltage and to generate a control signal according to the comparison result. The switching unit may be configured to determine whether to apply the supply voltage to a chip in response to the control signal. The delay unit may be configured to delay transmission of the control signal to the switching unit by a delay time.

Abstract: A determination unit of a power-on reset circuit of a semiconductor integrated circuit is provided that ANDs (1) a first monitoring signal output from a first monitoring unit for monitoring when a first source voltage supplied from outside the semiconductor integrated circuit reaches a predetermined level and (2) a second monitoring signal output from a second monitoring unit for monitoring when an internal source voltage reaches a predetermined level, to produce a reset signal. In the determination unit, a first PMOS is inserted in series with a second PMOS connected between the first source voltage and a node. The conducting state of the second PMOS is controlled by the second monitoring signal. The conducting state of the first PMOS is controlled by the reset signal. Thus, even when the second monitoring signal becomes unstable and the second PMOS and a first NMOS are simultaneously turned on, the first PMOS is turned off, thus causing no flow of through current.