Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.

Abstract: A circuit with load driver detection includes a reference voltage generation circuit configured to generate a reference voltage based on a reference current, a voltage selection circuit configured to select one of a first detection voltage based on a first driving current through a load and a second detection voltage based on a second driving current flowing through the load, and a detection circuit configured to generate a detection signal, the detection circuit being configured to compare a detection voltage selected by the voltage selection circuit with the reference voltage, wherein the reference voltage is set by the reference voltage generation circuit in response to the load.

Abstract: A power converter includes a charge pump in which transistors transition between conducting and non-conducting states thereby causing said pump capacitors to be interconnected in different arrangements at different times. Among the transistors is one that transitions into a conducting state when a source and gate of that transistor are at equal potentials.

Abstract: An electronic circuit includes a native N-channel Metal-Oxide-Semiconductor (NMOS) transistor and a P-channel Metal-Oxide-Semiconductor (PMOS) transistor. The gates of the native NMOS transistor and the PMOS transistor and the source of the native NMOS transistor are grounded. The drains of the native NMOS transistor and the PMOS transistors are connected to one another and to an output port, and the source of the PMOS transistor is connected to an input voltage.

Abstract: A power detection apparatus is provided. The power detection apparatus includes a first current processing circuit and a second current processing circuit. The first current processing circuit is configured to provide a dynamic bias voltage at a bias terminal in response to a variation of a system power. The second current processing circuit is coupled to the first current processing circuit and is biased under the dynamic bias voltage for outputting a power good signal at an output terminal to represent that the system power is ready when the dynamic bias voltage is greater than a threshold voltage.

Abstract: A temperature sensor includes: a gate voltage generation unit including a bias resistor, a first source resistor, and a first MOS transistor and configured to generate a gate voltage; and a variable voltage output unit including an output resistor, a second source resistor, and a second MOS transistor and configured to generate the variable voltage.

Abstract: A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points and hysteresis voltage is presented. The PoR circuit includes a CMOS circuit with asymmetric rise and fall delays for monitoring wideband supply voltage transients including supply brown out. Being a non-bandgap and non-comparator based circuit, it consumes a very small power and Si area.

Abstract: An improved reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the improved Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (E.g. Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply. This improves the sensing of Vssq-referenced signals in such a system.

Abstract: A power on reset circuit is capable of changing logic level of reset signal at different threshold voltages.

Abstract: A power supply monitoring circuit for monitoring a voltage at a power supply node compared to a reference node, the power supply monitoring circuit comprising a first field effect transistor and first and second voltage dropping components arranged in current flow communication between the power supply node and the reference node and each having first and second nodes, and wherein a first node of the first voltage dropping component is connected to one of the first and second nodes of the field effect transistor, and a gate of the field effect transistor is connected to the second node of the first voltage dropping component, and an output signal is taken from a connection made with the first field effect transistor.

Abstract: A desaturation detection circuit for use between the desaturation detection input of an optocoupler and the output of a power switching device, the desaturation detection circuit comprising: a threshold setting element having an input and an output, the input for connection to the output of a power switching device via one or more diode(s), the threshold setting element being arranged to set a threshold voltage at the input at which the threshold setting element will provide an output at the output of the threshold setting element when the input voltage is exceeded, and a detector having an input connected to the output of the threshold setting element and an output connectable to a desaturation detection input of an optocoupler, the detector being arranged to detect an output at the output of the threshold setting element and in response to provide a control signal at the output of the detector for the desaturation detection input to trigger a desaturation routine in the optocoupler.

Abstract: A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases.

Abstract: A comparator circuit, includes a first power source terminal having a first potential, a second power source terminal having a second potential different from the first potential, a detection voltage terminal, a reference voltage generator coupled between the first power source terminal and the second power source terminal, the reference voltage generator generating a middle potential which is a potential between the first potential and the second potential and outputting the middle potential at a middle potential node, the reference voltage generator further generating a reference voltage, a bias unit coupled between the first power source terminal and the middle potential node, the bias unit receiving the reference voltage and generating a corresponding reference voltage by using the first potential and the middle potential as energy sources thereof, and a comparator unit coupled between the first and second power source terminals and the detection voltage terminal.

Abstract: There is provided a voltage comparison circuit including: a voltage adjustment section connected between a first potential supply line and a first node; a first constant current source connected between the first node and a fixed potential supply line; a switch element connected between a second potential supply line and a second node, and including a control terminal connected to the first node, the switch element operating in accordance with a voltage of the first node; and a second constant current source connected between the second node and the fixed potential supply line.

Abstract: A no-load detecting circuit and the method thereof are disclosed. The no-load detecting circuit may be applied in switching mode power supplies or other circuits. The no-load detecting circuit comprises: a variable resistance circuit coupled in series to a load of the switching mode power supply; and a first comparison circuit coupled to the variable resistance circuit to receive the voltage across the variable resistance circuit, wherein based on the comparison of the voltage across the variable resistance circuit and a first threshold, the first comparison circuit generates a no-load detecting signal indicative of the load status; wherein the equivalent resistance of the variable resistance circuit varies based on the varying of the load of the switching mode power supply.

Abstract: An ADC with comparing circuit units is provided. Each comparing circuit unit comprises a first resistor, a second resistor, and a CMOS. The first and second resistors provide first and second level voltages, respectively. The base of the PMOS is electrically connected to the power source and the base of the NMOS is connected to the source of the NMOS. The signal input port is located at the gate of the CMOS and receives an analog signal. The first level port of the CMOS is located at the source of the NMOS and receives the first level voltage. The second level port of the CMOS is located at the source of the PMOS and receives the second level voltage. The signal output port of the CMOS is located at the drain and outputs a digital signal.

Abstract: Apparatus, systems and methods are provided for protecting a processing system from electromagnetic interference. An integrated circuit comprises a sensing arrangement configured to sense an interference signal and an interference detection module coupled to the sensing arrangement. The interference detection module is configured to detect when a power level associated with the interference signal is greater than a threshold value. In one embodiment, the interference detection module generates an interrupt for a processing system when the power level associated with the interference signal is greater than the threshold value.

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected between the first transistor and the fourth terminal, and a fourth transistor of the second conductivity type connected between the second transistor and the third terminal, the fourth transistor flowing a mirror current depending on a current passing through the third transistor.

Abstract: A reset circuit for resetting and terminating the resetting of a reset target includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), a gate drive circuit configured to switch a drain voltage of the n-channel MOSFET from a low level to a high level when a power supply voltage exceeds a predetermined threshold, a sink circuit configured to maintain the drain voltage at the low level by sinking a current flowing from a drain side of the n-channel MOSFET to the sink circuit, and a block circuit configured to block the current sinking to the sink circuit when the power supply voltage exceeds the predetermined threshold. The low level indicates a state where the reset target is in a reset state and the high level indicates a state where the reset state of the reset target is terminated.

Abstract: A chopper comparator with a novel structure is provided. The comparator includes an inverter, a capacitor, a first switch, a second switch, and a third switch. An input terminal and an output terminal of the inverter are electrically connected to each other through the first switch. The input terminal of the inverter is electrically connected to one of a pair of electrodes of the capacitor. A reference potential is applied to the other of the pair of electrodes of the capacitor through the second switch. A signal potential input is applied to the other of the pair of electrodes of the capacitor through the third switch. A potential output from the output terminal of the inverter is an output signal. A transistor whose channel is formed in an oxide semiconductor layer is used as the first switch.

Abstract: A comparator circuit, includes a first power source terminal having a first potential, a second power source terminal having a second potential different from the first potential, a detection voltage terminal, a reference voltage generator coupled between the first power source terminal and the second power source terminal, the reference voltage generator generating a middle potential which is a potential between the first potential and the second potential and outputting the middle potential at a middle potential node, the reference voltage generator further generating a reference voltage, a bias unit coupled between the first power source terminal and the middle potential node, the bias unit receiving the reference voltage and generating a corresponding reference voltage by using the first potential and the middle potential as energy sources thereof, and a comparator unit coupled between the first and second power source terminals and the detection voltage terminal.

Abstract: A resume and reset (RSMRST) signal output circuit, for outputting a low level voltage RSMRST signal, includes a first switch circuit, a delay circuit, and a second switch circuit. The first switch circuit receives a first voltage signal and converts the first voltage signal to a second voltage signal. The delay circuit is charged by the second voltage signal and outputs the second voltage signal it is when fully charged. The second switch circuit receives the second voltage signal and outputs the low level voltage RSMRST signal. The delay circuit is charged during a first state and discharged during a second state.

Abstract: A detection circuit is coupled to an output terminal of a driver circuit. The detection circuit includes a comparator to compare a signal at the output terminal to a reference signal corresponding to a signal that would be generated if a capacitive load having a relatively high capacitance value were connected to the output terminal. Output of the comparator is sampled at a predetermined time after the driver circuit provides the drive signal. An error signal is generated when the sampled output indicates that the capacitive load having the relatively high capacitance value is actually connected to the output terminal.

Abstract: A detection circuit is disclosed in specification and drawing, where the detection circuit includes a current source, a voltage-current converter and a current comparator. The voltage-current converter is configured to acquire a receiving current from the current source by comparing a reference voltage with an input voltage of a detecting terminal. The current comparator is configured to output an output voltage by comparing a steady current with an output current based on the receiving current.

Abstract: Methods and devices for detecting single-event transients in combinational logic circuits and other circuits. A sensing circuit detects a voltage or current deviation at a bulk contact node of a transistor. Output of the sensing circuit is amplified and used to flip a latch. Output of the latch may be evaluated and used in possible error correction measures.

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals connected to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected in series with the first transistor, a fourth transistor of the second conductivity type connected in series with the second transistor, a fifth transistor of the second conductivity type through which a mirror current depending on a current flowing through the third transistor, a sixth transistor of the second conductivity type flowing a mirror current depending on a current flowing through th

Abstract: An electronic device is provided that includes a power-on-reset (POR) circuit. The POR circuit includes a trigger stage configured to change an output if a first power supply voltage level exceeds a threshold voltage level and a first inverter and a second inverter being cross-coupled. An output of the second inverter is the POR output of the power-up reset circuit. The output is coupled to the trigger stage for switching the trigger stage off in response to a change of a signal at the output of the second inverter. The first inverter is dimensioned to follow with a voltage level at an output an initially rising slope of the first power supply voltage level and the second inverter is dimensioned to keep a voltage level at an output at a second power supply voltage level during the initially rising slope of the first power supply voltage level.

Abstract: A corner detector comprises a PMOS threshold voltage detector and an NMOS threshold voltage detector, the PMOS threshold voltage detector is composed of a first clock terminal, a first CMOS inverter, a first capacitor, a PMOS threshold voltage function generator and a first voltage output terminal, wherein the PMOS threshold voltage function generator is electrically connected to the first capacitor and applied to generate a first formula of voltage signal as a function of threshold voltage, the NMOS threshold voltage detector is composed of a second clock terminal, a second CMOS inverter, a second capacitor, an NMOS threshold voltage function generator and a second voltage output terminal, wherein the NMOS threshold voltage function generator is electrically connected to the second capacitor and applied to generate a second formula of voltage signal as a function of threshold voltage.

Abstract: In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.

Abstract: A circuit arrangement for operating voltage detection has a detection block (1) and a control block (2). Detection block (1) has a first transistor (P1) that is connected between a first supply voltage terminal (VDD) and a first node (K1) and has a first control terminal (S1), a first resistor element (R1) that is connected between first node (K1) and second supply voltage terminal (VSS), a second transistor (P2) that is connected between first supply voltage terminal (VDD) and a second node (K2) and has a second control terminal (S2), a second resistor element (R2) that is connected between second node (K2) and second supply voltage terminal (VSS), a first switch (N1) that connects first node (K1) to second control terminal (S2), and a third resistor element (R3) that is connected between second control terminal (S2) and first supply voltage terminal (VDD).

Abstract: Power up circuit. An example power up circuit includes a switch for charging a power node of an electronic device. A level detector is used for monitoring charge level of the power node. Further, the power up circuit includes one or more power switches for providing current to the electronic device based on the charge level.

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract: A power-on reset circuit includes a first circuit and a second circuit. The first circuit include a first NMOS transistor having a gate controlled by a low voltage supply VDD_L, a resistor connected between the source of the first NMOS transistor and a voltage supply VSS that is lower than VDD_L, and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor. The second circuit includes a first PMOS transistor having a source connected to VDD_L, a second PMOS transistor having a source connected to the drain of first PMOS transistor, a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, and an inverter configured to output a signal in response to the power on of the high voltage supply VDD_H and the low voltage supply VDD_L.

Abstract: A buffer circuit including an input terminal capable of receiving an input signal and an output terminal capable of being connected to a capacitive load, including an output circuit a series connection, between two terminals of application of a power supply voltage, of a first MOS transistor, a first and a second resistor of adjustable values, and a second MOS transistor, and means for controlling said first and second transistors receiving the input signal The buffer circuit further includes means for comparing the voltage on the output terminal of the circuit with at least one threshold voltage, the comparison means being connected to said control means.

Abstract: A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

Abstract: In today's environment class-D amplifiers are used to provide an integrated solution for applications such as powered audio devices due to their advantages in power consumption and size over more traditional analog amplifiers. Due to power output requirements, the output stages of power drivers such as class-D amplifiers require a supply voltage in excess of the technologically allowed voltage for the switches in the output stage. A level shifter is used to ensure voltages supplied to the output switches do not exceed the technological limits. An ideal level shifter should provide the optimal voltage swing to output switches under all process, supply voltage and temperature (PVT) variations. The ideal level shifter should also provide fast transitions when the control signal changes from high to low and low to high.

Abstract: An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level.

Abstract: A comparator circuit (300) has a first field effect transistor (FET) (307) with a supply voltage (301) connection and a diode connected FET (303) connected in series to form the first circuit leg of the comparator (300). A second diode connected FET (309) and a second FET (305) in series form the second circuit leg. The first FET (307) and said second FET (305) are approximately equal sized FETs. Another embodiment is an integrated circuit (401) with two n-channel FETs. A first diode connected FET (303) is connected to the first n-channel FET (307) in series to form the first circuit leg of a comparator (300) and a second diode connected FET (309) is connected to a second n-channel FET (305) in series to form the second circuit leg of the comparator. The two n-channel FETs that form the differential pair are approximately equal in size. The trip point is high with respect to the supply voltage.

Abstract: Methods are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature.

Abstract: Apparatus are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature.

Abstract: A circuit for detecting noise peaks on the power supply of an electronic circuit, including at least a first transistor having its control terminal connected to a terminal of application of a first potential of a supply voltage of the circuit and having a first conduction terminal connected to a terminal of application of a second potential via at least one first resistive element, the second conduction terminal of the first transistor providing the result of the detection.

Abstract: A reset signal generating circuit outputs a reset signal having a sufficient pulse width even when the power supply voltage is fluctuated. A node B reaches a high level during a power-on reset and is at a low level during operation. When a power supply (Vcc) fluctuates during operation and as soon as a node C reaches a high level, a switch element MN50 turns on, the node B is decreased to a low level, and a stable low-level reset signal RST1 is outputted. When the node B reaches a low level, a switch element MN51 turns off with a delay and capacitors 104 and 105 are gradually charged by a charging circuit 112. When the potential at the node B exceeds a threshold level of an inverter circuit 106, the reset signal RST1 is brought back to a high level, the reset is cancelled, the switch element MN50 is turned off, and the switch element MN51 is brought to be in an on-state again (FIG. 1).

Abstract: A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.

Abstract: A semiconductor device is capable of stably maintaining a voltage level of a shield line, even when a voltage level of an adjacent line is varied. The semiconductor device includes normal lines arranged for transfer of signals, a shield line arranged adjacently to the normal lines, a level shifting circuit for receiving an input signal swinging between a power supply voltage level and a ground voltage level, and shifting the input signal to an output signal swing between the power supply voltage level and a low voltage level lower than the ground voltage level by a predetermined level to output a shifted signal via the shield line, and a signal input unit for transferring the signal provided via the shield line to an output node.

Abstract: In order to monitor various types of noises which are to be introduced on signals through signal lines on a circuit board and automatically adjust the thresholds for signal state discriminations to make it possible to surely make a signal state discrimination without being affected by these noises even if the amplitude of a signal is reduced for higher-speed transmission and lowered electric power, there is provided a configuration comprising a signal generation unit generating a noise monitor signal; a noise monitor signal line receiving and propagating the noise monitor signal; a noise detection unit detecting a noise which has been introduced into that noise monitor signal propagated through the noise monitor signal line and which affects a state discrimination using a threshold; and a threshold adjustment unit, if the noise detection unit detects the noise, adjusting the threshold such that the state discrimination is not affected by the noise.

Abstract: A voltage detection circuit of the present invention includes an NMOS transistor diode-connected, a gate and a drain thereof being supplied with a power supply voltage, a resistor connected between a source of the NMOS transistor and a ground potential, and a source voltage detection circuit receiving a voltage of the source, wherein an NMOS type transistor is employed as the NMOS transistor, a channel width and a channel length of the NMOS type transistor being set in such a manner that an operating point on a VG-ID curve of the NMOS type transistor may come to a certain point, at the certain point, a drain current of the NMOS type transistor being constant even if the temperature fluctuates.

Abstract: A voltage comparator for comparing a reference voltage with a threshold, includes a first voltage-to-current converter to convert a reference voltage that determines the threshold into a reference current that depends on the reference voltage, a second voltage-to-current converter to convert the comparison voltage into a comparison current that depends on the comparison voltage, and an output stage to output a digital output level, wherein the digital output level depends on the reference current and the comparison current.

Abstract: A voltage detection circuit for accurately detecting a voltage that is unaffected by fluctuation due to variations in transistor characteristics and threshold voltage. The voltage detection circuit includes a reference current generating section and a detecting section. The reference current generating section includes a voltage-controlled current source that includes a control terminal, a reference terminal and an output terminal. The reference current generating section generates an output current that serves as a reference current and output to a current mirroring circuit. The detecting section includes a number of voltage-controlled current sources each with the same configuration as the voltage-controlled current sources in the current generating section. A potential to be detected is input into the detecting section. A target potential is calculated as the set potential multiplied by the number of voltage-controlled current sources in the detecting section.

Abstract: A comparator with a fixed reference voltage (self bias) for an oscillator is disclosed. The comparator includes: a depletion MOS network to form a source current, wherein the gate and the source has a connection; and an enhanced MOS transistor, wherein the drain or the source connects with the depletion MOS transistor in series. The gate of the enhanced MOS transistor receives an input voltage when the input voltage is lower than the reference voltage, and the comparator outputs a high level voltage, or the enhanced MOS transistor outputs a low level voltage if the input voltage is higher then the reference voltage. Moreover, the oscillator's comparator has a reference voltage that is independent from temperature and supply voltage source.

Abstract: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability.