Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

Abstract: A comparator circuit with dynamic biasing comprises a comparator, first dynamic biasing generator, first extra biasing device, second dynamic biasing generator, and second extra biasing device. The comparator includes a biasing circuit, input stage, active loads, and output terminal. The input stage has a first input terminal, second input terminal, first current path, and second current path. The comparator is configured to output an output signal at the output terminal according to the first input signal and second input signal. The first dynamic biasing generator is coupled between a first detection node and the first extra biasing device coupled to the biasing circuit. The second dynamic biasing generator is coupled between a second detection node and the second extra biasing device coupled to the biasing circuit. The first and second detection nodes are between the input stage and the active loads.

Abstract: Aspects for sensing total current of distributed load circuits independently of a spatial profile of the total current using distributed voltage averaging are disclosed. In one aspect, a current sense circuit is configured to sense total current of a distributed load circuit independently of where current is distributed. The current sense circuit includes distributed voltage averaging circuits configured to determine average voltages of the distributed load circuit based on voltages sensed at multiple resistive paths corresponding to a distribution network configured to provide voltage to the distributed load circuit. An amplifier includes an output node having an output voltage that is proportional to total current flowing in the distributed load circuit. The current sense circuit allows for sensing total current independent of where the current flows, providing more accurate current sensing compared to sensing current in one area of the distributed load circuit.

Abstract: A method with function parameter setting and an integrated circuit using the same are provided. The integrated circuit includes a function pin coupled to an external setting unit, a switch unit, and first and second function adjustment circuits. The first function adjustment circuit includes first and second current sources. The second function adjustment circuit detects a percentage of a divided voltage at the function pin, to provide a reference value and to set a second function parameter. The first function adjustment circuit uses the first current source to detect a first voltage detecting value at the function pin, and compares the first voltage detecting value with a default value. The switch unit switches the first and second current sources according to a compare result. The present invention adopts an integrated circuit for switching a plurality of current sources and detections, and may determine more resistance value setting intervals.

Abstract: An RC triggered ESD protection device comprises a discharge transistor, a driver circuit and a trigger circuit. The trigger circuit comprises a plurality of native NMOS transistors connected in parallel with a plurality of PMOS transistors operating as resistors. The relatively small resistance of the plurality of native NMOS transistors helps to keep a stable RC time constant value so that the ESD protection device can avoid a leakage current during a power up operation.

Abstract: A semiconductor device 3 for sensing a physical quantity adjusts the output characteristic of a pressure sensor, for example, based on trimming data stored in an EPROM 34. A comparator 311 compares an input voltage given to a terminal 43 and a predetermined reference voltage, and delivers a write control signal for EPROM 34. When the comparator 311 delivers a Low signal for the EPROM 34, a first gate circuit 312 provided between the terminal 43 and a temperature sensor 32 connects the terminal 43 and the temperature sensor 32. A second gate circuit 313 provided between the terminal 43 and a pull-down resistor 314 disconnects the terminal 43 and the pull-down resistor 314. The operational voltage of the temperature sensor 32 is lower than the reference voltage, and the terminal 43 is used as an output terminal for the temperature sensor 32.

Abstract: A method for producing a structure includes the steps of etching a first substrate of an integrated member including, in sequence, the first substrate, an etching stop layer, and a seed layer, from a surface of the first substrate opposite the surface adjacent to the etching stop layer to form a hole or a plurality of gaps in the first substrate in such a manner that part of a surface of the etching stop layer is exposed, partially etching the etching stop layer from the surface of the etching stop layer exposed to expose part of a surface of the seed layer, and forming a metal member by plating using the seed layer as a seed to charge a metal into at least part of the hole or the gaps.

Abstract: A voltage change detection device, which reduces a deviation of a detection potential and detects a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node. The detection signal generator generates a detection signal indicating that the power supply potential has crossed a predetermined detection potential.

Abstract: An object is to widen detection range of current. A current detection circuit includes a first resistor, which is connected to a first connection terminal and a second connection terminal; a second resistor, which is connected to the first resistor; a third resistor, which is connected to the first resistor; a first transistor, a source of which is connected to the second resistor; a second transistor, a source of which is connected to the third resistor, and a drain and a gate of which is connected to a gate of the first transistor; a third transistor, a source of which is connected to the source of the second transistor, and a gate of which is connected to the drain of the first transistor; and a fourth resistor, which is connected to the drain of the third transistor, and to which a voltage is input.

Abstract: A voltage change detection device, which reduces a deviation of a detection potential and detects a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node. The detection signal generator generates a detection signal indicating that the power supply potential has crossed a predetermined detection potential.

Abstract: An apparatus and method for charging a battery includes a battery to be charged, a power delivery path configured for delivering power to the battery, and an integrated switching battery charger configured for charging a battery by delivering output power to the battery via the power delivery path based on input power from an input power source. The integrated switching battery charger includes an output voltage regulation loop and an input voltage regulation loop, both of which are configured to control the output current flowing out of the integrated switching battery charger to the battery. The input or output voltage regulation loops are further enhanced by adding a current source which is proportional to absolute temperature from the regulated voltage to the control voltage for the purpose of either regulating peak power from the source or to maximize energy storage in the battery as a function of temperature.

Abstract: A current source generates a reference current. A first transistor is a depletion-type MOSFET arranged such that one terminal thereof is connected to the current source and its gate is connected to its source. A second transistor is an enhancement-type MOSFET arranged such that one terminal thereof is connected to the other terminal of the first transistor, the other terminal thereof is connected to a fixed voltage terminal, and its gate and drain are connected. A third MOSFET is an enhancement-type P-channel MOSFET arranged such that one terminal thereof is connected to the current source, the other terminal thereof is connected to the fixed voltage terminal, and its gate is connected to a connection node connecting the first and second transistors. A constant voltage circuit outputs at least a voltage that corresponds to the gate voltage of the third transistor or a voltage that corresponds to the gate voltage thereof.

Abstract: An output stage includes a first transistor pair with a first conductivity type and a second transistor pair with a second conductivity type. The source connections of the first and second transistors in the first transistor pair and of the first and second transistors in the second transistor pair are respectively connected to a first and a second circuit node. The output stage further includes a first current mirror with the first conductivity type and a second current mirror with the second conductivity type. The current mirror transistors are connected to the signal output. The signal input is connected to control connections of the first transistors in the first and second transistor pairs. A second connection of the second transistor in the first transistor pair is connected to the second current mirror, and a second connection of the second transistor in the second transistor pair is connected to the first current mirror.

Abstract: A voltage change detection device is provided, which can reduce a deviation of a detection potential and can detect a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node.

Abstract: An electric circuit device includes: a power supply line; a load circuit; a current supply controller which compares a voltage of the power supply line with a certain voltage; and a current supply circuit which supplies a electric current from the power supply line to the load circuit and changes the electric current during a supply of the electric current.

Abstract: A circuit arrangement for producing a defined output signal in CMOS integrated circuit is provided in which the output of a sensor signal conditioning circuit is connected to the drain terminal of a first N channel depletion transistor, to a source terminal of a second N channel depletion transistor and to the output (OUT) of an integrated CMOS circuit. The gate terminals of the first and second N channel depletion transistors are connected to the output (VP) of a control circuit and the first terminal of a discharge resistance. The second terminal of the discharge resistance and the source terminal of the first N channel depletion transistor are connected to a potential VSS, and the drain terminal of the second N channel depletion transistor is connected to a potential VDD.

Abstract: A time constant calibration device includes: a first voltage generating circuit utilizing a first current passing through a capacitive component to generate a first voltage; a second voltage generating circuit utilizing a second current passing through a resistive component to generate a second voltage; and a comparing circuit for comparing the first voltage with the second voltage to generate a comparing signal, wherein the first voltage generating circuit comprises an analog adjusting component for adjusting the first voltage according to the comparing signal until the first voltage is equal to the second voltage, whereby an RC time constant defined by an equivalent capacitance corresponding to the first current passing through the capacitive component and an equivalent impedance corresponding to the second current passing through the resistive component reaches a predetermined value.

Abstract: Embodiments include a comparing device having hysteresis characteristics and a voltage regulator using the same. The voltage regulator includes a comparator which compares a comparison voltage with a reference voltage and outputs a result of the comparison, a switching controller which generates a plurality of switching signals in response to the comparison result, resistors connected in the form of a string to divide the comparison voltage into a plurality of voltages, and a switching box which selects one of the plural voltages as the comparison voltage in response to the switching signals.

Abstract: Power savings are achieved for digital data transport over short distances by using the characteristics of resonant LC circuits. Economy of circuit elements is achieved by enabling a single pair of resonant circuits to drive large numbers of digital data lines or nodes in parallel. This maximizes power efficiency and minimizes area and cost. Resistance is minimized by insuring that all switches in the current path are fully “ON” whenever significant current is flowing through them. All other parasitic resistances in the circuits, consisting primarily of parasitic interconnect resistances, are minimized. This enables the data transmission circuits to achieve maximum Q or quality factor, which minimizes power dissipation.

Abstract: Embodiments of methods and apparatus for receiving data are disclosed. More particularly, methods of receiving a current mode signal, which can improve a signal to noise ratio (SNR) according to a change in a power supply voltage, and current mode comparators and semiconductor devices that use the methods are provided. A method of receiving a current mode signal includes receiving a reference current signal and a data current signal through a channel and generating a sensing voltage based on a difference between the reference current signal and the data current signal, varying a transconductance to reduce an input resistance of the current mode comparator in inverse proportion to an increase in a power supply voltage supplied to the current mode comparator, and converting the sensing voltage into a CMOS level output signal using the current mode comparator.

Abstract: A step motor driving circuit is provided. An exemplary step motor driving circuit includes an input voltage source set, a reference voltage source, a voltage level shift unit, a logic unit, a reset voltage source, and an output voltage terminal. The input voltage source set provides an input voltage set. The reference voltage source provides a reference voltage. The voltage level shift unit raises one of the levels of the input voltage set to a level of the reference voltage. The logic unit receives the reference voltage and the input voltage set and outputs a control voltage. The reset voltage source outputs a reset voltage to reset the logic unit. The output voltage terminal receives the control voltage and outputs an output voltage.

Abstract: In one embodiment, a method for a control interface includes: receiving a signal conveying bits of information over a single line; and for each bit of information, comparing the proportion of time that the signal on the single line is low versus the proportion of time that the signal on the single line is high for a respective bit period defined from one operative edge of the signal to the next operative edge of the signal in order to determine a logic value for that bit of information.

Abstract: A voltage comparator for comparing a reference voltage with a threshold, includes a first voltage-to-current converter to convert a reference voltage that determines the threshold into a reference current that depends on the reference voltage, a second voltage-to-current converter to convert the comparison voltage into a comparison current that depends on the comparison voltage, and an output stage to output a digital output level, wherein the digital output level depends on the reference current and the comparison current.

Abstract: A brown-out-reset circuit having programmable power and response time characteristics. These characteristics may be programmed over an n-bit wide bus for 2n different characteristics ranging from very low power consumption and slower response time to very fast response time and higher power consumption. A serial one wire bus may be used instead of the n-bit wide bus.

Abstract: A high-speed receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The high-speed receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the high-speed receiver assembly.

Abstract: A current mode comparator for a semiconductor device is disclosed. The current mode comparator may include a logic circuit coupled to a voltage sensing node, a first cascode coupled to the voltage sensing node and a first power node, and a second cascode coupled to the voltage sensing node and a second power node. The logic circuit may convert a voltage of the voltage sensing node to an output signal.

Abstract: A precise over-voltage comparator exhibits zero-waiting-current characteristics during normal working conditions. An NMOS transistor is used in conjunction with other circuit elements to regulate the over-voltage comparator. For normal power supply voltages, the comparator stays in standby status and does not consume quiescent current.

Abstract: Supply voltage level detectors are disclosed. The supply voltage level detector comprises a voltage source divider dividing a voltage source to generate a detection voltage, a bandgap reference voltage generator, a comparator comparing the detection voltage with a bandgap reference voltage generated by the bandgap reference voltage generator to determine if the voltage source is ready, a control circuit, and a forcing circuit. To ensure reliability of the comparison result, the control circuit disables the comparing device until the bandgap reference voltage is available. The forcing circuit is coupled to the output terminal of the comparing device and is controlled by the control circuit. When the comparing device is disabled, the forcing circuit forces the voltage level of the output terminal of the comparing device to a specific value indicating the voltage source is unready.

Abstract: An embodiment of a device for monitoring voltages of a motherboard includes: a comparator having an input terminal connected to a reference voltage and the other input terminal connected to a voltage of the motherboard; an electrical switch having a first terminal connected to an output terminal of the comparator, a second terminal connected to a power source, and a third terminal being grounded; and a light emitting diode (LED) including a cathode connected to the second terminal of the electrical switch and an anode connected to the power source. The electrical switch is turned on when the first terminal of the electrical switch receives a controlling signal from the comparator. Then the LED emits light to show an abnormal state of the voltage of the motherboard.

Abstract: A disclosed method of producing a semiconductor device includes the steps of (A) forming a gate electrode and a trimming fuse on a semiconductor substrate; (B) forming a side wall insulating film covering the gate electrode and the trimming fuse; (C) forming a conductive film on the side wall insulating film and patterning the conductive film to form an etching stop layer and a resistance element; (D) forming a side wall on the sides of the gate electrode; (E) repeating, one or more times, sub-steps of forming an interlayer insulating film and of forming an upper wiring layer, and then forming a passivation film; (F) removing the passivation film and the interlayer insulating film in the trimming opening forming area until the etching stop layer is exposed; and (G) forming the trimming opening by removing the etching stop layer in the trimming opening forming area.

Abstract: A power down reset circuit for asserting a signal when a first VDD voltage falls below a voltage threshold. The circuit has at least one diode coupled to the first VDD voltage. The at least one diode is configured to produce a second voltage. At least one capacitor is coupled to the at least one diode to maintain the second voltage. A voltage detector asserts a signal when the first VDD voltage drops below a threshold level. The voltage detector is powered by the second voltage and is coupled to the at least one diode.

Abstract: A chopper comparator has inverters in input and output stages including NMOS transistors to control connection and disconnection of an inverter circuit of each inverter. During a non-operation period of the chopper comparator, parts of the inverters are disconnected form the ground based on a signal supplied to gates of the NMOS transistors.

Abstract: A semiconductor device is constructed by at least one reference voltage generating circuit for generating a reference voltage, a plurality of input voltage pads for receiving input voltages, a control signal pad for receiving a control signal, and a plurality of input buffers. Each of the input buffers amplifies a difference between one of the input voltages and the reference voltage to generate an output voltage, and includes a switch connected between the reference voltage generating circuit and one of the input voltage pads and controlled by the control signal.

Abstract: A buffer has an amplifier that receives an external signal, a reference voltage, and outputs an amplified signal. The amplified signal is responsive to the difference between the external signal and the reference voltage. An inverter receives the amplified signal and generates an inverted signal. A voltage supply circuit is configured to provide an adjusted power supply voltage to the inverter responsive to the reference voltage. A ground voltage supply circuit is configured to provide an adjusted ground voltage to the inverter responsive to the reference voltage.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of the positive charge pump is begun after the charging of the negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from a negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected.

Abstract: In a conventional signal transmission device that transmits signals fed thereto to another device through a transformer, when the direction of the current flowing through the primary coil of the transformer is switched by switching devices connected in series between two different potentials, the timing with which the switching device that has been receiving current up to the moment is turned off is delayed from the timing with which the other switching devices are turned on or off to reduce overshoots and undershoots. This, however, may distort the square wave appearing across the secondary coil and make correct signal transmission impossible. To prevent this, a signal transmission device of the invention additionally has a waveform adjustment circuit that controls the delay time produced by a timing adjustment circuit according to changes in the states of control signals.

Abstract: A differential amplifier power supply is derived from the same source that generates the reference voltage for the differential amplifiers. This will ensure the direction of voltage level shifts of these two voltages to be in tandem. That is, these two voltages will move in the same direction due to any variations in the source since they are generated from the same regulator. In this way receiver timing errors can be significantly reduced in source synchronous and common clock interfaces.

Abstract: A method for reducing static power dissipation in a semiconductor device is provided. The method is characterized in that utilizing a simple control device connecting with a MOS device, serving for a drain voltage controller, instead of the conventional voltage supply directly connected with the drain. The control device comprises two input terminals and an output terminal. One of the two input terminals is connected with a voltage supply, the other of the two input terminals is connected with a control signal. The output terminal of the control device is connected to the drain of the MOS device. When the control signal is activated, the output terminal of the control device is grounded and thus the drain is grounded. Thereby, all of the possible leakage paths induced by the drain voltage are inhibited. While the control signal is un-activated, the output terminal of the control device provides a supply voltage to the drain.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a signal generation circuit which provides a differential current. The resolving circuit is coupled to a latching circuit. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal setup and hold times are inherently very small due to the high intrinsic bandwidth of the receiver. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 m Volt) voltage differences, reduced capacitive loading, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: The present invention provides a current comparator that reduces both input and output resistance. The current comparator positions a resistive feedback network in a first inverting amplifier of an input stage. The input stage according to the present invention can include a first and a second input terminal, an output terminal, a reference current source, a load circuit, a driving unit, and a resistive circuit. The reference current source supplies a reference current to the first input terminal. The load circuit supplies a first current to the output terminal. The first current is preferably equal to the reference current. The driving unit generates a prescribed output voltage by controlling the first current based on an input current applied to the second input terminal. The resistor is coupled between a control terminal of the driving unit, the second input terminal and the output terminal.

Abstract: A method and arrangement for determining state information of a high-power semi-conductor, the power semiconductor comprising a collector (C), an emitter (E) and a gate (G), and a gate driver (3) comprising an auxiliary voltage input is connected to the gate of the power semiconductor. The method is characterized by steps wherein the auxiliary voltage (Vcc) of the gate driver (3) is used as reference voltage, saturation voltage (Vsat) of the power semiconductor (1) is compared with the reference voltage by using an optoisolator (4), and a detection signal of state information is generated depending on the magnitudes of the saturation voltage and the reference voltage.

Abstract: A level detector enables high speed operation at low voltage with eliminating dependency to fluctuation of a power source voltage and tolerance in a device, and further permits stable operation. The level detecting circuit performs predetermined level shifting of a voltage level of an input signal input from a load voltage generating circuit, with a resistance type potential division by a voltage dividing resistor element using a reference power source voltage independent of a power source voltage to be supplied to own circuit. In this case, a differential amplifier feeds an output depending upon a difference between a level shifted signal from the level shifter and a predetermined reference voltage for leading an output thereof as a detection output. Also, since the reference power source independent of the power source voltage is used, influence of fluctuation of the power source voltage for the circuit is restricted to realize stable operation.

Abstract: A current-switching method and circuit is provided for use with digital-to-analog converters (DACs) to provide improved compliance and linearity in the output current characteristic. In the current-switching circuit, an additional transistor that is set to a permanently-on state is connected at the output port of the current-switching circuit, which can help increase the output impedance of the current-switching circuit. Moreover, the problem of simultaneous switching-off of two control transistors can be eliminated by connecting the gate of one transistor to a reference voltage whose magnitude is set between the logic-high and logic-low voltage states of the input digital signal. The current-switching method and circuit can therefore meet the requirements of 3 V working voltage with 1.2 V output compliance and the requirements of 10 bits linearity in the output current characteristic.

Abstract: A collector of a transistor Q3 to a base of which an amplifier signal Sa generated from the differential amplifier is input is connected with one end of the resistive element RC1 and one end of a resistive element RC2. Other ends of the resistive element RC1 and RC2 are connected with a power source level Vcc and a base of the transistor Q3, respectively. When the emitter of the transistor Q3 is shorted to a ground level GND, for example, in case that a capacitive element CP is not charged enough, the electric potential of the collector of the transistor Q3 is lowered, and the electric potential of the base of the transistor Q3 is also lowered. Accordingly, inflow of the excess current to the transistor Q3 can be prevented.

Abstract: An interface circuit includes first and second current mirrors, first and second input circuits, and a reference setting unit. Each of the first and second current mirror circuit has a current input terminal and a current output terminal. The first input circuit has a first transistor having a gate to which an input signal is input and a drain connected to the current output terminal of the first current mirror circuit. The second input circuit has a second transistor having a gate to which a predetermined reference voltage is input and a drain connected to the current output terminal of the second current mirror circuit. The reference setting unit is connected to the current input terminal to set a current amount flowing to the current output terminal as a logic determination level of the first transistor. A method of setting a determination level for the interface circuit is also disclosed.

Abstract: Disclosed herein is a voltage judgment circuit comprising one or more diodes inserted in the forward direction of a judgment voltage, a current extraction section for extracting a forward current of the diodes, and a comparison section for comparing an output current from the current extracting section with a specified current value to input the comparison results. According to the voltage judgment circuit of the present invention, the discharge after the charging can be prevented to perform the voltage judgment using a low consumption current with high accuracy. A battery cell pack having the above voltage judgment circuits also performs a similar judgment.

Abstract: A comparator circuit providing for improved symmetry of operation. The circuit includes two delay paths to facilitate rising and falling input transitions. Such paths are made up of an equal number and type of current mirrors. The circuit also includes an input differential pair wherein both delay paths are coupled to a single transistor of the pair.

Abstract: In a system, a low-voltage detecting circuit includes an oscillating section for outputting a rectangular wave proportional to a supply voltage according to a control signal selected by the user and produced by a micro-controller unit, and a low-voltage detecting signal generator for counting the number of waves present in the rectangular waveform and comparing the count value with a reference value preset by the user to produce a detection signal for detecting a voltage drop in the system.

Abstract: A semiconductor integrated circuit device is provided having a low-amplitude input/output interface for inputting or outputting an input/output signal synchronously with a clock signal and transferring the input/output signal with an amplitude corresponding to a power supply voltage to or from an external command unit. A first differential circuit to be practically continuously operated is used as an input circuit for receiving a clock signal supplied from an external clock unit. In addition, a second differential circuit is provided which is intermittently operated in accordance with the clock signal to sample an input signal in accordance with an internal clock signal generated by the first differential circuit while the second differential circuit is operated and holds the sampled signal while the second differential circuit is not operated. This second differential circuit is used as an input circuit for receiving a low-amplitude input signal inputted synchronously with the clock signal.