Abstract: A zero current enable circuit and zero current enable method are disclosed. The integrated circuit features at least one sense circuit and a logic gate. The sensing circuit combines a broken band gap reference voltage, a voltage divider, a voltage clamp, a comparator, and a logic gate to generate an enable signal.

Abstract: A current comparator arrangement has first and second inputs (100, 103), an output (105), and cross-coupled transistors (MP1, MP2) which form a latching circuit. The arrangement also includes current stores (MP3, MP4), the input currents to be compared being fed to the current stores in a selected forward differential order for storage therein during a first portion of a clock period in which the cross-coupled latching circuit is reset. During a second portion of the clock period the input current connections are reversed, thereby reversing their differential order, and the reverse order currents are supplied together with the stored forward order currents to the latching circuit. This cancels common mode and offset currents so that they do not affect the comparison of the input currents.

Abstract: An overcurrent detector circuit (21) for a power MOSFET (22) is described. The overcurrent detector circuit (21) generates a bias voltage corresponding to the drain to source voltage of the power MOSFET (22). The drain to source voltage correlates directly to the current being conducted by the power MOSFET (22). An overcurrent condition occurs when the power MOSFET (22) exceeds a predetermined current. The bias voltage is applied to a transistor (24) for generating a current. A current source (29) couples to the transistor (24). The current provided by the transistor equals the reference current of the current source (29) when the power MOSFET conducts the predetermined current. The overcurrent detector circuit (21) generates a signal indicating a overcurrent condition does not exist when the reference current is greater the current provided by the transistor.

Abstract: This invention relates to the operation of common electronic comparators and particularly to an electronic circuit with a comparator for the operational test of integrated circuits (ICs). According to the invention, the electronic circuit comprises a common comparator with an input, an output and a reference input. To the reference input a constant reference voltage is applied. The input voltage to be compared with the reference voltage is superimposed to a time-dependent signal and the resulting voltage is applied to the input of the comparator.

Abstract: A power semiconductor device (4) has a main current carrying section (4a) with a number of parallel-connected active device cells (5) and a first main electrode (6) coupled to a first terminal (2), a second main electrode (7) connected to a second terminal (3) and a control electrode (8) and a sense current carrying section (4b) with at least one sense cell (5a) similar to the active device cells (5) and having a first main electrode (6) coupled to the first terminals (2) and a second main electrode (9). A current sensing arrangement (10) has a first resistor (R1) coupling the second main electrode (9) of the sense current carrying section (4b) to the second terminal (3), a second resistor (R2) similar to the first resistor (R1) and a current source (11) coupled in series with the second resistor to the second terminal (3) for supplying a reference current (Ir) through the second resistor (R2).