Abstract: An integrated circuit having multiple switched-capacitor delta-sigma data converter circuits includes compensation for voltage reference error due to leakage current that causes reference voltage droop. The reference filter capacitor terminal voltage is maintained by periodic connection to the reference feedback capacitor(s) that are alternately connected to a voltage reference buffer, and the leakage into the reference feedback capacitor networks of disabled converter circuits causes reference voltage droop. The compensation is either determined from the number of converter circuits that are disabled, or from an error between the filter capacitor voltage and a separate voltage reference, and may be applied by adjusting a resistance selectively coupled between the voltage reference buffer output and the filter capacitor, feedback applied to the voltage reference buffer or its input source.

Abstract: A low pass filter embedded digital-to-analog converter including a first switch coupled to a first node that is coupled to a fourth switch and a first capacitor, a second switch coupled to a second node that is coupled to the first capacitor and a third switch, a negative input of a first operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor, and an output port of the first operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch.

Abstract: An apparatus includes a capacitor, a reference voltage, an input signal to be measured, and a frequency calculation circuit. The frequency calculation circuit is configured to select a capacitance value for the capacitor, charge the capacitor with the reference voltage, discharge the capacitor to a threshold voltage, and, based on a comparison of time to discharge the capacitor to the threshold voltage with a clock cycle of the input signal, determine a frequency of the input signal.

Abstract: The application provides a charge pump circuit, includes a digital control circuit, coupled to the switch module, configured to receive a up digital signal and a down digital signal, and adjust a first output voltage to a voltage level of an input voltage and adjust an second output voltage to a ground voltage level according to the up digital signal and the down digital signal; a digital-to-analog converter (DAC), configured to generate a corresponding up reference voltage and a corresponding down reference voltage according to the up digital signal and the down digital signal; and a voltage follower, comprising a plurality of operational amplifiers and a plurality of transistor switches, configured to lock the first output voltage and the second output voltage according to the up reference voltage and the down reference voltage; wherein the up digital signal and the down digital signal are varied with time.

Abstract: The application provides a charge pump circuit, including a switch module, including a plurality of switches and a soft ramp-up switch, configured to generate a first output voltage and a second output voltage according to an input voltage; and a digital control circuit, coupled to the switch module, configured to receive a up digital signal and a down digital signal, and adjust the first output voltage to a voltage level of the input voltage and adjust the second output voltage to a ground voltage level according to the up digital signal and the down digital signal. The charge pump circuit of application has advantages of minimizing inrush currents to avoid circumstances of distortions caused by the pop noises or clipping and optimizing the efficiency of the amplifier.

Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.

Abstract: A method is provided for controlling a sample and hold circuit that includes a switching module coupled to a storage capacitor. A circuit external to the sample and hold circuit of generates at least one main current representative of at least one leakage current of the switching module in its off state. The at least one main current is delivered to at least one auxiliary capacitor. An initial pulse signal is generated from the charging and discharging of the at least one auxiliary capacitor. The sampling phase of the sample and hold circuit is triggered at the rate of the pulses of a pulse signal derived from the initial pulse signal.

Abstract: Embodiments are directed to a system for sensing a data state of a selected memory cell. The system includes a first reference cell, a sample-and-hold sense amplifier and a switching system. During a first sensing phase the switching system is configured to open a first series communication path that places the selected memory cell in series with the first reference cell, thereby creating a first series voltage divider. During the first sensing phase, the switching system is further configured to open a first branch communication path that taps an input of the sample-and-hold sense amplifier into a first divided voltage between the selected memory cell and the first reference cell.

Abstract: A method for correcting the duty cycle of a clock signal uses two-dual-slope integrators with two comparators; each comparator is connected to both integrators and configured to include a “dead band” when the input pulse duty cycle is at or near 50%. One comparator detects when duty cycle is high and the other comparator detects when the duty cycle is low. When the duty cycle is within the “dead band” range, neither comparator goes valid. This provides an analog filter where the output comparators will not instantaneously switch between opposite duty cycle correction states. When the duty cycle is greater or less than 50%, the integrated voltages on the two integrators move in opposite directions producing twice the signal magnitude on differential inputs of the comparators, as compared with using a single integrator architecture.

Abstract: A high-speed sampling front-end circuit is presented that includes a MDAC sampling network, a reference voltage generator circuit, a comparator array, an operational amplifier, an output short-circuit switch, an adjustable clock duty cycle stabilizer, a status control module and a feedback control module. The circuit features low power, high sampling rate and high input bandwidth of sampling network. The time constant of the MDAC sampling network and the comparator array is precisely matched one another to improve input bandwidth of the sampling network. Sampling capacitors are designed as feedback capacitors and DAC calculation capacitors, thereby the operational amplifier doubles feedback coefficient and features 50% bandwidth and 50% power. The cycle stabilizer is adopted to shorten sampling time and extend amplification phase to greatly improve sampling rate. One input reference voltage tends to simplify the design of the reference voltage generator circuit.

Abstract: An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output s terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.

Abstract: A positive/negative sampling and holding (S/H) circuit is disclosed herein. The positive/negative S/H circuit includes an operational amplifier, a first capacitor, a second capacitor being parallel with the first capacitor and forming an integration circuit with the operational amplifier, and several discharge switches correspondingly connecting discharge paths of the first and the second capacitors to control the first and the second capacitors to output a first sampling signal and a second sampling signal respectively, and herein, the first and the second sampling signals has the same magnitude but opposite voltage polarities.

Abstract: A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (PWM), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit. The second die includes ultra-high voltage high-side drivers. In an ultra-high voltage application, the PWM and external circuitry together form a switching power supply that generates a high voltage. The high voltage powers external high-side transistors. The processor and timer control the ultra-high voltage high-side drivers, that in turn supply drive signals to the external high-side transistors through the package terminals. External low-side transistors are driven directly by low-side drivers of the first die. If the fault protection circuit detects an excessive current, then the fault protection circuit supplies a disable signal to high-side and low-side drivers of both dice.

Abstract: A sample and hold circuit may include: a main sample and hold circuit configured to sample and hold pixel information of an organic light emitting diode (OLED) cell, and output a first output signal; and a dummy sample and hold circuit configured to sample and hold a reference voltage in synchronization with the main sample and hold circuit, and output a second output signal for offsetting a switching noise signal contained in the first output signal.

Abstract: A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.

Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.

Abstract: An input circuit for an analog-to-digital converter (ADC) includes at least one bootstrap circuit, including at least one first switch for connecting electrical power to a first terminal of at least one capacitor; at least one second switch for connecting a second terminal of the at least one capacitor to a signal to be sampled; at least one third switch for connecting the first terminal of the at least one capacitor to the control gate of at least one sampling network input switch; at least one fourth switch for connecting the at least one sampling network input switch to a substrate; and at least one fifth switch for connecting the second terminal of the at least one capacitor to the substrate.

Abstract: An offset canceling circuit stores charge corresponding to a voltage difference between a reset voltage received from a unit pixel and a reference voltage, thereby canceling an offset of the unit pixel.

Abstract: A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.

Abstract: A peak hold circuit includes an input node configured to receive an input waveform, a peak hold component coupled to the input node and configured to sample and hold a peak value of the input waveform at a peak value node, a reset node configured to receive a reset signal, a reset circuit coupled to the peak hold component and the reset node, the reset circuit configured to reset the peak hold value, and a voltage clamp coupled to the input node, the reset circuit, and the reset node, the voltage clamp configured to clamp the input node in response to the reset signal.

Abstract: The invention relates to a low leakage switch having an input node for receiving an input voltage and an output node for providing an output voltage. The low leakage switch comprises a main sampling transistor the backgate voltage of which is biased through other transistors, and wherein the control gate of the main sampling transistor is controlled through a second control signal and the control gates of the other transistors are controlled through a first control signal, wherein the electronic device is further configured to activate the other transistor for adjusting the backgate voltage of the main sampling transistor through the first control signal before activating the main sampling transistor for sampling the input voltage on a main sampling capacitor through the second control signal.

Abstract: To suppress an adverse effect of change in held data in a sample-and-hold circuit as a result of increase in operation speed on a generated parallel data signal. A signal converter circuit includes a first sample-and-hold circuit and a second sample-and-hold circuit each of which has a function of extracting and holding part of a serial data signal as a data in accordance with a sampling control signal and has a function of generating a data signal which is one of data signals of a parallel data signal by using the held data and outputting the data signal. The second sample-and-hold circuit includes a switch which has a function of selecting whether the potential of the data of the second sample-and-hold circuit is set to a reference potential or not in accordance with the sampling control signal of the first sample-and-hold circuit.

Abstract: A packaged controller for closed-loop control applications includes two dice packaged together in a semiconductor package. The first die is optimized for digital circuitry and includes a processor, an ADC, a serial bus interface, and a sequencer. The second die is optimized for analog circuitry and includes a serial bus interface, a plurality of sample/hold circuits, and an analog multiplexer. The sequencer on the first die causes a series of multi-bit values to be communicated serially across a low latency serial bus to the second die, and thereby controls the analog multiplexer and the asserting of a sample/hold signal on the second die. Under control of the sequencer, multiple voltages are captured simultaneously on the second die, and then are multiplexed one by one to the ADC on the first die for conversion into digital values. The architecture reduces complexity and cost of the overall packaged controller.

Abstract: A method, an apparatus, and a computer program product embodiments are disclosed for detection of the availability of a battery (160) by a host terminal (100) during a data exchange session with the battery (160). In accordance with the embodiments of the invention, sampling, data communication with the battery pack (150), and detection of battery (160) removal, may occur substantially simultaneously. The battery (160) removal may be detected during data transmission from the terminal (100) to the battery pack (150). Moreover, a response may be received by the terminal (100) from the battery circuits (155) in response to data communicated to the battery (160) on the battery communication line (140), during sampling in a timed manner.

Abstract: As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

Abstract: A sample and hold circuit with leakage compensation is disclosed. An example sample and hold circuit includes a first switch coupled to sample and hold an input signal value in a first capacitor coupled to the first switch in response to a sample signal. A second switch through which a second leakage current flows to a second capacitor coupled to the second switch is also included. The second leakage current through the second switch to the second capacitor is substantially equal to a first leakage current through the first switch to the first capacitor. An offset circuit that is coupled to the first and second capacitors is also included to produce a compensated sampled value in response to a difference between a quantity representing the held input signal value and charge accumulated in the first capacitor in response to the first leakage current from a quantity representing charge accumulated in the second capacitor in response to the second leakage current.

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract: A sample hold circuit and a method for eliminating the offset voltage of the analog signal are provided. The sample hold circuit includes a sample unit, a plurality of capacitors, a control unit and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an analog signal. When the sample hold circuit is in a second state, the capacitors eliminate a DC offset voltage of the analog signal sampled by the sample unit, and the hold unit outputs an AC signal of the analog signal sampled by the sample unit. The control unit adjusts a number of the capacitances coupled to a common voltage according to a magnitude of the DC offset voltage, thus to determine the capacitance for eliminating the DC offset voltage.

Abstract: A semiconductor integrated circuit has a sampling circuit which samples a potential of an input terminal, a dynamic comparator having a standby and a comparison mode which compares the potential of the input terminal and a reference potential, a switch for input signals connected between the input terminal and the dynamic comparator, a capacitor for comparator having one end connected between the switch for input signals and the dynamic comparator and another end connected to a fixed potential, and a timing control circuit which controls a timing to sample by sampling circuit, a timing to switch modes of dynamic comparator, and a timing to make switch for input signals conducting or blocking state. The timing control circuit makes the switch for input signals blocking state from conducting state before the dynamic comparator switches from standby mode to comparison mode, and terminates sampling by sampling circuit after switching modes.

Abstract: A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.

Abstract: The serial interface operable, for example, to facilitate high speed differential data transfer between integrated circuits provides level shifting of an incoming data signal using a switched capacitor technique which level shifts the common mode voltage with minimal attenuation and minimal reduction of bandwidths. The serial interface also includes a DC offset correction loop of the input data receiver path. The level shifting circuit operates by sensing the incoming common mode voltage of a differential data signal with a resistor divider and sampling the difference between the measured input common mode voltage and desired input differential voltages generated by a differential DAC in the DC offset correction loop on two small capacitors.

Abstract: Methods and apparatus are disclosed to track and hold a voltage. An example track and hold circuit comprises a first electronic switch, a second electronic switch, and a current mode logic amplifier.

Abstract: A sample and hold circuit in one aspect includes first and second switches. The first switch can be coupled to receive an input signal and to sample the input signal using a first capacitor. A first leakage current flows between first and second conductive terminals of the first switch and accumulates as a first leakage charge in the first capacitor. A second leakage current flows between the first and second conductive terminals of the second switch and accumulates as a second leakage charge in the second capacitor. An offset circuit produces a compensated sampled value by subtracting a quantity from a signal developed in response to the held sampled signal and charge accumulated through the first switch, wherein the quantity is developed in response to the accumulated leakage charge in the second capacitor.

Abstract: A peak detector provides repeatable and accurate measurements of the signal amplitude for variable frequencies of input signals. The peak detector includes a pulse edge generator circuit that generates a pulse edge signal in response to the signal peaks of an input signal and a sampler circuit that is triggered to sample the input signal by the pulse edge signal. The pulse edge generator circuit compares the input signal with a delayed version of the input signal to produce a differential signal and generates the pulse edge signal using the differential signal. An analog or digital sampler is triggered by the pulsed edge signal to measure the information, e.g., peak value, of the input signal. One or more delay circuits may be used to align the edges of the pulsed edge signal with the peaks of the input signal.

Abstract: Switches with passive bootstrap that can achieve good sampling performance are described. In one design, a sampling circuit with passive bootstrap includes first and second filters and a switch. The first filter filters an input signal and provides a filtered input signal. The second filter filters a clock signal and provides a filtered clock signal. The switch receives a control signal formed based on the filtered input signal and the filtered clock signal and either passes or blocks the input signal based on the control signal. The first filter may be a lowpass filter having a first corner frequency that is higher than the bandwidth of the input signal. The second filter may be a highpass filter having a second corner frequency that is lower than the fundamental frequency of the clock signal. The first and second filters may both be implemented with one resistor and one capacitor.

Abstract: An apparatus having an input voltage and an output voltage is provided. The apparatus comprises a switch that receives the input voltage and that is adapted to be coupled to a load, a modulator having a timing signal, a compensator that is coupled to the modulator and that includes an amplifier, an overcurrent circuit, and a sampler. The modulator is coupled to the switch and the modulator actuates the switch at a first frequency. The amplifier amplifies the difference between at least a portion of the output voltage with a predetermined reference voltage and outputs an amplified voltage. The overcurrent circuit receives the amplified voltage and outputs an overcurrent signal to the modulator.

Abstract: A track and hold circuit is disclosed, including: a source follower coupled to a voltage supply; a MOS transistor with well structure, the MOS transistor having a gate terminal coupled to a gate terminal of the source follower, a drain terminal coupled to its body terminal and a source terminal of the source follower, and a source terminal coupled to a current source and an output terminal; a capacitive device having a terminal coupled to the gate terminal of the MOS transistor and another terminal coupled to a fixed voltage level; and a switch device coupled and disposed between an input signal and the gate terminal of the MOS transistor, wherein the switch device is controlled by a control signal.

Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal and a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal and the common signal.

Abstract: A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.

Abstract: A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

Abstract: A variable gain frequency multiplier comprises a multiplier circuit and a control circuit configured to receive a power control signal, the power control signal being proportional to a power output signal.

Abstract: A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.

Abstract: A sample hold circuit includes an op-amp, first capacitors provided on an inverting side of the op-amp and second capacitors provided on a non-inverting side. The sample hold circuit is configured such that a total capacitance of the first and second capacitors to which an input voltage is applied in a sampling phase is equal to that of the first and second capacitors to which the input voltage is applied in a holding phase, a total capacitance of the first capacitors to which the input voltage is applied in the holding phase is equal to that of the second capacitors to which the input voltage is applied in the holding phase, and a total capacitance of the first capacitors to which the input voltage is applied in the sampling phase is different from that of the second capacitors to which the input voltage is applied in the sampling phase.

Abstract: An electronic device, such as a sample-and-hold circuit, includes a field effect transistor (FET), a capacitor, and a voltage offset circuit. The FET is configured to receive a signal at a first terminal thereof and selectively provide the signal to a second terminal thereof responsive to a switching signal at a gate terminal thereof. The capacitor is electrically connected to the second terminal of the FET. The voltage offset circuit is electrically connected to the first terminal and the gate terminal of the FET. The voltage offset circuit is configured to maintain a substantially constant voltage differential between the first terminal and the gate terminal of the FET while the signal is provided to the second terminal of the FET and substantially independent of a voltage level of an input signal. Related methods of operation are also discussed.

Abstract: A circuit and method thereof for sampling/holding signal is provided. The signal sampling/holding circuit comprises a first signal sampling/holding device, a second signal sampling/holding device, a target signal and a reference voltage. First, the first signal sampling/holding device is supplied with the reference voltage and the target signal. The reference voltage is disconnected from the first signal sampling/holding device before the target signal is. Similarly, the reference voltage is disconnected from the second signal sampling/holding device before the target signal is. Thus the target signal is respectively sampled and held in the first signal sampling/holding device and the second signal sampling/holding device.

Abstract: A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

Abstract: An apparatus and method for generating an output signal that tracks the temperature coefficient of a light source are provided. A light source temperature coefficient tracking mechanism (e.g., a current source circuit) that generates an output signal, which tracks the temperature coefficient of the light source (e.g., temperature coefficient of a light emitting diode (LED)) is provided. A proportional to absolute temperature current source circuit (PTAT current source circuit) generates a first signal. A complimentary to absolute temperature current source circuit (CTAT current source circuit) generates a second signal. The output signal that tracks the temperature coefficient of the light source is based on the first signal and the second signal.

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract: A first bias voltage to be applied to a drain portion of a MOS transistor and a pulse voltage pulsating with a predetermined potential difference are being generated by an apparatus incorporating the MOS transistor. Voltage generation means generates a second bias voltage to be applied to a gate portion of the MOS transistor, based on a value of the predetermined potential difference of the pulse voltage generated in the apparatus incorporating the MOS transistor, a value of the first bias voltage generated in the apparatus incorporating the MOS transistor, and a channel potential of a channel portion provided beneath the gate portion of the MOS transistor. Superposition means generate a voltage to be applied to the gate portion of the MOS transistor by superposing the pulse voltage onto the second bias voltage generated by the voltage generation means.