Including Details Of Sampling Or Holding Patents (Class 327/91)
  • Patent number: 10560071
    Abstract: An embodiment attenuator includes a plurality of circuits coupled in series. A respective circuit includes a first capacitor connected between an input node of the respective circuit and an output node of the respective circuit, and a second capacitor connected between the output node of the respective circuit and a reference node. The output node of the respective circuit, other than a last circuit of the plurality of circuits, is connected to the input node of a successive circuit. The attenuator further includes a plurality of selectors, in which the respective circuit is associated with a respective selector that is coupled between the output node of the respective circuit and an output node of the attenuator.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: February 11, 2020
    Assignee: STMICROELECTRONICS SA
    Inventor: Renald Boulestin
  • Patent number: 10497455
    Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to receive an input signal. The first switch is further coupled to a first capacitor. The S/H circuit further includes a buffer coupled to the first switch. In addition, the S/H circuit includes a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 3, 2019
    Assignee: Silicon Laboratories Inc.
    Inventor: Mohamed M. Elsayed
  • Patent number: 10423180
    Abstract: Methods of powering a radio that is mounted on a tower of a cellular base station are provided in which a direct current (“DC”) power signal is provided to the radio over a power cable and a voltage level of the output of the power supply is adjusted so as to provide a substantially constant voltage at a first end of the power cable that is remote from the power supply. Related cellular base stations and programmable power supplies are also provided.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: September 24, 2019
    Assignee: CommScope Technologies LLC
    Inventors: John Charles Chamberlain, Michael R Guerin
  • Patent number: 10425071
    Abstract: The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 24, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Rahul Karmaker
  • Patent number: 10394265
    Abstract: Methods of powering a radio that is mounted on a tower of a cellular base station are provided in which a direct current (“DC”) power signal is provided to the radio over a power cable and a voltage level of the output of the power supply is adjusted so as to provide a substantially constant voltage at a first end of the power cable that is remote from the power supply. Related cellular base stations and programmable power supplies are also provided.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: August 27, 2019
    Assignee: CommScope Technologies LLC
    Inventors: John Chamberlain, Michael Guerin
  • Patent number: 10396582
    Abstract: A battery charging system includes a master charger that receives a supply voltage, outputs a master charging current based on the supply voltage, and selectively outputs a slave charger control signal. At least one slave charger receives the slave charger control signal from the master charger, receives the supply voltage, and selectively outputs a slave charging current based on the slave charger control signal and the supply voltage.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: August 27, 2019
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Guoying Yi, Rudy Kurniawan, Yayue Zhang, Sungil Ha, Haitao Hu, Guang Zhang, John Hu, Chin Boon Huam, Jia Hu
  • Patent number: 10379415
    Abstract: According to an aspect, a display apparatus includes: a display panel including a plurality of pixels each including a pixel capacitor and a pixel transistor, a scanning line that is coupled to the respective pixels and is configured to receive a scan signal, and a video signal line that is coupled to the respective pixels and is configured to receive a video signal; and a driver configured to drive the display panel. The pixel transistor includes: at least one N-channel metal oxide semiconductor (NMOS) transistor coupled between the video signal line and the pixel capacitor; and a P-channel metal oxide semiconductor (PMOS) transistor coupled in parallel with the NMOS transistor.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 13, 2019
    Assignee: Japan Display Inc.
    Inventor: Tadayoshi Katsuta
  • Patent number: 10379557
    Abstract: Methods of powering a radio that is mounted on a tower of a cellular base station are provided in which a direct current (“DC”) power signal is provided to the radio over a power cable and a voltage level of the output of the power supply is adjusted so as to provide a substantially constant voltage at a first end of the power cable that is remote from the power supply. Related cellular base stations and programmable power supplies are also provided.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: August 13, 2019
    Assignee: CommScope Technologies LLC
    Inventors: John Charles Chamberlain, Michael R Guerin
  • Patent number: 10378946
    Abstract: In some examples, a method of sensing an ink level includes applying a pre-charge voltage to a sense capacitor to charge the sense capacitor with a charge, sharing the charge between the sense capacitor and a reference capacitor, causing a reference voltage at a gate of an evaluation transistor, and determining a resistance from a drain to a source of the evaluation transistor that results from the reference voltage.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: August 13, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Trudy Benjamin, Teck-Khim Neo, Joseph M. Torgerson, Neel Banerjee, George H. Corrigan, III
  • Patent number: 10353418
    Abstract: Methods of powering a radio that is mounted on a tower of a cellular base station are provided in which a direct current (“DC”) power signal is provided to the radio over a power cable and a voltage level of the output of the power supply is adjusted so as to provide a substantially constant voltage at a first end of the power cable that is remote from the power supply. Related cellular base stations and programmable power supplies are also provided.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: July 16, 2019
    Assignee: CommScope Technologies LLC
    Inventors: John Chamberlain, Michael Guerin
  • Patent number: 10348250
    Abstract: The noise power of an amplifier or buffer can increase towards the unity gain crossover frequency of the amplifier. The inventor realized that many applications do not require the full bandwidth capability of the amplifier all of the time and hence step could be taken to reduce the bandwidth at the output of the amplifier and hence the noise power can be reduced when appropriate, taking other operating requirements into consideration.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: July 9, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventor: Dennis A. Dempsey
  • Patent number: 10270630
    Abstract: A receiver system for an on-off key (“OOK”) isolator system may include a receiver that generates an intermediate current signal based on an OOK input signal. The intermediate current may be provided at a first current level when the input signal has a first OOK state and a second current level when the input signal has a second OOK state. The system also may include an output driver to generate a voltage representation of the intermediate current signal. Performing signal processing in a current domain permits fast transitions between OOK states.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: April 23, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Ruida Yun, Eric C. Gaalaas, Baoxing Chen
  • Patent number: 10260767
    Abstract: An environmental control device (100), such as a thermostat, is disclosed. The environmental control device (100) has one or more terminals (222, 222a-222d) and a respective configurable interface circuit (102, 102a-102d, 300) coupled to each terminal for selectively configuring the terminal (222, 222a-222d) for a corresponding input or output connection to an HVAC system (14).
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: April 16, 2019
    Assignee: Siemens Schweiz AG
    Inventors: Michael S. Schuler, Pei Jin Li, Zhan Jun Ding, William J. Fenske
  • Patent number: 10216972
    Abstract: Embodiments herein describe an input device that includes a rectangular array of sensor electrodes connected to sensor modules that measure capacitive sensing signals corresponding to the electrodes. During a charge stage, the input device applies a charging voltage to neighboring sensor electrodes in the array. The input device then drives the neighboring sensor electrodes to a reference voltage and measures the amount of charge accumulated on at least one of the sensor electrodes. Because of the parasitic capacitance between the neighboring electrodes, driving these electrodes (even the ones not being measured) to the same charging and reference voltages reduces the effect of the parasitic capacitance on the capacitive sensing measurement. Thus, during the read stage, the measured charge is affected primarily by the capacitance between the sensor electrodes and an input object (e.g., a finger).
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: February 26, 2019
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Arash Akhavan Fomani, Kirk Hargreaves, Patrick Smith
  • Patent number: 10177581
    Abstract: A semiconductor device includes a serial resistance element section including plural resistance elements connected in series, each resistance element provided so as to correspond to one of a plural battery cells connected in series; a comparison section that compares a voltage of a connection point of the plural battery cells connected in series to a voltage of a connection point between the resistance elements that correspond to the battery cells; and a measurement section that measures a voltage of one of the plural battery cells.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 8, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masato Yamazaki
  • Patent number: 10145734
    Abstract: Various embodiments of the present technology may comprise methods and apparatus for a light sensor with a precharge circuit, such as for charging an internal node of a sensor to a starting voltage equal to an ending voltage of a different sensor. The methods and apparatus may comprise sequentially reading out the voltages of photosensitive elements and selectively activating the precharge circuit of one sensor during readout of the last photosensitive element of a different sensor.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: December 4, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael A. Wu
  • Patent number: 10115475
    Abstract: A compensation circuit for compensating for an input charge at a first input of a sample and hold circuit, comprising: a first buffer, a first compensation capacitor comprising a first compensation terminal switchable between a first buffer input and a first buffer output, and a second compensation terminal switchable between the first buffer output and a reference terminal, and a control circuit to switch the first compensation terminal to the first buffer1 output and the second compensation terminal to the reference terminal during sampling, for storing a compensation charge into the first compensation capacitor, and to switch the first compensation terminal to the first buffer input and the second compensation terminal to the first buffer output during holding, for discharging the first compensation capacitor into the first input. The compensation charge is substantially equal to the input charge.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: October 30, 2018
    Assignee: NXP USA, Inc.
    Inventors: Yuan Gao, Jerome Jean Pierre Luc Casters, Stephane Laurant Michel Ollitrault
  • Patent number: 10102693
    Abstract: A system for performing predictive analysis and diagnostics is disclosed. The system includes a plurality of sensors communicatively coupled to a vehicle electronics unit. The plurality of sensors are configured to generate at least one first signal indicative of a first sensed condition and at least one second signal indicative of a second sensed condition. A remote central processing system is coupled to the vehicle electronics unit. The remote central processing system comprises a remote processor and a remote data storage device, wherein the remote central processing system is configured to receive each of the at least one first and second signals.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: October 16, 2018
    Assignee: DEERE & COMPANY
    Inventor: Yifu Wu
  • Patent number: 10072458
    Abstract: A method of operating a motorized window covering is presented wherein in response to a standard movement command power is supplied to a motor in a continuous or generally continuous manner thereby moving the shade material from a start position to an end position in a generally continuous manner. However, in doing so, the motor rotates at a fast rate thereby causing elevated noise levels. In response to an automated movement command, power is supplied to the motor by cycling power to the motor between a powered state and an unpowered state thereby moving the shade material from a start position to an end position in an incremental manner. While moving the shade material in this incremental manner is slower, it is substantially quieter. The preferred mode of operation is selected based on whether the movement command is a standard movement command or an automated movement command.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: September 11, 2018
    Assignee: CURRENT PRODUCTS CORP
    Inventors: Willis Jay Mullet, Daniel T. Matthews, Richard Scott Hand
  • Patent number: 10026497
    Abstract: A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: July 17, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni, Zvika Lupu
  • Patent number: 9787928
    Abstract: Ping-pong readout architecture allows for faster frame rates in CMOS image sensors. However, various problems are created by this architecture due to cross-talk between components. Provided herein are novel ping-pong readout layouts which better isolate components to reduce crosstalk issues. Also provided herein are novel timing schemes for operating ping-pong readout circuits which prevent crosstalk signal spikes or readout corruption.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: October 10, 2017
    Assignee: Forza Silicon Corporation
    Inventors: Dexue Zhang, Yingying Wang, Loc Truong, Steven Huang
  • Patent number: 9728271
    Abstract: A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: August 8, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Golan Zeituni, Zvika Lupu
  • Patent number: 9720072
    Abstract: A method is provided that includes a vehicle receiving data from an external computing device indicative of at least one other vehicle in an environment of the vehicle. The vehicle may include a sensor configured to detect the environment of the vehicle. The at least one other vehicle may include at least one sensor. The method also includes determining a likelihood of interference between the at least one sensor of the at least one other vehicle the sensor of the vehicle. The method also includes initiating an adjustment of the sensor to reduce the likelihood of interference between the sensor of the vehicle and the at least one sensor of the at least one other vehicle responsive to the determination.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: August 1, 2017
    Assignee: Waymo LLC
    Inventors: Edward Daniel McCloskey, Russell Leigh Smith
  • Patent number: 9715941
    Abstract: A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transistor, and a resistive element and a second switch connected in parallel between a drain electrode of the first transistor and a predetermined voltage. The resistive element may include a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor, or may include multiple transistor banks connected in parallel, each including a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor. The gate control signal may originate from a circuit including a state machine.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 25, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Amit Sokolover, Golan Zeituni
  • Patent number: 9678166
    Abstract: A first part circuit and an operational amplifier form a level shift circuit, which selects either one of battery cells forming an assembled battery and extracts and holds a voltage representing an inter-terminal voltage of a selected battery cell. A second part circuit and the operational amplifier form a residual voltage generation circuit, which generates a residual voltage by amplifying a differential voltage between a conversion subject voltage and an analog voltage corresponding to a conversion result of an A/D conversion circuit and applies the residual voltage to the A/D conversion circuit as a conversion subject voltage. A switchover circuit operates the operational amplifier as either one of the level shift circuit and the residual voltage generation circuit and switches over a connection-state to apply a voltage held by the level shift circuit to the A/D conversion circuit and the residual voltage generation circuit as a conversion subject voltage.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: June 13, 2017
    Assignee: DENSO CORPORATION
    Inventors: Kazutaka Honda, Tetsuya Makihara, Shogo Hikosaka
  • Patent number: 9654095
    Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: May 16, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Michel Cuenca
  • Patent number: 9628737
    Abstract: Provided is a solid-state imaging device in which a first substrate and a second substrate having circuit elements, which constitute pixels, arranged thereon are electrically connected to each other. Each pixel includes: a photoelectric conversion unit disposed on the first substrate that outputs a signal based on incident light; a sampling transistor disposed on the second substrate that includes a gate terminal, a source terminal, and a drain terminal, that samples and holds the signal input from the photoelectric conversion unit to a first terminal, and outputs the sampled and held signal from a second terminal; a capacitor disposed on the second substrate that stores the signal output from the second terminal; and a potential fixing circuit that fixes a potential of the first terminal to a potential based on a predetermined fixed potential during a readout period in which the signal stored in the capacitor is read out.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: April 18, 2017
    Assignee: OLYMPUS CORPORATION
    Inventor: Hideki Kato
  • Patent number: 9599500
    Abstract: In an embodiment, a method of sensing an ink level includes applying a pre-charge voltage Vp to a sense capacitor to charge the sense capacitor with a charge Q1, sharing Q1 between the sense capacitor and a reference capacitor, causing a reference voltage Vg at the gate of an evaluation transistor, and determining a resistance from drain to source of the evaluation transistor that results from Vg.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: March 21, 2017
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Trudy Benjamin, Teck-Khim Neo, Joseph M. Torgerson, Neel Banerjee, George H. Corrigan, III
  • Patent number: 9559835
    Abstract: A signal receiver may comprise circuitry for applying multi-level sampling to an input signal, using a plurality of sampling rates that comprises at least two different sampling rates, and circuitry for processing one or more outputs of the multi-level sampling. The processing may comprises sampling at a sampling rate that is different than each of the plurality of sampling rates used during the multi-level sampling and applying analog-to-digital conversion. At least one of the sampling rates used during the multi-level sampling and/or the sampling rate used during the processing may be set based on configuring of one or more clock signals used during the multi-level sampling and/or during the processing. At least one of the one or more clock signals may be configured based on reduction of frequency of a corresponding base clock signal.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: January 31, 2017
    Assignee: MAXLINEAR, INC.
    Inventors: Jianyu Zhu, Sheng-Yu Peng, Rodney Chandler, Pawan Tiwari, Rahul Bhatia, Eric Fogleman
  • Patent number: 9413228
    Abstract: A switched capacitor circuit includes a threshold detector to generate a threshold detection signal when a difference between first and second input signals crosses a predetermined level. A variable current source produces a varying amount of current in response to the difference between the input signals. A voltage measurement means produce a measurement signal in response to the difference between the input signals. A correction means produces a correction signal in response to the measurement signal to produce an optimum coarse phase overshoot. A timing comparison means produces a timing signal in response to the difference between the input signals. A correction means produces a correction signal in response to the timing signal to produce an optimum coarse phase overshoot.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: August 9, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Matthew Z. Straayer, Hae-Seung Lee, Kush Gulati, Carlos E. Munoz
  • Patent number: 9384819
    Abstract: Disclosed herein is a device including a timing control circuit that receives a strobe signal supplied from outside to generate an internal strobe signal that is used as a timing signal to latch a data signal. An operation state of the timing control circuit is changed according to temperature change so as to keep an output timing of the internal strobe signal with respect to an input timing of the strobe signal.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: July 5, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Yasuhiro Takai
  • Patent number: 9351089
    Abstract: Techniques are described for recognizing an audio double tap or other tapped audio sequences generated by a user. Amplitudes of an audio signal are processed to generate an energy function or curve. The energy curve is analyzed to detect audio pulses. Detected pulses are validated and double tap events are detected based on features such as duration, power, and/or symmetry, plus additional rules related to the structure of the audio event.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: May 24, 2016
    Assignee: Amazon Technologies, Inc.
    Inventor: Wai C. Chu
  • Patent number: 9231539
    Abstract: An amplifier, comprising: an input node; an output node; a gain stage having a gain stage inverting input, a gain stage non-inverting input and a gain stage output; a feedback capacitor connected in a signal path between the gain stage output and the gain stage inverting input; a sampling capacitor connected between the input node and the gain stage inverting input, and a controllable impedance in parallel with the feedback capacitor, wherein the controllable impedance is operable to switch between a first impedance state in which it does not affect current flow through the feedback capacitor, and a second impedance state in which it cooperates with the feedback capacitor form a bandwidth limiting circuit.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 5, 2016
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Colin G. Lyden, Christopher Peter Hurrell, Derek Hummerston
  • Patent number: 9208591
    Abstract: One embodiment of the invention comprises a method for constructing a graph pertaining to a specified metric. Measured values of the specified metric are selectively stored, wherein each stored value comprises a data point. The method further includes routing successive data points to a location associated with the graph, wherein a first number of data points are included in a specified graph time period. The method further includes using a value that represents a particular data level of detail to divide the specified graph time period into multiple time intervals, wherein each time interval includes a second number of data points. The method further includes selectively processing the second number of data points of a time interval, in accordance with prespecified criteria, to determine a most representative value for that time interval. The most representative values of respective time intervals are then used to construct the graph.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Claus Huempel, Pamela A. Nesbitt, Jake Palmer
  • Patent number: 9147497
    Abstract: Aspects of the disclosure provide a sampling circuit with reduced sampling distortions. The sampling circuit can include a switch and a first driving module configured to drive a first signal in response to an input signal onto a first channel terminal of the switch. The sampling circuit also can include a bootstrap module coupled to a control terminal of the switch and a second driving module coupled to the bootstrap module. The second driving module can be configured to drive a second signal in response to the input signal to the bootstrap module, such that the bootstrap module can vary a control voltage on the control terminal based on the input signal for turning on the switch and causing an output voltage on a second channel terminal of the switch to track the first signal on the first channel terminal of the switch.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: September 29, 2015
    Assignee: Marvell International Ltd.
    Inventor: Kenneth Thet Zin Oo
  • Patent number: 9106208
    Abstract: A band-pass filter made up by an operational amplifier and by an input circuit. The input circuit is formed by a capacitive filtering element, connected to the input of the operational amplifier; a coupling switch, coupled between an input node and the capacitive filtering element; a capacitive sampling element, coupled between the input of the filter and the input node; and a sampling switch, coupled between the input node and a reference-potential line. The coupling switch and the input sampling switch close in phase opposition according to a succession of undesired components sampling and sensing steps, so that the capacitive sampling element forms a sampler for sampling the undesired component in the undesired components sampling step, in the absence of the component of interest, and forms a subtractor of the undesired components from the input signal in the sensing step.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: August 11, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Andrea Visconti, Luciano Prandi, Carlo Caminada, Paolo Angelini
  • Patent number: 9106210
    Abstract: In one example embodiment, a programmable capacitor array is provided for low distortion and minimizing linearity degradation of an input (Vin) by utilizing control circuitry to switch on and off an array of MOSFET switches. The control circuitry turns on a MOSFET to load a capacitance on Vin and turns off the MOSFET to remove the capacitance from Vin in response to a Din control signal. When the intention is to load Vin with the capacitance, the MOSFET is left on continuously. When the intention is to remove or unload the capacitance from Vin, the MOSFET is primarily turned off, however, the MOSFET is still periodically turned on with appropriate voltage levels in response to a clock signal for periods of time when the loading of the capacitance on Vin is tolerable to the system, thereby ensuring minimal linearity degradation of Vin due to the programmable capacitor array system.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: August 11, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Siddharth Devarajan, Lawrence A. Singer
  • Patent number: 9093998
    Abstract: An apparatus and method for generating a ramp signal includes applying a constant reference voltage to a reference capacitor and controlling charging or discharging of the reference capacitor with a programmable current generator to provide the ramp signal at a ramp signal node. The method can include, buffering the ramp signal to an output node to drive a load. When generating the ramp signal having a negative slope, the programmable current generator includes a programmable current sink coupled to the ramp signal node. When generating the ramp signal having a positive slope, the programmable current generator includes a programmable current source that is coupled between a positive power supply node and the ramp signal node. When generating the ramp signal having a bidirectional slope, the programmable current generator includes a programmable current source and a programmable current sink.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Martin Kinyua, Eric Soenen
  • Patent number: 9007283
    Abstract: A pixel and display having the pixel are disclosed. The pixel includes transistors along a leakage path from a storage capacitor. The pixel also includes transistors to apply a reference voltage to the leakage path to minimize leakage.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: April 14, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Deok-Young Choi
  • Patent number: 9000702
    Abstract: A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (PWM), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit. The second die includes ultra-high voltage high-side drivers. In an ultra-high voltage application, the PWM and external circuitry together form a switching power supply that generates a high voltage. The high voltage powers external high-side transistors. The processor and timer control the ultra-high voltage high-side drivers, that in turn supply drive signals to the external high-side transistors through the package terminals. External low-side transistors are driven directly by low-side drivers of the first die. If the fault protection circuit detects an excessive current, then the fault protection circuit supplies a disable signal to high-side and low-side drivers of both dice.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: April 7, 2015
    Assignee: Active-Semi, Inc.
    Inventors: Steven Huynh, Tsing Hsu
  • Patent number: 9000809
    Abstract: In accordance with various embodiments, a method for sampling an input signal may be provided, wherein the method may include providing a single frequency clock signal; selecting clock pulses from the single frequency clock signal in a random manner to generate a spread spectrum clock signal; and sampling the input signal using the spread spectrum clock signal. A corresponding device for sampling an input signal may be provided.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Peter Bogner, Marco Faricelli
  • Patent number: 8952729
    Abstract: A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: February 10, 2015
    Assignee: BAE Systems Imaging Solutions Inc.
    Inventors: Boyd Fowler, Peter Bartkovjak
  • Patent number: 8941414
    Abstract: A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Marco Corsi, Robert F. Payne
  • Publication number: 20150002326
    Abstract: An analog-to-digital converter (“ADC”) is disclosed. The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: Brendan Farley, James Hudner, Ivan Bogue, Declan Carey, Darragh Walsh, Marc Erett
  • Patent number: 8912838
    Abstract: A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: December 16, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Hae-Seung Lee
  • Patent number: 8907703
    Abstract: Methods and systems for sampling a differential signal. The sampling circuit includes a differential input and a differential output. A logic control block, which is powered by VDD and VSS sources, controls the state of switches used to sample and store differential signals. The logic control block is AC coupled to the switches. The sampling circuit is configured to sample a common mode voltage at the differential input of a level that exceeds that of the VDD and VSS sources.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 9, 2014
    Assignee: Linear Technology Corporation
    Inventor: Gerd Trampitsch
  • Patent number: 8901993
    Abstract: A system and method receive the output signal from a capacitance diaphragm gauge (CDG) and generate a noise reduced output signal. An input signal processing circuit receives an input signal from a signal source that drives the CDG. The input signal processing circuit generates a segment of N normalized digital samples of the input signal. An output signal processing circuit receives the output signal from the CDG and generates M segments of N digital samples of the CDG output signal and averages the corresponding samples in the M segments to generate a signal segment of N averaged samples. Each of the N averaged samples is multiplied by a corresponding one of the N normalized samples to generate N products. The N products are averaged to generate an average product, which is multiplied by a constant to generate a system output signal with reduced noise.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: December 2, 2014
    Assignee: Reno Sub-Systems Canada Incorporated
    Inventor: Robert J. Ferran
  • Patent number: 8896350
    Abstract: A sampling circuit and a sampling method are provided, where the sampling circuit includes a first delay chain, a second delay chain, and a half-speed binary-phase detector. The first delay chain is used to delay an input signal according to an up signal and a down signal, so as to generate a first delay signal; and the second delay chain is used to delay the first delay signal according to a preset delay value, so as to generate a second delay signal. The half-speed binary-phase detector is used to sample a data signal according to edge trigger of the first delay signal and that of the second delay signal, and generate an output signal, an up signal, and a down signal according to a sampling result of the data signal.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: November 25, 2014
    Assignee: Reatek Semiconductor Corp.
    Inventors: Ching-Sheng Cheng, Hsu-Jung Tung
  • Patent number: 8890733
    Abstract: A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: November 18, 2014
    Assignees: IMEC, Renesas Electronics Corporation
    Inventors: Takaya Yamamoto, Jan Craninckx
  • Patent number: 8872574
    Abstract: An interpolation circuit includes: a first node to receive a first current; a second node to receive a second current; a third node to receive a third current; a first capacitor circuit including: first capacitors; a first switch to couple one end of each of first capacitors to one of first and second nodes; and a first output coupled to the other end of each of first capacitors; a second capacitor circuit including: second capacitors; a second switch to couple one end of each of second capacitors to one of second and third nodes; and a second output node coupled to the other end of each of second capacitors; and a third capacitor circuit including: a third capacitor whose one end is coupled to the second node; and a third switch to couple the other end of the third capacitor to one of first and second output nodes.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Limited
    Inventor: Yoshiyasu Doi