Abstract: The present disclosure relates to a field-effect transistor (FET) controlling apparatus and method for accurately, controlling an operation state of a FET by adaptively adjusting a voltage applied to the FET to correspond to a voltage of a source terminal of the FET. The voltage applied to the gate terminal of the FET may be adaptively controlled according to the voltage of the source terminal using a capacitor. Therefore, even when the source terminal is not connected to the ground but connected to an external load, there is an advantage that the operation state of the FET may be smoothly and accurately controlled. In addition, there is an advantage that a voltage within a certain range may be applied to the gate terminal of the FET.

Abstract: A pulse detection circuit configured to detect peak pulse values from pulses contained in an input analog signal includes a control circuit to generate a peak control signal based on input from a microcontroller and/or a peak detector, and a peak track/hold circuit to produce an output peak analog signal responsive to the input analog signal and peak control signal. The peak track/hold circuit includes a peak-detect operational amplifier having first and second input terminals to receive the input analog signal and the peak control signal respectively, and a peak-hold capacitor connected to an output terminal of the operational amplifier. The pulse detection circuit includes an analog to digital converter to produce an output peak digital signal from the output peak analog signal. The peak track/hold circuit switches from a tracking mode to a hold mode upon the arrival of the peak control signal generated from the control circuit.

Abstract: A capacitance measurement circuit for determining complex electric currents in a multi-channel capacitive sensing device includes a first sensing circuit for selectively connecting one of a plurality of sense electrodes to a common sense node and for connecting a corresponding guard electrode of the sense electrode to a common guard node, and at least a second sensing circuit. A measurement signal voltage source provides an alternating measurement voltage to the common guard node in a remotely controllable manner. A diagnostic signal voltage source provides an alternating diagnostic voltage to the common guard node in a remotely controllable manner. A current measurement circuit is connected with a signal input port to the common sense node and with a reference input port to the output port of the measurement signal voltage source.

Abstract: An electronic device may include wireless circuitry having analog-to-digital converter (ADC) circuitry. The ADC circuitry may include a sampling switch coupled to a bootstrap circuit. The bootstrap circuit may include a bootstrap capacitor, a first transistor coupled between an input of the sampling switch and a bottom plate terminal of the bootstrap capacitor, a second transistor coupled between the bottom plate terminal of the bootstrap capacitor and ground, and a resistor or transistor that is disposed between the first transistor and the bottom plate terminal of the bootstrap capacitor and that is configured to boost the input impedance of the bootstrap circuit.

Abstract: A clock generating device includes a first voltage output circuit configured to output a first voltage corresponding to a power supply voltage in response to a preliminary clock signal, a clock output circuit configured to generate the preliminary clock signal and a final clock signal at a period corresponding to a difference between the first voltage and a negative feedback voltage, a negative feedback voltage generating circuit configured to generate the negative feedback voltage from a reference value corresponding to a frequency of the final clock signal and a second voltage and filtered to a uniform voltage level, and a second voltage output circuit configured to output the second voltage to the negative feedback voltage generating unit, the second voltage having lower sensitivity of fluctuations in the power supply voltage than the first voltage.

Abstract: A multiplexer includes a charging circuit; a plurality of sampling switches receiving a plurality of input signals; and a plurality of boosting circuits connected between the sampling switches and the charging circuit and sharing the charging circuit. First and second charging switches of the charging circuit are controlled by a first clock signal. Each of the boosting circuits includes a first boosting switch connected to a first node of the charging circuit and a gate of one of the sampling switches, a second boosting switch connected between a second node of the charging circuit and the one sampling switch, and a level shifter configured to control the first boosting switch and the second boosting switch in response to a second clock signal and a selection signal.

Abstract: The disclosed embodiments are directed toward improved control circuitry for artificial intelligence processors. In one embodiment, a device is disclosed comprising a processing element, the processing element including a processing device configured to receive a first set of vectors; a hijack control circuit, the hijack control circuit configured to replace the first set of vectors with a second set of vectors in response to detecting that the processing element is idle; and a processing element control circuit (PECC), the PECC storing a set of values representing the second set of vectors, the set of values retrieved from a remote data source.

Abstract: Example embodiments include an apparatus with a buffer amplifier having an output node. A first switchable unidirectional current path is provided between the output node and a capacitor, the first path allowing current flow from the capacitor to the output node. A second switchable unidirectional current path is provided between the output node and the capacitor, the second path allowing current flow from the output node to the capacitor. Comparator circuitry is provided that operates to open the first path if the capacitor voltage is above an upper threshold and to open the second path if the capacitor voltage is below a lower threshold. The capacitor voltage may be read by an analog-to-digital converter.

Abstract: A single-ended to differential converter includes a converter input, a first converter output, a second converter output, and an internal node, wherein the first converter output and the second converter output comprise a differential output; a non-inverting amplifier having an input coupled to the converter input, and an output coupled to the first converter output; an inverting amplifier having an input coupled to the first converter output, and an output coupled to the second converter output; a charge pump having a charge pump output capacitor coupled between the second converter output and the internal node; and a feedback capacitor coupled between the first converter output and the internal node.

Abstract: Circuitry generates base-to-emitter voltages (Vbe1, Vbe2) of two BJTs biased at different current densities, a base-to-emitter voltage (Vbe) of a BJT biased so Vbe is complementary to absolute temperature and has a curved non-linearity across temperature, and base-to-emitter voltages (Vbe1_c, Vbe2_c) of two BJTs biased by a temperature independent constant current and a current proportional to absolute temperature so Vbe2_c?Vbe1_c has the same but opposite curved non-linearity across temperature as Vbe. A sampling circuit samples these voltages and provides them to inputs of a loop filter. Filter outputs are quantized to produce a bitstream.

Abstract: The disclosure discloses an electro-hydraulic servo actuator capable of implementing long-stroke and high-frequency loading and a control method. The actuator includes: a long hydraulic cylinder with a piston, a short hydraulic cylinder with a piston, a fixed-end rod, low frequency and high frequency electro-hydraulic servo valves, a left rod chamber, a right rod chamber, a force applying end head, and a force applying end rod. With this structure, the displacement of the piston of the short hydraulic cylinder is a combination of small-displacement and high-frequency movement and large-displacement and low-frequency movement, so as to realize the generation of large-displacement and high-frequency movement. Therefore, a target large-displacement and high-frequency excitation is applied to the specimen under load test. The actuator can output high-frequency and large-displacement target excitation of 0.

Abstract: The invention provides a voltage doubler switched capacitor circuit capable of detecting short circuit of flying capacitor and a detection method thereof. The voltage doubler switched capacitor circuit provides a way to connect the flying capacitor in parallel to the charging path, and calculate whether it is charged to a predetermined voltage in the designed charging time interval, and then it can effectively detect whether the flying capacitor is short-circuited.

Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.

Abstract: A track-and-hold circuit includes: a transistor, in which a base is connected to a signal input terminal, a power supply voltage is applied to a collector, and an emitter is connected to a first signal output terminal; a transistor in which a base is connected to the signal input terminal, the power supply voltage is applied to a collector, and an emitter is connected to a second signal output terminal; capacitors; a constant current source; and a switch circuit alternately turning the transistors to an ON state in response to differential clock signals.

Abstract: Bias adjusting circuits (1_(2k-1), 1_2k) (where k is an integer equal to or greater than 1 and equal to or less than N, and N is an integer equal to or more than 2) adjust DC bias voltage of at least one of clock signals such that a duty ratio, which is a ratio between a period in which a clock signal is High as to a clock signal and a period in which the clock signal is Low thereasto, becomes (2N?2k+1):(2k?1). Sampling circuits switch between a track mode in which an output signal tracks an input signal, and a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with clock signals output from the bias adjusting circuits (2_1 to 2_2N).

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a current sensing circuit includes first and second integrated resistors on a semiconductor die, a controllable current source configured to provide a reference current, and a current determination circuit. A resistance value of the second integrated resistor is a factor n larger than a resistance value of the first integrated resistor. A current drawn by a target circuit is configured to flow through the first integrated resistor, and the reference current is configured to flow through the second integrated resistor. The current determination circuit is configured to determine a value of the current drawn by the target circuit based on the value of the reference current when a first voltage at a terminal of the first integrated resistor is approximately equal to a second voltage at a terminal of the second integrated resistor.

Abstract: Infrastructure equipment for transmitting data to and receiving data from a mobile device on a communications network is described. The infrastructure equipment comprising: transmitter circuitry configured to transmit the data to the mobile device; and controller circuitry configured to control the transmitter circuitry to transmit a first position reference signal in a first subframe and a second position reference signal in a second subframe, wherein the second position reference signal is a time adjusted version of the first position reference signal, the amount of time adjustment being determined by the sample time at which the mobile device samples the position reference signal.

Abstract: An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.

Abstract: A method and circuit for performing vector-matrix multiplication may include converting an input vector of binary-encoded values into analog signals using one-bit DACs, and sequentially performing a vector-matrix multiplication operation for each bit-order. The method may also include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the multiplier to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector-matrix multiplication.

Abstract: A regulator system includes a multi-bit detector system and a multi-cell charge/discharge circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of detectors has a predetermined threshold voltage. The multi-cell charge/discharge circuit includes a plurality of charge pumps. Each of the charge pumps is configured to generate a predetermined charge. Each of the charge pumps is associated with a predetermined threshold voltage of the detector circuit.

Abstract: A flyback converter communication channel is provided that comprises a pair of capacitors. A transmitter on a first side of a transformer for the flyback converter transmits a transmitter signal over a first one of the capacitors. The transmitter also transmits a complement of the transmitter signal over a second one of the capacitors. A receiver on a second side of the transformer controls a switch transistor responsive to a high-pass-filtered difference of the received signals from the pair of capacitors.

Abstract: Techniques and apparatus for supplying power to gate drivers of a switched-mode power supply (SMPS) circuit. One example power supply circuit generally includes a SMPS circuit having a first input voltage node and a second input voltage node, and a charge pump. The charge pump generally includes a first capacitive element having a first terminal and a second terminal; a first switch coupled between a first input node of the charge pump and the first terminal of the first capacitive element; a second switch coupled between the second terminal of the first capacitive element and a second input node of the charge pump; a third switch coupled between the first terminal of the first capacitive element and the first input voltage node of the SMPS circuit; and a fourth switch coupled between the second terminal of the first capacitive element and the second input voltage node of the SMPS circuit.

Abstract: In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

Abstract: A wireless charging system, a wireless charging method, and a device to-be-charged are provided. The wireless charging system includes a wireless charging device and a device to-be-charged. The wireless charging device is configured to conduct wireless communication with the device to-be-charged through communication control circuits to adjust a transmission power of the wireless charging device. In addition, the device to-be-charged has a step-down circuit.

Abstract: A switch device for switching an analog electrical input signal includes: a switching transistor being a flipped-well-silicon-on-insulator-NMOS transistor; and a bootstrapping arrangement including a voltage providing arrangement for providing a floating voltage during the on-state, wherein the floating voltage is provided at a positive terminal and at a negative terminal of the voltage providing arrangement; wherein the bootstrapping arrangement is configured in such way that during the on-state the positive terminal is electrically connected to the front gate contact of the switching transistor and to the back gate contact of the switching transistor, and the negative terminal is electrically connected to the source contact of the switching transistor; wherein the bootstrapping arrangement is configured in such way that during the off-state the positive terminal and the negative terminal are not electrically connected to the switching transistor.

Abstract: A method and apparatus for estimating a characteristic of a wind turbine electrical signal comprises buffering a sequence of sample values of the wind turbine electrical signal and a sequence of sample times corresponding with the sequence of sample values. The time periods represented by the sample times are variable. A sub-sequence of the buffered sample values to integrate is determined, based at least in part on a sum of the time periods. The characteristic is estimated by integrating the sample values in the sub-sequence.

Abstract: An electronic device including a semiconductor device capable of intermittent driving is provided. The electronic device includes a semiconductor device, and the semiconductor device includes a current mirror circuit, a bias circuit, and first to third transistors. The current mirror circuit includes a first output terminal and a second output terminal, and the current mirror circuit is electrically connected to a power supply line through the first transistor. The current mirror circuit has a function of outputting current corresponding to a potential of the first output terminal from the first output terminal and the second output terminal. The bias circuit includes a current source circuit and a current sink circuit, the current source circuit is electrically connected to the second output terminal through the second transistor, and the current sink circuit is electrically connected to the second output terminal through the third transistor.

Abstract: This application discloses a camera circuitry and a camera device. The camera circuitry includes a light collection circuit, an operational amplification circuit, an image processor and a first resistor. The light collection circuit is used to collect the brightness value and pass the collected brightness value through the operational amplification circuit and the first resistor are then transmitted to the image processor, and the image processor initiate imaging based on the brightness value. By providing an operational amplification circuit and a first resistor at the back end of the light collecting circuit, and adopting a continuous power supply mode for the light collecting circuit and the operational amplification circuit, the convergence speed of the light brightness value is effectively improved, so that accurate ambient light brightness values can be obtained faster to achieve normal camera functions.

Abstract: An analog to digital converter (ADC) includes a conversion circuit digitizing an input analog signal to produce an output digital signal. A current generator generates a constant bias current. A current mirror circuit includes an input transistor receiving the constant bias current, an output transistor in a mirroring relationship with the input transistor and generating a variable bias current, and a parallel transistor circuit selectively coupling a parallel transistor in parallel with the input transistor or the output transistor in response to a control signal. The control signal is representative of the conversion rate of the ADC. A buffer generates a common mode voltage for use by the conversion circuit, from the variable bias current.

Abstract: A circuit having capacitors, and corresponding method. A circuit and corresponding methods are provided. A controller causes a first capacitor to be connected to an input connection in a first operating phase, charge to be transferred from the first capacitor to a second capacitor in a second operating phase and charge to be transferred from the second capacitor to a processing circuit in a third operating phase. The input connection and the second capacitor belong to different voltage domains.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a first equalizer circuit and a second equalizer circuit. The first equalizer circuit is configured to equalize an input signal which is added by offset voltages that are different from each other, to generate output signals with voltage levels that are different from each other. The second equalizer circuit coupled to the first equalizer circuit. The second equalizer circuit includes a first equalizer unit and a second equalizer unit. The first equalizer unit is configured to equalize the output signals, to generate odd data signals. The second equalizer unit is coupled to the first equalizer unit and configured to equalize the output signals, to generate even data signals. A method is also disclosed herein.

Abstract: A power switch with a bootstrap driver for continuous time operation is disclosed. In an exemplary aspect, the power switch selectively connects power management circuitry to one or more power amplifier stages in a radio frequency (RF) front end. The bootstrap driver provides a constant gate to source voltage during an enabled state of the power switch such that a switching element can remain closed with near-constant closed switch resistance in the presence of varying signals (e.g., varying power signals) passing through the power switch. The bootstrap driver can use a variable clock frequency to quickly close the power switch and resistor-capacitor (RC) filtering to reduce noise contribution to the signal path through the power switch. In some examples, a constant voltage reference provides battery independent voltage control of the gate to source voltage of the power switch.

Abstract: One or more embodiments enable both a fixed bandgap reference voltage and a variable reference voltage to be generated and stored on a capacitor. According to certain aspects, the present embodiments use an additional storage capacitor of smaller size to reduce the sub-threshold leakage of an isolating FET switches at high temperatures. Among other aspects, this enables a more efficient use of chip area for reducing sub-threshold induced leakage than simply increasing the storage capacitor when precision storage is required.

Abstract: A bootstrap circuit including: a charge pump; a power unit including a bootstrap capacitor, wherein the bootstrap capacitor is charged using an output voltage of the charge pump; and a switch driver for generating a bootstrap signal based on a clock signal and an analog signal, wherein the analog signal is input to an analog switch, the switch driver for controlling the analog switch using the bootstrap signal, and including a first body switch connected between an input terminal and a body of the analog switch.

Abstract: To control a drive voltage of a transistor to be constant in a circuit that captures signals. A duty ratio control unit changes a duty ratio of a predetermined input periodic signal and outputs the predetermined input periodic signal as an output periodic signal. A transistor is a transistor that outputs an input signal input to a source from a drain as an output signal. A charge control unit charges the condenser with a predetermined voltage in a case in which the output periodic signal is not at a specific level. A transistor drive unit applies the charged predetermined voltage between a gate and the source of the transistor in a case in which the output periodic signal is at the specific level.

Abstract: An analog-to-digital converter includes an adder configured to add an input signal and a feedback signal generated based on the input signal and output an output signal as the result, a successive approximation register analog-to-digital converter (SAR ADC) configured to output a differential signal corresponding to a difference between a digital output signal obtained by quantizing the output signal output from the adder and the input signal, and a bandpass filter circuit configured to perform bandpass filtering on the differential signal output from the SAR ADC and to output the feedback signal according to a result of the bandpass filtering.

Abstract: This application relates to time-encoding modulators (TEMs). A TEM (100) receives an input signal (SIN) and outputs a time-encoded output signal (SOUT). A filter arrangement (102) receives the input signal and also a feedback signal (SFB) from the TEM output, and generates a filtered signal (SFIL) based, at least in part, on the feedback signal. A comparator (101) receives the filtered signal and outputs a time-encoded signal (SPWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp (103), capacitance (104) and switch network (105). In the first mode the op-amp (103) is enabled, and coupled with the capacitance (104) to provide the active filter.

Abstract: An embodiment attenuator includes a plurality of circuits coupled in series. A respective circuit includes a first capacitor connected between an input node of the respective circuit and an output node of the respective circuit, and a second capacitor connected between the output node of the respective circuit and a reference node. The output node of the respective circuit, other than a last circuit of the plurality of circuits, is connected to the input node of a successive circuit. The attenuator further includes a plurality of selectors, in which the respective circuit is associated with a respective selector that is coupled between the output node of the respective circuit and an output node of the attenuator.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to receive an input signal. The first switch is further coupled to a first capacitor. The S/H circuit further includes a buffer coupled to the first switch. In addition, the S/H circuit includes a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer.

Abstract: Methods of powering a radio that is mounted on a tower of a cellular base station are provided in which a direct current (“DC”) power signal is provided to the radio over a power cable and a voltage level of the output of the power supply is adjusted so as to provide a substantially constant voltage at a first end of the power cable that is remote from the power supply. Related cellular base stations and programmable power supplies are also provided.

Abstract: The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.

Abstract: A battery charging system includes a master charger that receives a supply voltage, outputs a master charging current based on the supply voltage, and selectively outputs a slave charger control signal. At least one slave charger receives the slave charger control signal from the master charger, receives the supply voltage, and selectively outputs a slave charging current based on the slave charger control signal and the supply voltage.

Abstract: Methods of powering a radio that is mounted on a tower of a cellular base station are provided in which a direct current (“DC”) power signal is provided to the radio over a power cable and a voltage level of the output of the power supply is adjusted so as to provide a substantially constant voltage at a first end of the power cable that is remote from the power supply. Related cellular base stations and programmable power supplies are also provided.

Abstract: According to an aspect, a display apparatus includes: a display panel including a plurality of pixels each including a pixel capacitor and a pixel transistor, a scanning line that is coupled to the respective pixels and is configured to receive a scan signal, and a video signal line that is coupled to the respective pixels and is configured to receive a video signal; and a driver configured to drive the display panel. The pixel transistor includes: at least one N-channel metal oxide semiconductor (NMOS) transistor coupled between the video signal line and the pixel capacitor; and a P-channel metal oxide semiconductor (PMOS) transistor coupled in parallel with the NMOS transistor.

Abstract: In some examples, a method of sensing an ink level includes applying a pre-charge voltage to a sense capacitor to charge the sense capacitor with a charge, sharing the charge between the sense capacitor and a reference capacitor, causing a reference voltage at a gate of an evaluation transistor, and determining a resistance from a drain to a source of the evaluation transistor that results from the reference voltage.

Abstract: Methods of powering a radio that is mounted on a tower of a cellular base station are provided in which a direct current (“DC”) power signal is provided to the radio over a power cable and a voltage level of the output of the power supply is adjusted so as to provide a substantially constant voltage at a first end of the power cable that is remote from the power supply. Related cellular base stations and programmable power supplies are also provided.

Abstract: Methods of powering a radio that is mounted on a tower of a cellular base station are provided in which a direct current (“DC”) power signal is provided to the radio over a power cable and a voltage level of the output of the power supply is adjusted so as to provide a substantially constant voltage at a first end of the power cable that is remote from the power supply. Related cellular base stations and programmable power supplies are also provided.

Abstract: The noise power of an amplifier or buffer can increase towards the unity gain crossover frequency of the amplifier. The inventor realized that many applications do not require the full bandwidth capability of the amplifier all of the time and hence step could be taken to reduce the bandwidth at the output of the amplifier and hence the noise power can be reduced when appropriate, taking other operating requirements into consideration.

Abstract: A receiver system for an on-off key (“OOK”) isolator system may include a receiver that generates an intermediate current signal based on an OOK input signal. The intermediate current may be provided at a first current level when the input signal has a first OOK state and a second current level when the input signal has a second OOK state. The system also may include an output driver to generate a voltage representation of the intermediate current signal. Performing signal processing in a current domain permits fast transitions between OOK states.

Abstract: An environmental control device (100), such as a thermostat, is disclosed. The environmental control device (100) has one or more terminals (222, 222a-222d) and a respective configurable interface circuit (102, 102a-102d, 300) coupled to each terminal for selectively configuring the terminal (222, 222a-222d) for a corresponding input or output connection to an HVAC system (14).