Abstract: A comparator includes an input pair circuit, an isolation circuit, and a latch circuit. The input pair circuit receives first and second input signals to generate first and second signals. The isolation circuit is selectively turned on according to a clock signal to transmit the first signal from the input pair circuit to a first output node and transmit the second signal from the input pair circuit to a second output node. The latch circuit adjusts a level of the first output node to generate a first output signal, adjusts a level of the second output node to generate a second output signal, and selectively resets the levels of the first and the second output nodes according to the clock signal. When the latch circuit resets the levels of the first and the second output nodes, the isolation circuit is not turned on.

Abstract: An isolation circuit for electrically isolating a first circuit operating at a first voltage from a second circuit operating at a second voltage that is different than the first voltage is provided. The isolation circuit includes: a first voltage source that operates at the first voltage, the first voltage source having a first supply rail and a second supply rail; an isolation device having a first input, a second input, a first output and a second output, the second input coupled to a first ground potential and the second output coupled to a second ground potential that is electrically isolated from the first ground potential by the isolation device; a first resistor coupled between the first supply rail and the first input of the isolation device; a second resistor coupled to the first input of the isolation device and the second input of the isolation device; and wherein the first output of the isolation device is coupled to the second circuit.

Abstract: A hydrocarbon heating system for a hydrocarbon production and/or transportation system comprising at least one electrical conductor and an alternating current (AC) power source connected to the at least one electrical conductor. The alternating current power source generates heat in the at least one electrical conductor by providing alternating current power to the at least one electrical conductor.

Abstract: A power voltage detector comprises voltage sensors for sensing supply voltages; and a logic. The logic combines the sensed supply voltages to generate a logic output indicative of whether the sensed supply voltages have met one or more predefined thresholds. Each of the voltage sensors has diode-connected transistors and passive resistance. The diode-connected transistors and the passive resistance are serially connected for generating an output, where the output is coupled to an input of the logic.

Abstract: A thermal sensor providing simultaneous measurement of two diodes. A first diode and a second diode are coupled to a first current source and a second current source, respectively. The ratio of the currents provided by the two sources is accurately know The voltage across each of the two diodes may be coupled to the input of a differential amplifier for determination of temperature. Alternatively, the first diode may be coupled to a first current source by a resistor with a known voltage drop, the second diode may be coupled to an adjustable second current source. The current in the second diode is equal to the sum of voltage drop across the first diode and the known voltage drop across the resistor. Under the established conditions, the Diode Equation may be used to calculate a temperature.

Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.

Abstract: A system and method have been provided for passively isolating a latch circuit. The method provides a latch having a first input, an output, and a reset port. The latch first input is selectively connected to a first reference voltage. While the latch first input is connected to the first reference voltage, the latch is reset. Subsequent to disconnecting the latch first input from the first reference voltage, a first node is selectively connecting to the latch first input. In response to selectively connecting the first node, a first analog signal is supplied to the latch first input. Subsequent to resetting the latch, the first analog signal is captured and the latch output supplies a digital signal responsive to the captured first analog signal.

Abstract: An analog disconnection envelope detection circuit having a low power supply detects a high speed, high differential voltage disconnect state on a data line. Level-shifting circuitry shifts the voltage level of two input signals by the value of a detection threshold voltage, generates differential signals used to indicate conditions of the input signals, and mitigates effects of input differential signal common-mode voltage on the detection operation. Circuitry is provided to equalize VDS of detecting tail current sources, thereby eliminating errors resulting from VDS mismatch of tail current sources. Comparator circuitry compares the sets of differential signals and indicates when the absolute difference between the two input signals is greater than a reference voltage. Output circuitry generates a disconnect signal corresponding to the disconnect condition.

Abstract: Integrated circuits having analog-to-digital converters are provided. Analog-to-digital converters may contain latched comparators. A latched comparator may include inputs configured to receive a differential input voltage signal, a differential reference voltage signal, and a clock signal. The comparator may include a preamplifier, a latching circuit, a level shifter, and a flip-flop coupled in series. The preamplifier may include large input transistors for minimizing offset, stacked tail transistors, and diode-connected load transistors for minimizing kickback noise. The preamplifier may be used to generate amplified voltage signals. The latching circuit may include a first pair of cross-coupled pull-down transistors, a second pair of cross-coupled pull-up transistors, and precharge transistors.

Abstract: A method for generating a signal is provided, the method including: providing a first signal having a first signal frequency; providing a second signal having a second signal frequency or a third signal frequency, wherein the second signal frequency is higher than the third signal frequency; switching the second signal having the second signal frequency to the third signal frequency based on a predefined first signal event of the first signal; and returning the second signal having the third signal frequency to the second signal frequency in response to a predefined second signal event.

Abstract: The electronic circuit includes a first comparator and a second comparator in which an induced electromotive force of a coil are compared with each of a first reference potential and a second reference potential and which output a pulse signal in accordance with conditions; the first signal processing circuit which outputs a first receiving rectangular wave signal and a first error signal in accordance with conditions of the pulse signal output from the first comparator and in which data held in accordance with conditions of pulse signal output from the second comparator is reset; and the second signal processing circuit which outputs a second receiving rectangular wave signal and a second error signal in accordance with conditions of the pulse signal output from the second comparator and in which data held in accordance with conditions of pulse signal output from the first comparator is reset.

Abstract: An interpolation circuit includes: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter.

Abstract: A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state.

Abstract: A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.

Abstract: A hysteresis comparator circuit that compares first and second input signals to output a hysteresis output signal includes a constant current source, a first comparator, a second comparator, and an output circuit. The constant current source includes a load resistor to generate a given constant current. The first comparator is controlled by the constant current supplied from the constant current source to compare the first and second input signals to output a first comparison result. The second comparator is controlled by the constant current supplied from the constant current source to compare the first and second input signals to output a second comparison result. The output circuit has a pair of inputs thereof connected to the first and second comparators, respectively, which inverts an output thereof in response to each of the first and second comparison results to generate the hysteresis output signal.

Abstract: A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Abstract: Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, an apparatus includes a power detector circuit powered by a first voltage supply. At least one voltage level-shifting device is coupled to a second voltage supply and a test input is provided to the power detector circuit. An optional leakage self-control device may reduce unwanted leakage currents associated with the first supply and the second supply.

Abstract: A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units.

Abstract: A compare circuit for comparing a first data word with a second data word includes a plurality of sub-circuits, each having a two-bit static compare stage and a dynamic complex logic stage; a dynamic compare node responsive to respective outputs of the sub-circuits; and an output latch that captures a comparison result in accordance with a logic state of the dynamic compare node. In an exemplary embodiment, a local clock generator provides a single controlling clock signal for clocking the output latch, precharging of the dynamic compare node, and clocking of the dynamic complex logic stage of the sub-circuits.

Abstract: According to one embodiment of the present invention, it is possible to realize a signal transmitter which is capable of reducing power consumption and which can be easily designed. A differential transmitter block outputs differential output signals fixed to a predetermined logic signal to a differential receiver block and disconnects terminating resistors from a signal transmission path in an idle state. In the differential receiver block, a differential comparator outputs a logic determined by symbols of the differential output signal from the differential transmitter block, and an operating state detector detects the idle state upon detection that time successively outputting a predetermined logic by the differential comparator reaches a predetermined time, and controls switches so as to disconnect the terminating resistors from the signal transmitter in the receiving side upon detection of the idle state.

Abstract: According to one embodiment, a test circuit comprises a function block, a test circuit, and a signal generation circuit. The test circuit is arranged in an area close to the function block having a plurality of transistors. The test circuit comprises a first flip-flop circuit, a second flip-flop circuit, and a logic circuit connected between the output of the first flip-flop circuit and the input of the second flip-flop circuit. The signal generation circuit generates clock pulses including a first clock pulse and a second clock pulse. The signal generation circuit is capable of controlling a pulse interval between the first clock pulse and the second clock pulse. In a test, the first flip-flop circuit outputs data in synchronization with the first clock pulse of the signal generation circuit and the second flip-flop circuit latches data in synchronization with the second clock pulse of the signal generation circuit.

Abstract: A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay circuit that delays the first data and generates second data, and a second flip flop that stores the second data. Furthermore, the speed performance measurement circuit includes a first comparator circuit that compares output of the first flip flop to output of the second flip flop, and a third flip flop that stores output data from the first comparator circuit in accordance with timing of the first clock signal. Data in a normal path is compared to data in a path delayed by a certain time to measure speed, and power voltage of a circuit is determined based on such comparison. Thus, change in speed with respect to power voltage in a critical path can be measured.

Abstract: A latched comparator circuit (1) comprises an input amplification unit (10), a buffer unit (20), and a control unit (30). The input amplification unit (10) comprises a first and a second input terminal (40a, 40b) for receiving a first and a second input voltage, respectively, of the latched comparator circuit (1). The input amplification unit (10) further comprises a first and a second output terminal (50a, 50b) for outputting a first and a second output voltage, respectively, of the input amplification unit (10). In addition, the input amplification unit (10) comprises a reset terminal (60) arranged to receive a reset signal for resetting the input amplification unit. The buffer unit (20) is operatively connected to the first and the second output terminal (50a, 50b) of the input amplification unit (10). Furthermore, the buffer unit (20) comprises a first and a second output terminal (70a, 70b) for outputting a first and a second output voltage, respectively, of the buffer unit (20).

Abstract: A clock detector is provided. The clock detector generally comprises a filter, a first branch, a second branch, a latch, and logic. The filter is adapted to receive a clock signal and is coupled to a low threshold inverter in the first branch and a high threshold inverter in the second branch. The latch is adapted to receive the clock signal and is coupled to the first branch, while the logic is coupled to the node between the first branch and the latch, an output of the latch, and the second branch so that it can output a clock detection signal.

Abstract: In some examples, a differential comparator includes a differential amplifier configured to output differential output signals, a first switch portion configured to input the differential output signals from the differential amplifier and output the differential output signals from output terminals while alternatively changing over the output terminals, a latch portion configured to update and latch the differential output signals from the output terminals of the first switch portion, and a second switch portion configured to input output signals from the latch portion and output the latched output signals. The first switch portion and the second switch portion are changed over complementarily so that the differential output signals from the differential amplifier are always outputted from the same first and second output terminals of the second switch portion respectively.

Abstract: A calibration method for an oversampling acquisition system uses a digital calibration signal that has a period between edges that is unrelated to the period of a sample clock. The calibration signal in input in parallel to a plurality of samplers, each of which is clocked at a different time by a delayed version of the sample clock, to produce a plurality of sequential samples per sample clock period. Edge transitions of the calibration signal are counted that occur between adjacent ones of the samplers, and are accrued over an acquisition period to produce a plurality of edge counts. The edge counts are then processed to produce control signals to adjust the sample clock delay for each sampler so that the time intervals between the sequential samples are essentially uniform.

Abstract: In one embodiment, a method for a control interface includes: receiving a signal conveying bits of information over a single line; and for each bit of information, comparing the proportion of time that the signal on the single line is low versus the proportion of time that the signal on the single line is high for a respective bit period defined from one operative edge of the signal to the next operative edge of the signal in order to determine a logic value for that bit of information.

Abstract: Techniques pertaining to a comparator circuit with reduced power consumption are disclosed. According to one aspect of the present invention, the comparator unit has a pair of input signal pins VIP and VIN, a pair of output signal pins VOR and VOS, and a clock signal pin CLK. In operation, when the CLK signal is at an idle voltage level, the comparator unit comes into an idle state. At the idle state, the comparator unit does not compare the two input signals VIP and VIN so that the output signals are identical. When the CLK signal is at a busy voltage level, the comparator comes into a busy state. At the busy state, the comparator compares the input signals VIP and VIN, and determines the values of the output signals VOR and VOS depending on the comparing result, e.g., if the input signal VIP is larger than the input signal VIN, the output signal VOR is high and the output signal VOS is low; otherwise, the output signal VOR is low and the output signal VOS is high.

Abstract: In some examples, a differential comparator includes a differential amplifier configured to output differential output signals, a first switch portion configured to input the differential output signals from the differential amplifier and output the differential output signals from output terminals while alternatively changing over the output terminals, a latch portion configured to update and latch the differential output signals from the output terminals of the first switch portion, and a second switch portion configured to input output signals from the latch portion and output the latched output signals. The first switch portion and the second switch portion are changed over complementarily so that the differential output signals from the differential amplifier are always outputted from the same first and second output terminals of the second switch portion respectively.

Abstract: A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal.

Abstract: A data receiver of a semiconductor integrated circuit includes an amplifier that outputs an amplified signal by detecting and amplifying received data using equalization function according to feedback data, a detecting unit that detects a period when data is not received in the amplifier and outputs a detecting signal, and an equalization function control unit that stops the equalization function of the amplifier in response to the detecting signal.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a first switched capacitor comparator to be charged to a first reference voltage and to compare an input signal to the first reference voltage and to generate a first output signal when the input signal reaches the first reference voltage. A second switched capacitor comparator to be charged to a second reference voltage and to compare the input signal to the second reference voltage and to generate a second output signal when the input signal reaches the second reference voltage. Time between the first output signal and the second output signal is slew rate of the input signal.

Abstract: A switch de-bouncing device includes a majority counter that counts samples generated by a sampler sampling a switch output where a counter value is incremented for each sample indicating a first switch state and decremented for each sample indicating a second switch state of the switch. A controller determines that the switch is in the first switch state when the counter value is above a first state threshold and is in the second switch state when the counter value is below a second state threshold.

Abstract: Techniques pertaining to a comparator circuit with reduced power consumption are disclosed. According to one aspect of the present invention, the comparator unit has a pair of input signal pins VIP and VIN, a pair of output signal pins VOR and VOS, and a clock signal pin CLK. In operation, when the CLK signal is at an idle voltage level, the comparator unit comes into an idle state. At the idle state, the comparator unit does not compare the two input signals VIP and VIN so that the output signals are identical. When the CLK signal is at a busy voltage level, the comparator comes into a busy state. At the busy state, the comparator compares the input signals VIP and VIN, and determines the values of the output signals VOR and VOS depending on the comparing result, e.g., if the input signal VIP is larger than the input signal VIN, the output signal VOR is high and the output signal VOS is low; otherwise, the output signal VOR is low and the output signal VOS is high.

Abstract: A deglitch circuit capable of removing noise with low power consumption. Voltage is input to a first inverter, connected to a power supply line via a first current source and grounded via a second current source. The first inverter is grounded via a capacitor and connected to first and second transistors. The gate terminals of these transistors receive a second control voltage, which is lower than the power supply voltage, and a first control voltage, which is higher than the ground level. The second transistor is connected to the ground line via a fourth current source. First voltage is supplied to a first input terminal of the latch circuit via a second inverter. The first transistor is connected to the power supply line via a third current source. Second voltage is supplied to a second input terminal of the latch circuit via the second inverter.

Abstract: A system and method is disclosed for providing a clock and data recovery circuit that comprises a low jitter data receiver. The low jitter data receiver comprises a phase interpolator, an amplifier unit and a data sampling comparator. The phase interpolator and the amplifier unit provide the data sampling comparator with a single ended clock signal that is relatively immune to power supply noise. The data sampling comparator samples an input data stream with minimal jitter due to power supply noise. The data sampling comparator consumes less static power than a current mode logic D flip flop and also has output levels that are compatible with complementary metal oxide semiconductor (CMOS) logic.

Abstract: A stable, low power consumption signal detecting circuit may include: a delay circuit, which receives a base clock signal and generates multiple versions thereof having time delay relationships thereto, respectively; dual amplifiers, which detect valid ones of input signals by comparing the input signals with reference voltage signals in response to the multiple versions of the base clock signal, respectively; a combining unit, which generates a combination signal in response to output signals of the dual amplifiers; and a sampling circuit, which samples the combination signal according to the base clock signal and generates an output signal.

Abstract: Low-power and low-noise CDS (correlated double sampling) comparators for use with a CIS (CMOS image sensor) device are provided. A CDS comparator is constructed using one of various low-power inverters that provide decreased instantaneous transition currents at a logic threshold voltage. The use of such low-power inverters in CDS comparators enables a significant reduction in power consumption and noise in the CIS device, or other devices that implement such CDS comparators and/or inverters.

Abstract: The invention relates to a circuit arrangement for pulse generation, having a capacitor, to which a charging current and a discharging current may be supplied in succession. To generate the charging current and the discharging current, there are provided a current source, a first current mirror circuit and a second current mirror circuit complementary to the first current mirror circuit. The current mirror circuits each comprise a plurality of output transistors, which each constitute an output stage for the charging and discharging current, which is connected to a regulator, and for a circuit for controlling the tail current of a differential amplifier forming the regulator. A current output of the differential amplifier is connected to the output of the second current mirror circuit.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: A linearized folding amplifier circuit (30) includes a comparator (40) that has a first state and a second state, and a switched output circuit that has a pair of outputs. The non-linearity in the response of a differential transistor pair to an input signal is partially linearized by a first resistor connecting the emitters of the two input transistors. The input is further linearized in response to the first and second state-controlling pairs of transistors and a differential error voltage therebetween that is replicated from the differential error in the base-voltages emitter voltages of the input differential pair. The output of the circuit is the combination of the partially linearized portion from the first resistor and a linearized transconductor circuit that has an output formed in response to the differential error.

Abstract: A circuit for providing a control voltage to a switch includes a capacitor, a first pair of switches for coupling the capacitor to an input voltage source and a second pair of switches for coupling the capacitor to the switch. The first pair of switches is controlled by a control signal in response to the voltage across the capacitor in order to prevent overcharging the capacitor beyond a first predetermined level. The second pair of switches is controlled by a second control signal in response to the voltage across the switch in order to replenish the capacitor voltage when the capacitor voltage falls to a second predetermined level. The first and second pairs of switches are closed during non-overlapping time intervals in order to isolate the switch from the input voltage source, thereby preventing switching transients from affecting the input voltage source and permitting the circuit to be used to drive a variety of switch types arranged in a variety of configurations.

Abstract: A circuit that senses changes in the electrical characteristics of a guard ring, and generates one or more signals based, at least in part, on the electrical characteristics that are sensed, is incorporated into an integrated circuit The one or more signals generated by the circuit are indicative of the reliability of the integrated circuit. In one embodiment of the present invention, a first point of the guard ring is electrically coupled to a voltage supply node by a switchable element such as a MOSFET, and at least two points of the guard ring are electrically coupled respectively to two input terminals of a differential amplifier circuit in such a way that voltage changes across the guard ring can be sensed.

Abstract: An automatic input threshold selector includes a maximum value level decision circuit, and an input threshold setting circuit. The maximum value level decision circuit decides, among m+1 level layers defined by m maximum value decision levels, a level layer to which the maximum value of an input signal belongs. The input threshold setting circuit sets an input threshold by selecting one of n input threshold candidates in response to the level layer to which the input signal maximum value belongs. These circuits are implemented as a simple combination of a voltage comparator, logic gates and the like. This makes it possible to solve a problem of a conventional automatic input threshold selector in that its circuit scale and power consumption is rather large because it includes a peak-hold circuit and a bottom-hold circuit.

Abstract: A power-up detection circuit to produce a power-up detection signal detects a reference voltage of a device. After a power-up detection has been produced, a DC current path to ground is established to conduct DC current to reset the power-up detection circuit to produce a subsequent power-up detection signal.

Abstract: A circuit that senses changes in the electrical characteristics of a guard ring, and generates one or more signals based, at least in part, on the electrical characteristics that are sensed, is incorporated into an integrated circuit. The one or more signals generated by the circuit are indicative of the reliability of the integrated circuit.In one embodiment of the present invention, a first point of the guard ring is electrically coupled to a voltage supply node by a switchable element such as a MOSFET, and at least two points of the guard ring are electrically coupled respectively to two input terminals of a differential amplifier circuit in such a way that voltage changes across the guard ring can be sensed.

Abstract: A level detection circuit, such as a Schmitt trigger circuit, has an input threshold voltage which varies depending upon the detection circuit output. The circuit includes a level detection stage, circuitry for switching the level detection stage between an active and a standby mode and a storage device for storing data indicative of the input threshold voltage when the level detection stage is in the standby mode and for controlling the level detection stage using the stored data so that the stage will retain the same input threshold voltage that existed when the level detection stage was switched to the standby mode.

Abstract: A pad signal detecting circuit for detecting a reference voltage input to a pad of a semiconductor device. This invention may be used in high speed terminated interfaces using a reference voltage, such as those using stub series termination logic (SSTL). The invention allows the manufacture of semiconductor devices having more than one type of interface, because the device can sense the type of interface which is connected to the pad and activate the appropriate interface circuitry. This feature eliminates the need to manufacture different devices for different types of interfaces, and it facilitates high volume and low cost production of semiconductor devices that are compatible with more than one type of interface circuitry.

Abstract: An integrated XNOR flip-flop is provided which is faster than conventional XNOR flip-flop combinations. The integrated XNOR flip-flop is faster and uses less area than conventional XNOR flip-flop combinations. The integrated circuit has few gates along the critical path and takes advantage of the set up times inherent in the flip-flop. Accordingly, the integrated XNOR flip-flop is able to perform the same function in an expedient manner. In one illustrative embodiment, a plurality of the integrated XNOR flip-flops are used to compare a tag of a cache memory with an address to determine whether the desired address is available in the cache.

Abstract: A data holding circuit is provided that reduces a setup time and hold time when a data is inputted to effectively transmit output data. The data holding circuit includes a latch unit that samples and holds input data, a delay unit that delays a control signal, and a three-phase buffer. The three-phase buffer is enabled based on a delayed control signal from the delay unit to hold data from the latch unit LAT and to transmit output data.