Abstract: There is disclosed an input circuit for a semiconductor integrated circuit device wherein a level shift circuit (LS1) adds a constant voltage to an input signal from an input signal terminal (3) and a reference voltage from a reference voltage terminal (4) to output signals, which are in turn amplified by means of a plurality of cascaded, first and second differential amplifier circuits (Dif1, Dif2), and then a difference between the amplified input signal and the amplified reference voltage is applied to a CMOS inverter circuit (In1), which in turn outputs a power supply potential (V.sub.DD) or a ground potential (V.sub.SS) in accordance with the difference, thereby achieving a high-speed operation in response to the binary input signal slightly varying in signal voltage and a normal operation independent of variation of the reference voltage. (FIG.

Abstract: The present invention relates to a comparator circuit which is arranged such that detected data signal is waveform-shaped without producing any bit error, so that the data signal as transmitted can be accurately demodulated. Reference voltage V.sub.RE of the comparator which is compared with the data signal V.sub.IN is provided by adding output resulting from integration of the data signal V.sub.IN and integrated output of an inverter 2 which inverts output of the comparator 1. The reference voltage V.sub.RE of the comparator 1 can always be located at the center between the high level and the low level of the data signal V.sub.IN despite variations in DC voltage level of the data signal V.sub.IN.

Abstract: The invention facilitates testing of electrical circuitry which includes a circuit receiving a signal asynchronous with respect to the circuit clock. The exact clock pulse on which the asynchronous signal is asserted may be difficult or impossible to predict even when the circuitry inputs are known. However, a range of pulses can be determined during which the asynchronous signal is asserted. The sampling of the asynchronous signal is blocked until the end of the range of pulses. If it is known that at the end of the range of pulses the asynchronous signal should still be asserted provided that the circuitry functions properly, the asynchronous signal is sampled at the end of the range of pulses. Alternatively, if the asynchronous signal can be deasserted by the end of the range of pulses, the assertion of the asynchronous signal is detected and latched by the asynchronous signal pulse detector, and at the end of the range of pulses the circuit samples the value latched by the pulse detector.

Abstract: In an autozero type MOSFET comparator, the spurious current induced by the high frequency input voltage can flow through the resistance of the reset switch to introduce an offset voltage error during the autozero mode. A canceler is used to prevent the spurious current from flowing through the reset switch. A T-network with two series capacitors and a shunt switch is used as the canceler. The spurious current is by-passed by the shunt switch and prevented from flowing through the reset switch placed at the output of the T-network.The spurious current canceler is particularly useful for a sub-ranging ADC, where the comparator is used also as a sample-and-hold circuit to hold the input voltage across the series capacitors by opening all the sampling switches, the reset switch and the shunt switch.