With Amplifier Condition Indicating Or Testing Means Patents (Class 330/2)
  • Patent number: 11933848
    Abstract: In a measurement system, a signal probing circuit may provide probed signals by probing voltages and currents and/or incident and reflected waves at a port of a device under test (DUT). A multi-channel receiver structure may include receivers that receive two probed signals from the signal probing hardware circuit, each receiver having its own sample clock derived from a master clock and further having a respective digitizer for digitizing a corresponding one of the two probed signals. A synchronization block, external to the receivers and including a reference clock derived from the master clock, may enable the two probed signals to be phase coherently digitized across the receivers by synchronizing the respective sample clocks of the receivers while the reference clock is being shared with the receivers. A signal processing circuit may then process the phase coherently digitized probed signals.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: March 19, 2024
    Assignee: National Instruments Ireland Resources Limited
    Inventor: Marc Vanden Bossche
  • Patent number: 11876491
    Abstract: A method for digital predistortion (DPD) calibration in a wireless communication device is provided that includes transmitting, by transmission circuitry of the wireless communication device, a plurality of pulses, where each pulse corresponds to an amplitude step in a pattern of amplitude steps, where the amplitude steps are separated by silence gaps, receiving each pulse in receiver circuitry of the wireless communication device, generating, by an accumulator component of the wireless communication device, an accumulated sample for each pulse based on a plurality of samples output by the receiver circuitry for the pulse, and computing, by a processor of the wireless communication device, amplitude dependent gain (AM/AM) and amplitude dependent phase shift (AM/PM) values for each accumulated sample.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: January 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raghu Ganesan, Harish Kumar Ramesh, John Roshan Samuel Chandran, Lakshmi Bala Krishna Manoja Vinnakota
  • Patent number: 11519972
    Abstract: A method for performing predictive maintenance of an amplifier module is described. At least one parameter of at least one amplifier module is acquired via a measurement data acquisition unit. The at least one parameter acquired is analyzed via a measurement data analyzing unit so as to predict the probability and/or time of default of the at least one amplifier module. Further, a system is described.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: December 6, 2022
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Raimon Goeritz
  • Patent number: 11411542
    Abstract: A transimpedance amplifier circuit includes a single-input amplifier that converts a current signal into a voltage signal, a control current circuit that generates a control current based on the voltage signal and a reference voltage signal, and a bypass circuit. The bypass circuit includes a control circuit configured to receive the control current, a feedback current source configured to generate a direct current (DC) bypass current, and a variable resistance circuit configured to generate an alternating current (AC) bypass current. The control circuit includes a first current mirror circuit that varies the DC bypass current via the feedback current source in accordance with the control current, and a second current mirror circuit that varies the AC bypass current via the variable resistance circuit in accordance with the control current and an offset current.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: August 9, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Keiji Tanaka
  • Patent number: 11349444
    Abstract: In a transimpedance amplifier circuit, a control current circuit generates a control current based on a voltage signal and a reference voltage signal and includes an integrating circuit that generates a differential integral signal based on the voltage signal and the reference voltage signal, and a transconductance amplifying circuit that includes a first transconductance circuit that generates a first output current in accordance with the differential integral signal, a second transconductance circuit that generates a second output current in accordance with the differential integral signal, and a current source that supplies a third output current, and a control circuit has an input electrically connected to an output of the first transconductance circuit, an output of the second transconductance circuit, and an output of the current source.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: May 31, 2022
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Keiji Tanaka
  • Patent number: 11264956
    Abstract: A DC offset cancellation circuit and a DC offset cancellation method are disclosed. The DC offset cancellation circuit comprises a high-speed amplifier, a voltage comparator, a microprocessor, and a digital-to-analog converter. The high-speed amplifier comprises an input stage with a DC offset cancellation function, an amplification stage, and an output buffer stage. The voltage comparator is connected to the output buffer stage. The microprocessor is connected to the voltage comparator. The digital-to-analog converter is connected to the microprocessor. The digital-to-analog converter is connected to the input stage.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 1, 2022
    Assignee: XIAMEN UX HIGH-SPEED IC CO., LTD.
    Inventors: Kexun Zhang, Junhua Ge, Jie Zhou, Jianhua Pan
  • Patent number: 11233590
    Abstract: Disclosed is a voltage detector and a communication circuit capable of detecting a low input voltage. The voltage detector includes: an alternating-current coupling circuit generating a first and a second input voltages according to a source input voltage; a feedback amplifier outputting a branch current according to a sink current including the branch current, and determining an output voltage according to the first input voltage and the amount of the branch current; and an auxiliary circuit outputting the amount of the sink current according to the second input voltage. When the sink current increases as the second input voltage rises, the branch current also increases, so that the output voltage not only rises as the first input voltage rises but also rises as the branch current increases. This feature allows a lower input voltage to be detectable by the detection of the risen output voltage.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: January 25, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chung-Yu Lin
  • Patent number: 11228289
    Abstract: This application describes an amplifier circuit (200) with a forward signal path with a class-D output stage (102) for generating a driving signal (Sout) based on a digital input signal (Sin). The amplifier has a first feedback path for providing a first digital feedback signal (Sfb1) based on the driving signal and a second feedback path for providing a second digital feedback signal (Sfb2) from a digital part of the forward signal path. The digital input signal (Sin) is combined with a selected feedback signal (Sfbs). The amplifier circuit is selectively operable in a first mode, in which the first feedback signal is used as the selected feedback signal, and in a second mode, in which the second feedback signal is used as the selected feedback signal. A calibration module (204) is operable to calibrate the first feedback path to reduce any DC offset when the amplifier circuit is operating in the second mode.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: January 18, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Angus Black, Hemant Shukla
  • Patent number: 11137445
    Abstract: A system and method for operating a data processing system to modify a time domain input signal to a signal generator to correct for distortions introduced by the signal generator are disclosed. The method includes receiving a target signal specifying a signal to be generated by the signal generator and initializing an input signal with the target signal, the method includes a) inputting the input signal to the signal generator to arrive at a signal generator output signal; b) measuring a frequency spectrum of the signal generator output signal with a test instrument; c) updating the input signal based on a comparison of said measured frequency spectrum and a frequency spectrum of target input signal; and d) repeating steps a)-c) until an exit condition is satisfied.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 5, 2021
    Assignee: Keysight Technologies, Inc.
    Inventors: Jan Verspecht, Augustine Stav
  • Patent number: 11140628
    Abstract: A method for saving power of a radio frequency (RF) system is provided herein. The method includes the steps of supplying a RF transmitter of the RF system configured for sending a RF transmission at a first transmission power level and supplying a RF receiver in communication with a controller of the RF system, the RF receiver configured for receiving the RF transmission from the RF transmitter. The controller includes a control algorithm to adjust the transmission power level of the RF transmitter based upon a status of a data frame to be received by the RF receiver. An RF system using the aforesaid method is also provided.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 5, 2021
    Assignee: CONTINENTAL AUTOMOTIVE GMBH
    Inventor: Brian Sunil Nicholas Fernandes
  • Patent number: 11088661
    Abstract: Power amplifier (PA) devices and methods for fabricating PA devices containing inverted power transistor dies are disclosed. In embodiments, the PA device includes a first set of input and output leads, an inverted first power transistor (e.g., peaking) die electrically coupled between the first set of input and output leads, and a base flange. The inverted first power die includes, in turn, a die body having a die frontside and a die backside opposite the die frontside. A power transistor having a first contact region is formed in the die frontside. A frontside layer system is formed over the die frontside and the power transistor, while an electrically-conductive bond layer attaches the inverted first power transistor die to the base flange. The first contact region of the power transistor is electrically coupled to the base flange through the electrically-conductive bond layer and through the frontside layer system.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 10, 2021
    Assignee: NXP USA, Inc.
    Inventor: Darrell Glenn Hill
  • Patent number: 11082020
    Abstract: A vehicle includes an antenna configured to receive a broadcast signal, an amplifier configured to amplify the broadcast signal, a detector configured to detect an output signal of the amplifier, a variable transformer configured to output a negative feedback signal based on the detected output signal, an auto gain control configured to control an input signal of the amplifier based on the negative feedback signal and a controller configured to control the variable transformer and the auto gain control based on the output signal of the amplifier.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: August 3, 2021
    Assignees: Hyundai Motor Company, Kia Motor Corporation
    Inventor: Jungnam Bae
  • Patent number: 11057063
    Abstract: A model structure modeling a power amplifier is based on at least a binomial expansion, a first building block, a second building block, and a third building block. The first building block is a first complex sub-band signal with a first delay, the second building block is a multiplication of the first complex sub-band signal with a second delay and a complex conjugate of the first complex sub-band signal with a third delay, and the third building block is a multiplication of a second complex sub-band signal with a fourth delay and a complex conjugate of the second complex sub-band signal with a fifth delay. The sum of the first complex sub-band signal and the second complex sub-band signal is a baseband signal. Terms are obtained by optimizing delay combinations for the model structure. The model structure is used to dual-band digital pre-distortion of the baseband signal.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: July 6, 2021
    Assignee: NOKIA SOLUTIONS AND NETWORKS OY
    Inventor: Tian He
  • Patent number: 11012105
    Abstract: Systems, circuitries, and methods for predistorting a digital signal in a transmit chain based on a predistortion function are provided in which the function is determined based on a first digital signal or a first transmit chain state. A method includes: receiving a second digital signal that is input to the transmit chain, wherein the transmit chain is characterized by a present transmit chain state; performing a first operation on the second digital signal to generate an adapted digital signal, wherein the first operation is based on either a relationship between the first digital signal and the second digital signal, or a relationship between the first transmit chain state and the present transmit chain state; predistorting the adapted digital signal based on the predistortion function; and performing a second operation on the predistorted adapted signal, wherein the second operation corresponds to an inverse of the first operation.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: May 18, 2021
    Assignee: Apple Inc.
    Inventors: Andreas Langer, Christoph Hepp, Andreas Menkhoff, Gunther Kraut
  • Patent number: 10996694
    Abstract: A regulator includes an operational amplifier, a programmable offset voltage, and a circuit. The operational amplifier includes a non-inverting input, an inverting input, and an output. The programmable offset voltage is configured to cancel a built-in offset voltage of the regulator based on a code. The circuit is configured to set the code based on a sensed built-in offset voltage of the regulator in response to an offset cancellation calibration mode enable signal.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ki-Jun Nam, John David Porter
  • Patent number: 10951181
    Abstract: Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may be utilized in a digital-to-analog converter. The amplifier circuit may comprise a first operational amplifier with a feedback circuit. The feedback circuit may comprise an inverting amplifier circuit.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: March 16, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Akinobu Onishi
  • Patent number: 10911006
    Abstract: An amplifier circuit may include an isolated amplifier circuit, disposed on a high voltage side of the amplifier circuit, and arranged to generate an isolated output signal. The amplifier circuit may include a first optocoupler circuit, disposed to receive the isolated output signal from the isolated amplifier circuit and an output amplifier circuit, disposed on a low voltage side of the amplifier circuit, and coupled to receive an optical output signal from the optocoupler circuit. The amplifier circuit may also include a calibration circuit, coupled to the output amplifier circuit, to generate a calibration initiation signal, and a second optocoupler circuit, disposed to receive the calibration initiation signal, and to output a switch signal, wherein a reference voltage is output to the isolated amplifier circuit.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: February 2, 2021
    Assignee: Littelfuse, Inc.
    Inventor: Michael Gambuzza
  • Patent number: 10901012
    Abstract: A method for calculating a calibration gain used for common-mode rejection in a current sensing system may include measuring a first value of a common-mode voltage associated with the current sensing system and a first output value of the current sensing system occurring at the first value of the common-mode voltage, measuring a second value of the common-mode voltage associated with the current sensing system and a second output value of the current sensing system occurring at the second value of the common-mode voltage, and based on a difference between the second output value of the current sensing system and the first output value of the current sensing system and a difference between the second value of the common-mode voltage and the first value of the common-mode voltage, calculating the calibration gain.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 26, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Katy Holland, Vamsikrishna Parupalli, Christian Larsen, Graeme Mackay
  • Patent number: 10896803
    Abstract: A method for measuring conductance of a material real-time during etching/milling includes providing a fixture having a socket for receiving the material. The socket is attached to a printed circuit board (PCB) mounted on one side of a plate that has at least one opening for providing ion beam access to the material sample. Conductive probes extend from the other side of the PCB to contact and span a target area of the material. A measurement circuit in electrical communication with the probes measures the voltage produced when a current is applied across the material sample to measure changes in electrical properties of the sample over time.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: January 19, 2021
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Shane A. Cybart, Robert C. Dynes
  • Patent number: 10826450
    Abstract: The present invention provides a system and method for operating hybrid concurrent and switched dual-band low noise amplifiers. Embodiments use a concurrent design at the input block of a hybrid LNA to advantageously achieve better impedance matching while using a switch capacitor design at the output block to advantageously achieve a better gain than typical concurrent multiband LNAs. Embodiments might be integrated into wireless devices configured to simultaneously receive on multiple frequency bands while providing gains of 30 dB or more by combining the advantages of concurrent multiband LNAs with the advantages of switched multiband LNAs. In addition to the higher gains provided by embodiments of the hybrid LNA described herein, hybrid multiband LNAs according to embodiments of the present invention provide a smaller device footprint and power requirements than would be required for a receiver including multiple single-band LNAs for amplifying signals for each frequency band individually.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: November 3, 2020
    Assignee: HuWoMobility, Inc.
    Inventors: Lin Zhou, Shih Mo
  • Patent number: 10790745
    Abstract: The invention relates to a control system for a DC-to-DC converter. Variations in the input voltage of the DC-to-DC converter are compensated by an estimated value being calculated for the variations, and a control variable being determined for the DC-to-DC converter based on the estimated values of the input voltage. The estimated values for the input voltage can, for example, be determined on the basis of a polynomial, for example using a Lagrange expansion.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: September 29, 2020
    Assignee: Robert Bosch GmbH
    Inventor: Gholamabas Esteghlal
  • Patent number: 10768242
    Abstract: Systems and methods for detecting ground faults in a power transmission circuit powering a load. The system includes a common mode union that is connected to a positive terminal of a power supply and a negative terminal of the power supply. The power supply may be a bifurcated symmetrical power source. A power supply symmetry circuit is connected to the common mode union and a offset threshold comparator circuit is connected to the power supply symmetry circuit. The offset threshold comparator circuit is configured to compare a signal from the power supply symmetry circuit to a threshold voltage value and generate a ground-fault signal indicating a ground fault when the signal from the power supply symmetry circuit exceeds a threshold voltage value. A local load control circuit is connected to the offset threshold comparator circuit and configured to receive a signal from the offset threshold comparator circuit.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 8, 2020
    Assignee: COTTONWOOD CREEK TECHNOLOGIES, INC.
    Inventors: Dwight W. Kitchin, Alan K. Schott
  • Patent number: 10560063
    Abstract: A method of constructing an amplifier circuit includes simulating an output of an amplifier device of the amplifier circuit over a range of impedances to yield a simulated maximum power and a simulated maximum power added efficiency at a particular frequency, fabricating a plurality of output matching networks and input matching networks with impedances above and below the impedances that yield the simulated maximum power and simulated maximum power added efficiency, empirically determining physical dimensions of an optimized output matching network and an optimized input matching network that result in actual impedances that provide an actual maximum power and maximum power added efficiency at the particular frequency, and coupling the optimized output matching network to an output of the amplifier device and coupling the optimized input matching network between an output of a driver circuit and an input of the amplifier device.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: February 11, 2020
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: Steven N. Bundick, Wei-Chung Huang
  • Patent number: 10456933
    Abstract: System and method for improving the shaving experience by providing improved visibility of the skin shaving area. A digital camera is integrated with the electric shaver for close image capturing of shaving area, and displaying it on a display unit. The display unit can be integral part of the electric shaver casing, or housed in a separated device which receives the image via a communication channel. The communication channel can be wireless (using radio, audio or light) or wired, such as dedicated cabling or using powerline communication. A light source is used to better illuminate the shaving area. Video compression and digital image processing techniques are used for providing for improved shaving results. The wired communication medium can simultaneously be used also for carrying power from the electric shaver assembly to the display unit, or from the display unit to the electric shaver.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: October 29, 2019
    Assignee: May Patents Ltd.
    Inventor: Yehuda Binder
  • Patent number: 10461713
    Abstract: A radio-frequency (RF) amplifier device comprises a signal input for receiving an RF electrical signal, a variable-gain amplifier for amplifying the received signal, and a signal output for outputting the amplified signal. The device has a binary input for switching a gain of the amplifier between a first level and the custom gain level. Configuration logic receives serialised data encoding a custom gain level at a serial input, and stores data representative of the custom gain level in a memory of the device. Gain-control logic reads the data representative of the custom gain level from the memory, and sets the gain of the amplifier to the first level or to the custom gain level in dependence on a state of the binary input.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 29, 2019
    Assignee: Nordic Semiconductor ASA
    Inventors: David Alexandre Engelien-Lopes, Bartosz Gajda, Kjetil Holstad
  • Patent number: 10439562
    Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. Other embodiments include bias compensation circuits that directly regulate a bias signal to an amplifier stage as a function of localized heating of one or more of amplifier stages. Such bias compensation circuits include physical placement of at least one bias compensation circuit element in closer proximity to at least one amplifier stage than other bias compensation circuit elements. One bias compensation circuit embodiment includes a temperature-sensitive current mirror circuit for regulating the bias signal.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 8, 2019
    Assignee: pSemi Corporation
    Inventors: Ikumi Tokuda, Tero Tapio Ranta, Keith Bargroff, Christopher C. Murphy, Robert Mark Englekirk
  • Patent number: 10365702
    Abstract: Over at least part of a lifetime of a product circuit, quiescent current to a product circuit is periodically measured. Over the part of the lifetime of the product circuit, voltage to the product circuit is periodically adjusted based on the monitored quiescent current. Methods, apparatus, and computer program product are disclosed. A calibration procedure may also be performed as part of manufacturing the product circuit, in order to provide values for the quiescent current and corresponding voltage to which the voltage should be adjusted.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chen-Yong Cher, Pierce I Chuang, Keith A Jenkins, Barry Linder
  • Patent number: 10355796
    Abstract: A first mode (one-knob off mode) and a second mode (one-knob on mode) are provided as modes for setting parameters. In the first mode, individual elements corresponding to respective parameters of a parameter set are displayed in an operable state, allowing setting of individual parameters. In the second mode, the individual elements are displayed in a non-operable state, and one-element is displayed in an operable state, and a plurality of parameters of the parameter set are controlled by operating the one-element. At the time of switching from the first mode to the second mode, the parameter set is initialized.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: July 16, 2019
    Assignee: YAMAHA CORPORATION
    Inventors: Tomohiro Yamamoto, Shunichi Kamiya, Kotaro Terada, Masato Suzuki
  • Patent number: 10340987
    Abstract: Methods, apparatuses, and systems that receive a communication signal. The communication signal may be split into a first communication signal and a second communication signal. The first communication signal may be zero padded. The zero padded first communication signal may be excursion compensated to generate an excursion compensated signal. The excursion compensating may be performed by fast Fourier transform logic. Zero padding may allow for efficient fast Fourier transform process by ensuring that the length of data frames processed is an integer power of two.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 2, 2019
    Assignee: CCIP, LLC
    Inventor: Ronald Duane McCallister
  • Patent number: 10236827
    Abstract: A method may include, in an apparatus comprising a closed loop amplifier and a signal processing block configured to generate an amplifier input signal as a function of an upstream signal received at an input of the signal processing block, in a calibration mode of the apparatus: decoupling a second stage input of the amplifier from a first stage output of the amplifier; determining an offset signal that when applied to the input of a signal processing block as the upstream signal generates approximately zero as an intermediate signal generated by the first stage of the amplifier; and controlling one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: March 19, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: Lei Zhu, Ku He, Xin Zhao, Miao Song, Saurabh Singh, Vinod Jayakumar
  • Patent number: 10225118
    Abstract: A carrier leakage correction method for a quadrature modulator according to an embodiment includes inputting a test signal with a frequency fBB to a transmitter and up-converting the test signal with a frequency fL0 and down-converting with the frequency fL0. A frequency 2fBB component is detected in the down-converted test signal. One or a plurality of parameters of the transmitter is/are adjusted so as to reduce a magnitude of the detected frequency 2fBB component in the test signal.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: March 5, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yousuke Hagiwara, Shigehito Saigusa, Mitsuyuki Ashida, Yuki Fujimura, Ichiro Seto
  • Patent number: 10079702
    Abstract: Examples of front-end modules, apparatuses and methods for coupling compensation in a closed-loop digital pre-distortion (DPD) system are described. The closed-loop DPD circuit may include a PA and a loopback path. The PA may receive a PA input signal and amplify the PA input signal to provide a PA output signal proportional to a product of the PA input signal and a gain of the PA. The loopback path may receive the PA output signal to output a loopback signal. A forward coupling and a backward coupling may exist between the PA input signal and an output of the loopback path. The output of the loopback path may be proportional to a product of the PA output signal and a gain of the loopback path. The loopback path may include a coupling cancellation mechanism configured to cancel couplings between the PA input signal and the loopback signal.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 18, 2018
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: YuenHui Chee, Fei Song, James Wang, Toru Matsuura, Osama K. A. Shana'a, Chiyuan Lu
  • Patent number: 10050608
    Abstract: A phase modulation (PM) noise reducer to reduce phase modulation noise of an oscillator, the PM noise reducer including: an amplitude modulation (AM) detector to receive a primary oscillator signal and to produce an AM detector signal based on the primary oscillator signal, the primary oscillator signal including a first phase modulation (PM) noise; a control circuit in electrical communication with the AM detector to receive the AM detector signal and to produce a control signal; a phase shifter in electrical communication with the control circuit to receive the primary oscillator signal and the control signal and to produce a secondary oscillator signal based on the primary oscillator signal and the control signal, the secondary oscillator signal comprising a second PM noise, wherein the second PM noise is less than the first PM noise.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: August 14, 2018
    Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventors: Archita Hati, Craig Nelson, David Howe
  • Patent number: 10008283
    Abstract: A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first transistor, a current source connected to the source electrode of the first transistor, and a resistive element and a second switch connected in parallel between a drain electrode of the first transistor and a predetermined voltage. The resistive element may include a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor, or may include multiple transistor banks connected in parallel, each including a second transistor biased to operate in a linear region according to a gate control signal at a gate electrode of the second transistor. The gate control signal may originate from a circuit including a state machine.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: June 26, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Noam Eshel, Amit Sokolover, Golan Zeituni
  • Patent number: 9948484
    Abstract: The present invention relates to a method and an apparatus for direct current offset calibration of a direct conversion receiver, a Direct Current (DC) offset calibration apparatus of a direct conversion receiver includes a plurality of variable gain amplifiers for amplifying an input signal based on a gain control value, a DC offset monitoring unit for monitoring a DC offset for an output signal of the plurality of variable gain amplifiers, a plurality of variable Digital to Analog Converters (DACs) for controlling a current applied to each of the plurality of variable gain amplifiers according to a current control code, and a DC offset cancellation unit for determining a current control code set which minimizes the DC offset value per preset gain control value, and thus the DC offset can be precisely cancelled without being affected by external factors such as a signal modulation method and heat and performance degradation of the receiver can be prevented.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: April 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yi-Ju Roh, Ji-Hoon Kim, Ju-Ho Son, Yun-A Shim, Dong-Hyun Lee, Dong-Yun Jung, Sung-Tae Choi, Seung-Pyo Hong
  • Patent number: 9859856
    Abstract: An apparatus is provided which comprises: a differential input amplifying stage including a current source and a first node; a first matched pair of transistors coupled to the first node, wherein one of the transistors of the first matched pair is coupled to an output node of a driving stage; a second matched pair of transistors coupled to a second node to bias the second matched pair of transistors, wherein one of the transistors of the second matched pair of transistors is coupled to the output node of the driving stage, and wherein the second node is to be charged according to a first bias of the current source; and a resistive device coupled to the first and second nodes.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 2, 2018
    Assignee: Intel IP Corporation
    Inventor: John G. Kauffman
  • Patent number: 9749172
    Abstract: A method for calibrating mismatches of an in-phase signal path and a quadrature signal path of a receiver is proposed in the present invention, including: utilizing the receiver to receive at least one test signal with a specific frequency via the first signal path and the second signal path, to generate a first signal path received signal and a second signal path received signal; performing frequency analysis upon the first signal path received signal and the second signal path received signal respectively, to generate a first frequency analysis result and a second frequency analysis result; and calculating at least one calibration coefficient according to the first frequency analysis result and the second frequency analysis result. A method for calibrating mismatches of an in-phase signal path and a quadrature signal path of a transmitter is also proposed in the present invention.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 29, 2017
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yuan-Shuo Chang, Ching-Chia Cheng
  • Patent number: 9714781
    Abstract: According to the present disclosure, in a container refrigeration apparatus configured to cool the inside of a container, the accuracy of determination of occurrence of a lock abnormality and a connection abnormality of a motor is increased, and erroneous detection of the motor abnormalities is reduced or prevented. The container refrigeration apparatus of the present disclosure includes an abnormality determinator configured to compare a value for current flowing through an in-compartment motor with a preset current threshold to determine occurrence of the motor abnormalities of the in-compartment motor, and a threshold changer configured to change the current threshold of the abnormality determinator in accordance with a supply voltage for each supply frequency of a power supply configured to supply power to the in-compartment motor.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: July 25, 2017
    Assignee: Daikin Industries, Ltd.
    Inventors: Akitoshi Ueno, Kiichirou Satou, Masataka Nakano
  • Patent number: 9698739
    Abstract: Aspects of this disclosure relate to systems and methods of performing dynamic impedance tuning. Certain aspects may be performed by or include a dynamic impedance matching network. The dynamic impedance matching network can determine a desired output power for a power amplifier, true power information for the power amplifier, and an output power delivered to a load by the power amplifier. In addition, the dynamic impedance matching network can determine whether the output power satisfies the true power information. Responsive to this determination, the dynamic impedance matching network may modify a load line impedance for the power amplifier using an impedance tuning network.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 4, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: James Phillip Young, Joel Anthony Penticoff
  • Patent number: 9654156
    Abstract: A nonlinear compensating apparatus and method, a transmitter and a communication system are provided. The apparatus includes a preprocessor configured to preprocess a transmitted signal according to a pre-obtained preprocessing coefficient and a predistorter configured to perform predistortion for the preprocessed signal, and a result of comparison of a characteristic parameter of the signal that has been preprocessed and then predistorted with that of the transmitted signal satisfies a predetermined condition. By preprocessing the transmitted signal at the transmitter end, the embodiments of the present disclosure may perform efficient nonlinear compensation only needing to measure at the transmitter end and without needing to perform many times of measurement at the receiver end, and may lower complexity of circuits of the communication system and complexity of calculation.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: May 16, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Bo Liu, Weizhen Yan, Lei Li
  • Patent number: 9614489
    Abstract: The invention provides one sound producing system including a speaker, a driving circuit and an audio controller. The speaker is used for producing an audible sound. The driving circuit is connected to the speaker. The audio controller is configured to receive an input audio signal and pre-amplify the input audio signal with an amplify gain to obtain a pre-amplified audio signal; operate a multiband dynamic range control on the pre-amplified audio signal to obtain an output audio signal; convert the output audio signal to a driving voltage; provide the driving voltage to the speaker through the driving circuit; detect over the driving circuit to obtain at least one excursion parameter to determine an estimated excursion of the speaker in response to the driving voltage; and adjust the amplify gain according to the estimated excursion.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 4, 2017
    Assignee: HTC Corporation
    Inventors: Chih-Chiang Cheng, Chun-Min Lee, Hann-Shi Tong
  • Patent number: 9608713
    Abstract: The present disclosure relates to an interference cancellation method and device of an ICS repeater using a leveler, and may effectively cancel only interference signals by using a leveler without using a magnetic correlation cancellation device or digital filter in order to cancel unnecessary noise signals generated by narrow-band signals and enable an ICS repeater design for an LTE wireless network that needs a short system time delay.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: March 28, 2017
    Assignee: RF WINDOW CO., LTD.
    Inventors: Yong Seok Oh, Young Cheol Jeon, Kyoung Soo Park
  • Patent number: 9588859
    Abstract: A detecting circuit includes: a testing signal generator, arranged to selectively generate a testing signal having a first signal edge or a second signal edge to a connecting port; and a detector, arranged to detect a first detect signal on the connecting port after the testing signal having the first signal edge is coupled to the connecting port, and to detect a second detect signal on the connecting port after the testing signal having the second signal edge is coupled to the connecting port; wherein the detector is further arranged to determine if an external circuit element is coupled between the connecting port and a reference voltage according to the first detect signal and the second detect signal.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 7, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chien-Hua Wu, Kuan-Hua Chao
  • Patent number: 9564046
    Abstract: A method and/or computer program product receives inputs from a wearable input device. A communication session is established between a wearable input device and a receiving hardware device. The receiving hardware device receives an input from the wearable input device that is generated in response to a conformational change to a shape of the wearable input device, wherein the conformational change is applied to a random section of the wearable input device. The receiving hardware device thereafter initiates a responsive action that is associated with the input from the wearable input device, wherein the responsive action occurs within the receiving hardware device.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ilse M. Breedvelt-Schouten, Jana H. Jenkins, Jeffrey A. Kusnitz, James L. Lentz
  • Patent number: 9525385
    Abstract: Limiting clipping in an amplifier is accomplished in the feedback loop of a class D PWM amplifier that includes an integrator coupled to an input node and configured to generate an integrated input signal such that a comparator may then generate a PWM signal for driving an amplifier output stage based on a comparison to a triangle wave signal. To this end, the amplifier also includes a threshold signal generator for generating high and low voltage thresholds based on the triangle wave signal to be used to engage compensation circuits for limiting the overall amplification. Such compensation circuits may be bipolar junction transistors that are disposed in the feedback loop of the integrator. Thus, the overall bandwidth of the amplifier itself is not affected by adding a limiter circuit aimed at reducing clipping.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 20, 2016
    Assignee: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD
    Inventor: Hong Wu Lin
  • Patent number: 9503031
    Abstract: The invention provides an auto configuration method for an operational amplifier in an electronic system. The method includes steps of estimating an internal resistance of the electronic system; estimating an operation frequency of the electronic system; and determining a control parameter to adjust a characteristic of the operational amplifier according to the internal resistance and the operation frequency.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: November 22, 2016
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Sheng-Cheng Lee, Herming Chiueh
  • Patent number: 9467224
    Abstract: A method and a device for determining an input optical power are provided. The method include: after determining a bias current value of an optical amplifier unit when the optical amplifier unit amplifies a target optical signal and a voltage value output after an optical receiving unit converts the amplified target optical signal into an electrical signal, determining, according to a predetermined first correspondence that is among a bias current value, a voltage value, and an input optical power value and corresponds to a wavelength of the target optical signal, an input optical power value corresponding to the determined bias current value and the determined voltage value. By using the solution in the embodiments of the present invention, an input optical power of an optical signal on which optical amplification is performed can be determined.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: October 11, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Ming Qi
  • Patent number: 9407246
    Abstract: A phase modulation (PM) noise reducer includes: an amplitude modulation (AM) detector to receive a primary oscillator signal and to produce an AM detector signal, the primary oscillator signal including a first PM noise; and a control circuit to receive the AM detector signal, to produce a control signal, and to communicate the control signal to a phase shifter, wherein the phase shifter receives the primary oscillator signal and control signal, and the oscillator produces a secondary oscillator signal that includes a second PM noise that is less than the first PM noise, and further including; a PM detector and power splitter receives the primary oscillator signal, splits a power of the primary oscillator signal, and communicates the primary oscillator signal to the AM detector and PM detector.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: August 2, 2016
    Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventors: Archita Hati, Craig Nelson, David Howe
  • Patent number: 9405220
    Abstract: An optical sensor configured to irradiate an object area with light and receive reflected light, amplify a voltage in accordance with the reflected light by an amplifier circuit and a resulting voltage, the optical sensor comprising a recording medium recorded with information indicating a noise component calculated, based on characteristics of an input voltage and an output voltage of the amplifier circuit.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: August 2, 2016
    Assignee: OMRON CORPORATION
    Inventors: Yoshitaka Taishi, Hajime Kawai, Junichi Yoshida
  • Patent number: 9385664
    Abstract: A digital pre-distortion system which can provide the flexibility to model the highly non-linear distortion associated with High Efficiency RF Power Amplifiers while through a novel implementation of a least squares estimation process allows an implementation well suited for an FPGA application where limited resources and in particular memory resources are available.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: July 5, 2016
    Assignee: ACEAXIS NETWORK TECHNOLOGY LTD
    Inventors: Philip Brown, Jeremy Segar, John Ibison, Frank Friedman, Stephen Cooper