With Amplifier Condition Indicating Or Testing Means Patents (Class 330/2)
  • Patent number: 7202737
    Abstract: The present invention relates to a method of influencing an input signal (x), in particular an input signal of a power amplifier of a wireless communication system, wherein said input signal (x) has a range of input amplitudes (r0, . . . , rM?1), wherein a correction signal (?(x)) depending on said input signal (x) is generated, and wherein said input signal (x) is influenced depending on said correction signal (?(x)). A generation of said correction signal (?(x)) is based on a plurality of base functions (?1, ?2, . . . , ?N?1), and said range of input amplitudes (r0, . . . , rM?1) is divided into intervals (r0,r1),(r1,r2), . . . ,(rM?2,rM?1), wherein each of said base functions (?1, ?2, . . . , ?N?1) contributes to said correction signal (?(x)) in a limited number of intervals ((r0,r1),(r1,r2), . . . ,(rM?2,rM?1)). Thus it is possible to change parts of the correction signal by adapting some of said base functions without influencing the whole correction signal.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: April 10, 2007
    Assignee: Alcatel
    Inventors: Jörg Schaepperle, Gabriele Schwoerer, Thomas Bohn
  • Patent number: 7200369
    Abstract: A linear amplification with nonlinear components (LINC) power transmitter is provided. The LINC power transmitter includes a digital signal processing unit which controls the LINC power transmitter; a frequency modulation unit which modulates or converts a digital signal output from the digital signal processing unit into a radio-frequency (RF) signal; a signal amplification unit which amplifies the RF signal output from the frequency modulation unit using a gain amplifier and a power amplification module; and a direct current/direct current (DC/DC) conversion unit which controls bias of the power amplification module. Here, the DC/DC conversion unit controls a base bias and/or a collect bias of the power amplification module, and the power amplification module operates in saturation.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: April 3, 2007
    Assignee: Postech Foundation
    Inventors: Bumman Kim, Youngoo Yang, Young Yun Woo, Jae Hyok Yi, Seung Woo Kim
  • Patent number: 7193461
    Abstract: A pre-distorter that compensates for amplitude and phase distortion created by an amplifier. During a training session, the amplifier is stimulated with input signals of pre-selected amplitude and phase at various temperatures and the amplifier output is captured and converted into data sets. Polynomials are then fitted to the data sets and inverses of the polynomials are determined. The coefficients of the inverse polynomials are then saved for each temperature. During operation, the amplifier temperature is predicted based on the amplifier input signal and the coefficients associated with the predicted temperature are selected to be applied to the input signal to compensate for amplitude and phase distortion caused by the amplifier.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: March 20, 2007
    Assignee: Agere Systems Inc.
    Inventors: Mohammad Shafiul Mobin, Jeffrey H. Saunders, Lane A. Smith
  • Patent number: 7161418
    Abstract: An amplifier arrangement is disclosed that includes at least two series-connected, programmable amplifiers. The amplifiers each have a different amplifier step size. In addition, a calibration path is provided which feeds back the output of the second programmable amplifier to the programming inputs of the first and/or second programmable amplifier. The calibration path includes an analog/digital converter and an evaluation and control element. It is thus possible to calibrate away less-than-ideal characteristics, particularly in the case of changes in the gain from one amplifier block to another. The proposed amplifier arrangement and the method for calibration are particularly suitable for use in transmission and reception paths in transceivers which operate continuously over time.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: January 9, 2007
    Assignee: Infineon Technologies AG
    Inventor: Zdravko Boos
  • Patent number: 7154329
    Abstract: An amplifier circuit includes a calibration circuit with a controllable circuit element such as a digital resistor. One or more properties of the controllable circuit element (e.g., the resistance in a digital resistor) is varied by a digital calibration word such that the voltage drop across the resistor matches a reference voltage. The calibration word is also used to control the resistance of a transistor that forms a part of a power amplifier to compensate for temperature and process variations. The amplifier may be a switching power amplifier, and the transistor may be a segmented transistor with the width (and hence the channel resistance) controlled by the digital calibration word.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: December 26, 2006
    Assignee: M/A-COM, Inc.
    Inventor: Dale Scott Douglas
  • Patent number: 7151403
    Abstract: Feedback for self-calibration of any parameter in an analog and/or digital system is described wherein a system quality factor can be represented by a voltage or current differential. The preferred embodiment is operative to alternately supply two or more optimally equivalent currents or voltages from such a system, detect amplitude and/or phase feedback of resultant output signal at the frequency of the alternation, and use feedback to modify a calibration value, voltage, or current so as to minimize or maximize the feedback, thus effecting self-calibration of the system. Such a method and attendant apparatus enables system self-calibration without need of any high-precision or high-cost components.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: December 19, 2006
    Assignee: Jam Technologies, Inc.
    Inventor: Larry Kirn
  • Patent number: 7138858
    Abstract: A buffer circuitry buffers a radio-frequency (RF) signal. The buffer circuitry includes a complementary pair of switches and a power source. The a complementary pair of switches has an input terminal and output terminal. The input terminal of the complementary pair of switches responds to the RF signal. The output terminal of the complementary pair of switches couples to an output of the buffer circuitry. The power source includes a capacitor coupled to a current source. The power source couples to the complementary pair of switches. The power source supplies power to the complementary pair of switches in a manner that the buffer circuitry supplies a substantially constant power level at its output.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: November 21, 2006
    Assignee: Silicon Laboratories, Inc.
    Inventors: Augusto M. Marques, Donald A. Kerth, Richard T. Behrens, Jeffrey W. Scott, G. Diwakar Vishakhadatta, G. Tyson Tuttle, Vishnu S. Srinivasan
  • Patent number: 7135916
    Abstract: A digitally adjustable amplifier with adjustable input offset voltage and amplification parameters for use in integrated circuits. Such adjustments are carried out by a binary counter which controls a non-binary weighting element which by a non-binary weighting of each stage to the next stage intentionally has a non-linearity of the ideal characteristic curve because of greater negative steps at increasing value count so that the steps remain below one least significant bit. Thus greater errors even can be tolerated, and a desired value can be very closely attained.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: November 14, 2006
    Inventor: Albrecht Schmidt
  • Patent number: 7126413
    Abstract: A method and related circuit structure correlate the transconductance value of transistors of different type, for example MOS transistors and bipolar transistors. The structure comprises a first differential cell formed by transistors of the first type and a second differential cell formed by transistors of the second type connected to each other by means of a circuit portion responsible for calculating an error signal obtained as difference between the cell differential currents and applied to said first differential cell and to an output node of the same circuit structure obtaining a transconductance correlation independent from process tolerances and temperature.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 24, 2006
    Assignee: Simicroelectronics, S.R.L.
    Inventors: Pietro Filoramo, Giovanni Calì
  • Patent number: 7119611
    Abstract: On-chip calibrated source termination for voltage mode driver. An amplifier is disclosed having an internal amplifier with a first output and a second output, the first output interfaced to a non-inverting input through an interface. The second output is coupled to the first output through a series resistance element. The output impedance of the amplifier is determined by the ratio of the current drive of the first and second outputs. The voltage on said second output being a function of said interface and the current input to said internal amplifier.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: October 10, 2006
    Assignee: Vitesse Semiconductor Corporation
    Inventors: Eric James Wyers, Dan Stiurca, John James Paulos
  • Patent number: 7116167
    Abstract: A predistortion linearizer may include a digital signal processor (DSP) for modeling a nonlinear characteristic of a high power amplifier (HPA) on a real time basis; a distortion signal generator for generating a distortion signal by using the signal modeled by the DSP; and a main path unit for combining the output signal of the HPA and the distortion signal of the distortion signal generator and transmitting an input signal without a distortion component. Since the nonlinear characteristic of the power amplifier is modeled on a real time basis to remove the distortion component contained in the output signal of the power amplifier, the nonlinear characteristic of the power amplifier is improved, and thus, an efficiency of the power amplifier can be maximized.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: October 3, 2006
    Assignee: LG Electronics Inc.
    Inventor: Kwang-Eun Ahn
  • Patent number: 7091779
    Abstract: In the present invention a completely different approach for modeling of non-linear devices or processes is used. A cascade of blocks each depending on a non-linearity parameter are utilized both in non-linear modeling and a pre-distorter design. The new non-linear model description can be used for characterization of a non-linear system or for linearizing a non-linear system. Application to a Communications System Multi-carrier Amplifier is shown as an application example. Also for other application areas of the new mathematical method is feasible echo-canceling, non-linear communications channels etc. Parameter extractions and tables for the new model do not give multiple dimensional mathematical solutions for parameter extractions as in prior art.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: August 15, 2006
    Assignee: Telefonatiebolaget LM Ericsson (publ)
    Inventor: Karl-Gosta Sahlman
  • Patent number: 7088173
    Abstract: A method for tuning phase relationships for a multi-port amplifier. The method includes providing a plurality of amplifiers arranged in a multi-port configuration, which has more than two amplifiers. The method includes selecting one of a plurality of test patterns to be input into one or more of the plurality of amplifiers to detect phase information of one or more of the amplifiers and detecting an output signal at a designated output coupled to the plurality of amplifiers. The method also includes adjusting a phase relation of the one or more amplifiers based upon the output signal.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: August 8, 2006
    Assignee: Lockheed Martin Corporation
    Inventors: Novellone Rozario, Herbert Joseph Wolkstein
  • Patent number: 7084703
    Abstract: An amplifier linearizer includes a signal adjuster having an internal signal, and an adaptation controller for monitoring the signal adjuster. The internal signal at an input to the adaptation controller is deemed a monitor signal. The adaptation controller generates a control signal for the signal adjuster by accounting for a difference between the internal and monitor signals.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: August 1, 2006
    Assignee: Andrew Corporation
    Inventors: James K. Cavers, Thomas Johnson
  • Patent number: 7081791
    Abstract: A low noise amplifier circuit (10) includes an attenuator (12) for receiving a calibration signal and generating an attenuated calibration signal. A low noise amplifier (14) amplifies the attenuated calibration signal in calibration mode or amplifies a functional signal in functional mode. In calibration mode, a envelope detector/comparator (16) compares the calibration signal with the output of the low noise amplifier and generates a compensation signal indicating a deviation between the two signals. The gain of the low noise amplifier is adjusted responsive to the compensation signal.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: July 25, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Lorenzo M. Carpineto, Eric Duvivier, Stefano Cipriani
  • Patent number: 7079818
    Abstract: A programmable multi-stage amplifier includes a 1st programmable amplifier, a 2nd programmable amplifier, and a control module. The 1st and 2nd programmable amplifiers are coupled in series to amplify an input signal. Each of the 1st and 2nd programmable amplifiers is operably coupled to receive independent gain control signals from the control module. The control module generates the gain control signals by determining the overall gain desired for the programmable multi-stage amplifier and a corresponding gain for each of the 1st and 2nd programmable amplifiers. The factors in which the control module makes this determination are based on an optimization of at least one of the power level of the programmable multi-stage amplifier, the noise factor for the programmable multi-stage amplifier, and/or linearity of the programmable multi-stage amplifier.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: July 18, 2006
    Assignee: Broadcom Corporation
    Inventor: Shahla Khorram
  • Patent number: 7071782
    Abstract: A device for amplifying or attenuating HF signals is characterized in that a transistor is connected in a common-emitter configuration in amplifying operation, and a base-collector diode is connected in the forward-biased direction for attenuating operation.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: July 4, 2006
    Assignee: NEC Electronics (Europe) GmbH
    Inventor: Ulrich Delpy
  • Patent number: 7026866
    Abstract: Techniques for DC offset cancellation are described. According to one embodiment, an amplifier has at least one output and first and second supply rails. The amplifier includes offset cancellation logic which is operable in a calibration mode to generate a first offset cancellation signal when the at least one output is coupled to a first voltage corresponding to the first supply rail, and a second offset cancellation signal when the at least one output is coupled to a second voltage corresponding to the second supply rail. The offset cancellation logic is further operable to facilitate at least partial cancellation of an offset voltage associated with the at least one output during a normal operation mode using a third offset cancellation signal which substantially corresponds to an average of the first and second offset cancellation signals.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: April 11, 2006
    Assignee: Tripath Technology, Inc.
    Inventor: William D. Llewellyn
  • Patent number: 7026865
    Abstract: An analogue amplifier with multiplexing capability, without the need to incorporate a multiplexor, comprising an input port, a test input port, an output port, a control input to switch the amplifier between a normal amplifying mode and a test mode, wherein a analogue signal introduced to the input port is amplified to the output port in normal mode, and a test signal on the test port is routed to the output port when the amplifier is in test mode.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: April 11, 2006
    Assignee: Infineon Technologies AG
    Inventor: Javier Arguelles
  • Patent number: 7015760
    Abstract: A method of operating an amplifier, for example, in a wireless radio transceiver, including monitoring a characteristic of the amplifier during an operating interval of the amplifier, for example, during a transmission burst, providing an open-loop control signal to the amplifier during a subsequent operating interval of the amplifier wherein the open-loop control signal based on the characteristic monitored during a previous operating interval. In one embodiment, the corrected control signals are stored in a look-up table (510) that is updated based on the changes in load impedance.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: March 21, 2006
    Assignee: Motorola, Inc.
    Inventors: Lazaar J. Louis, Matt C. Hayek
  • Patent number: 7005918
    Abstract: A current-to-voltage converting apparatus connected to an element or a circuit having a first terminal connected to a signal source and comprising a feedback amplifier, which is connected to a second terminal of the element or the circuit and keeps the second terminal at virtual ground, and which converts the current signals that flow to the element or the circuit to voltage signals and outputs these signals; a device for opening the feedback loop of the feedback amplifier and measuring the open-loop loss of the feedback loop; and a compensating amplifier, which compensates for the open-loop loss. It further comprises a device for measuring the open-loop phase shift of the feedback loop when the feedback loop is open and a control unit for keeping the open-loop phase shift at a pre-determined value.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: February 28, 2006
    Assignee: Agilent Technologies, Inc.
    Inventor: Yukoh Iwasaki
  • Patent number: 6998909
    Abstract: Methods and apparatus are provided for nonlinear compensation of a supposedly linear behaving semiconductor device (e.g., power amplifier). A measure corresponding to the temperature of the silicon in the semiconductor device can be derived from both current and previous inputs using a filter (e.g., infinite impulse response or finite impulse response). This measure can then be used as an index, or address, of a lookup table. The lookup table is continually updated through a feedback loop where the updated lookup table values (e.g., correction factors) are based on the differences between the desired output signals and the measured output signals. A lookup table value, when combined with an input signal, will distort the input signal in an amount that is substantially an inverse of the distortion introduced by the semiconductor device. As a result, an output signal that is in substantial linear relationship with the input signal can be achieved.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: February 14, 2006
    Assignee: Altera Corporation
    Inventor: Volker Mauer
  • Patent number: 6956430
    Abstract: A distortion detector comprises a clip detector to generate a distortion pulse, processing means to calculate the duty cycle of the distortion pulse and comparator means for supplying a control signal when the calculated duty cycle exceeds a certain threshold value. This control signal can be used, for example, the reduce the volume of audio reproduction.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: October 18, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Gerrit Frederik Magdalena De Poortere
  • Patent number: 6949976
    Abstract: A distortion compensating amplifier device is disclosed that maintains uniform delay amounts between a transmission input signal and a transmission output signal, even if there is a change in the device characteristics. The distortion compensating amplifier device of a digital predistortion type includes a second delay circuit that delays the transmission input signal; a distortion compensating circuit that performs predistortion compensation on the delayed signal, using a distortion compensating parameter; an amplifier that amplifies the signal subjected to the predistortion compensation; a first delay circuit that further delays the signal delayed by the second delay circuit; and a calculator that calculates the distortion compensating parameter to be used in the predistortion compensation, based on the difference between the signal output from the first delay circuit and the amplified signal.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: September 27, 2005
    Assignee: Fujitsu Limited
    Inventors: Yasuhito Funyu, Takao Sasaki, Hiromi Miyamoto, Takeshi Ohba
  • Patent number: 6927624
    Abstract: A method and circuit is provided for improving the control of the trimming procedure for various devices without the need for additional dedicated control pins. Instead, the trimming procedure is controlled through sensing of changes in current and/or voltage applied through the existing available pins or bondpads of the devices to determine whether a command for trim programming has occurred. As a result, package-level trimming of the devices can be conducted in standard device packages having low pin count configurations, such as operational amplifiers, instrumentation amplifiers, difference amplifiers, low drop-out regulators, voltage references and other similar types of devices. A device to be trimmed is configured with internal circuitry configured to sense changes in current and/or voltage in the output or supply voltage of the device, and a test system for applying changes in the current and/or voltage through the existing available pins or bondpads of the devices.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: August 9, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Vadim V. Ivanov, Stephen J. Sanchez, David M. Jones, David Spady
  • Patent number: 6924699
    Abstract: Apparatus, methods and articles of manufacture are disclosed for digital signal modification. Various wave characteristics of an electromagnetic wave may be modified according to desired values. Those values are provided to one or more current sources, wherein the output values of the current sources are modified accordingly.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: August 2, 2005
    Assignee: M/A-Com, Inc.
    Inventor: Walid K. M. Ahmed
  • Patent number: 6914943
    Abstract: A phase signal is modulated in quadrature modulation by a quadrature modulator, and the frequency of this modulated phase signal is converted into carrier frequency by a frequency converter. An amplitude signal extracted from the modulating signal is delayed by a delay circuit, and an output gain signal designating the output average power gain is supplied to the output signal of the delay circuit. Synchronization of this frequency modulated phase signal and the amplitude signal delayed and added to the output gain signal allows to obtain an RF signal with little out of band undesired component even if the modulating signal contains amplitude variation. Therefore, the RF signal with little out of band undesired component is output even if the modulating signal contains amplitude variation.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: July 5, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroaki Shimizu
  • Patent number: 6903604
    Abstract: Disclosed is an apparatus and method for modeling and estimating the characteristics of a power amplifier with memory. A predistortion module generates a predistorted signal in response to coefficients of a complex polynomial representative of the amplifier and to an input signal. A power amplifier receives time-spaced samples of the predistorted signal and generates an output signal. A polynomial module updates the coefficients of the complex polynomial in response to a current sample of the output signal and to the time-spaced samples of the predistorted signal. In particular, the complex polynomial is implemented with both even and odd terms.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: June 7, 2005
    Assignee: Lucent Technologies Inc.
    Inventor: Jaehyeong Kim
  • Patent number: 6882217
    Abstract: The present invention includes methods and devices to apply predistortion to correct nonlinearities of a power amplifier in an OFDM symbol transmission system. More particularly, predistortion is patterned to take into account clipping of symbols and to match an effective input range of the predistorter with an average power output of the power amplifier. This invention may be applied to a variety of standards utilizing OFDM technology, including IEEE 802.11a, Hiperlan/2 and MMAC.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: April 19, 2005
    Assignee: 3com Corporation
    Inventor: A. Joseph Mueller
  • Publication number: 20040263242
    Abstract: A composite amplifier includes a first and a second power amplifier (16, 18) connected to a Chireix output network (20). Means (10, 22) provide equal first and linear drive signal components that depends linearly on the amplitude A(t) of an amplitude modulated input signal. Further means (10, 24)provide first and second nonlinear drive signal components that have the same magnitude but opposite signs and depend non-linearly as {square root}1-A(t) on the amplitude A(t) and are in quadrature to the first and second linear drive signal components. Means (26, 28, 30, 32) individually adjust amplitudes and phases of the drive signal components to lower drive power consumption.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 30, 2004
    Inventor: Richard Hellberg
  • Publication number: 20040251959
    Abstract: A method and circuit is provided for improving the control of the trimming procedure for various devices without the need for additional dedicated control pins. Instead, the trimming procedure is controlled through sensing of changes in current and/or voltage applied through the existing available pins or bondpads of the devices to determine whether a command for trim programming has occurred. As a result, package-level trimming of the devices can be conducted in standard device packages having low pin count configurations, such as operational amplifiers, instrumentation amplifiers, difference amplifiers, low drop-out regulators, voltage references and other similar types of devices. A device to be trimmed is configured with internal circuitry configured to sense changes in current and/or voltage in the output or supply voltage of the device, and a test system for applying changes in the current and/or voltage through the existing available pins or bondpads of the devices.
    Type: Application
    Filed: June 12, 2003
    Publication date: December 16, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Vadim V. Ivanov, Stephen J. Sanchez, David M. Jones, David Spady
  • Publication number: 20040246048
    Abstract: The invention provides robust and non-invasive calibration of an adaptive signal conditioning system having a signal conditioning block in the signal path to a signal conversion system, and a feedback path with a number of feedback components for enabling adaptation, by means of a parameter adaptation block, of the parameters used in the signal conditioning. In order to calibrate the feedback path, a well-defined reference signal is inserted into the feedback path, and an appropriate calibration coefficient is then determined by a coefficient calibrator in response to the received reference signal. The calibration coefficient is provided to a compensator, which effectively compensates for changes in the transfer characteristics of the feedback path due to factors such as variations in ambient temperature and component aging.
    Type: Application
    Filed: February 26, 2004
    Publication date: December 9, 2004
    Inventors: Scott Leyonhjelm, Vimar Bjork, John Grass, Lennart Neovius, Paul Leather
  • Patent number: 6812792
    Abstract: A method and apparatus are disclosed for predistorting an input signal to a non-linear amplifier. An appropriate precorrection is determined for the input signal over a series of iterative stages according to an amplifier model. The amplifier model includes a limiting function that clips the input signal to reduce error due to amplifier saturation. The determined precorrection is then applied to the input signal.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: November 2, 2004
    Assignee: Harris Corporation
    Inventors: Anders S. Mattsson, Carlos Abascal, Wayne Duello, David Danielssons
  • Publication number: 20040201416
    Abstract: On-chip calibrated source termination for voltage mode driver. An amplifier is disclosed having an internal amplifier with a first output and a second output, the first output interfaced to a non-inverting input through an interface. The second output is coupled to the first output through a series resistance element. The output impedance of the amplifier is determined by the ratio of the current drive of the first and second outputs. The voltage on said second output being a function of said interface and the current input to said internal amplifier.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 14, 2004
    Inventors: Eric James Wyers, Dan Stiurea, John James Paulos
  • Patent number: 6794936
    Abstract: A predistortion system compensates or equalizes the phase and/or amplitude response over frequency of at least a portion of a signal path prior to the distortion generating circuitry, such as an amplifier, and/or of at least a portion of a feedback path after the distortion generating circuitry. For example, in a power amplification system using predistortion, an equalizer on the signal path adjusts the phase and amplitude of a predistorted signal across frequency to compensate for the amplitude and phase response of circuitry on the signal path, such as the amplitude and phase response of analog filters in the up-conversion process. After amplification, an equalizer on a feedback path adjusts the phase and amplitude across frequency of the signal representing the output of the amplifier to compensate for the amplitude and phase response of circuitry, such as analog filters in the down-conversion process, on the feedback path.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: September 21, 2004
    Assignee: Lucent Technologies Inc.
    Inventors: Liang Hsu, Jaehyeong Kim, Kyriaki Konstantinou
  • Publication number: 20040150469
    Abstract: Analogue amplifier with multiplexing capability comprising an input port (2) for receiving an analogue signal (S); a test input port (3) for receiving a test signal (T); an output port (5); a control input (4) for receiving a test control signal (CRTL-mode) switching the amplifier (1) between a normal amplifying mode and a test mode; wherein in the normal amplifying mode the analogue signal (S) is amplified and transmitted via said output port (5); wherein in the test mode the test signal (T) is routed to said output port (5).
    Type: Application
    Filed: January 21, 2004
    Publication date: August 5, 2004
    Applicant: Infineon Technologies AG
    Inventor: Javier Arguelles
  • Patent number: 6768434
    Abstract: A high speed x/sine(x) correction circuit for a digital to analog converter (DAC) functions by implementing a filter with an impulse response that approximates a sine(x)/x response. Each digital data value of an input signal to be converted by the DAC is considered a separate impulse. Each impulse, or initial pulse, is used to create a first reflection pulse by delaying the initial pulse by one clock cycle, inverting the delayed initial pulse and multiplying the delayed initial pulse by a constant less than one, such as dividing the delayed initial pulse by right-shifting the digital data value of the delayed initial pulse. The first reflection pulse is added to the input signal in the clock cycle it is generated prior to input to the DAC. A second reflection pulse may be generated in like manner from the first reflection pulse with an additional clock cycle delay for optimum results, both reflection pulses being added to the input signal in the clock cycle they are generated prior to input to the DAC.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: July 27, 2004
    Assignee: Tektronix, Inc.
    Inventor: Linley F. Gumm
  • Patent number: 6756924
    Abstract: A signal processing apparatus for correcting DC offset in a communication system is provided.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: June 29, 2004
    Assignee: Integrant Technologies Inc.
    Inventors: Junghwan Lee, Bo-Eun Kim, Jinkyu Lim, Minsu Jeong, Bonkee Kim
  • Patent number: 6750663
    Abstract: The present invention provides for a method (30) and system (10) for isolating the input nodes (3, 4) and/or the output nodes (5, 8) of an analog device (12) and performing continuity testing thereof without using relays. The system includes an analog device having a pair of input and output terminals and a plurality of resistors (R1-R3 and R4-R6) arranged in parallel and connected thereto. The method for testing continuity of the analog device includes providing a voltage input via at least one of the resistors to either input node, and then measuring the voltage at the same node via a resistor. If a diode drop from ground is sensed there is continuity, and if the applied voltage is sensed at the node there is not continuity. As a result, the invention advantageously isolates the nodes and removes any unwanted capacitance and impedance loading thereon during testing thereof.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: June 15, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Gunvant Patel
  • Patent number: 6744310
    Abstract: A power amplifying device promptly detects an abnormal condition of a load and permits protection of an output without causing power loss. A test signal having a predetermined frequency and signal level is supplied to an amplifier, and the output level is measured. The measured level is compared with the output level that is projected when the test signal is supplied with an appropriate load connected to the amplifier so as to detect a load condition. If a determination result indicates that the load is short-circuited or released, then the operation of the amplifier is promptly interrupted.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: June 1, 2004
    Assignee: Pioneer Corporation
    Inventor: Jun Honda
  • Patent number: 6737919
    Abstract: A method and apparatus for calibrating a Gm cell using a Gm replica cell. A digital to analog converter receives a Gm setting code and generates a reference current. The Gm replica cell adjusts the tuning voltage until the difference between a pair of drain currents is substantially equal to the reference current. Where this condition is satisfied, the proper tuning voltage has been acquired. This results in proper calibration for the tuning voltage, which then may be utilized by a Gm cell connected with the Gm replica cell.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: May 18, 2004
    Assignee: Infineon Technologies North America Corp.
    Inventor: Sasan Cyrusian
  • Patent number: 6737913
    Abstract: A common mode feedback circuit includes first and second nodes defining a differential node pair. A collective plurality of transconductors includes a first plurality of transconductors associated with the first node and a second plurality of transconductors associated with the second node. Each plurality, for example, may consist of 2 transconductors such that one may be serve as a common mode current sink and the other may be operated as a current source during calibration. At least one transconductor of the collective plurality has an adjustable transconductance. In various embodiments, each node has at least one transconductor with an adjustable transconductance. The common mode feedback circuit includes a calibration engine. The calibration engine adjusts at least one adjustable transconductor until a sensed differential voltage across the differential node pair is substantially zero without the use of external current sources.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: May 18, 2004
    Assignee: Silicon Laboratories, Inc.
    Inventor: Marius Goldenberg
  • Patent number: 6737914
    Abstract: A method for removing effects of gain and phase mismatch in amplification branches of a linear amplification using nonlinear components (LINC) system. The method includes receiving an input signal, calculating a relative phase and gain difference in the amplification branches, and generating phasing components. The input signal is then controllably separated into a plurality of branch signals of different but constant envelope. The mismatch between branches may cause each branch signal to have a different envelop. The phases of the branch signals are then appropriately adjusted in a certain amount of corresponding phasing components, such that when the branch signals are recombined, the combined signal substantially replicates the input signal.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: May 18, 2004
    Assignee: 4D Connect, Inc.
    Inventor: Jian Gu
  • Patent number: 6734731
    Abstract: An amplifier linearizer includes a signal adjuster having an internal signal, and an adaptation controller for monitoring the signal adjuster. The internal signal at an input to the adaptation controller is deemed a monitor signal. The adaptation controller generates a control signal for the signal adjuster by accounting for a difference between the internal and monitor signals.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: May 11, 2004
    Assignee: Simon Fraser University
    Inventors: James K. Cavers, Thomas Johnson
  • Patent number: 6731161
    Abstract: An integrated device having a transimpedance amplifier (TIA) cascaded with a limiter can be tested such that the frequency response of the TIA is accurately measured. The frequency response of the TIA is derived from the measured output jitter response of the integrated TIA/limiter device. In a practical testing system, a sinusoidal test signal having a constant amplitude is combined with a broadband noise signal having a constant power level to obtain a noisy test signal. The TIA/limiter is driven by the noisy test signal while the frequency of the test signal is varied. The output jitter of the TIA/limiter is measured for a number of frequency settings to obtain the output jitter response.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: May 4, 2004
    Assignee: Applied Micro Circuits Corporation
    Inventor: Mark O'Leary
  • Patent number: 6727747
    Abstract: Three kinds of shrink factors, 1 time, 0.5 time, and 0.25 time, are prepared and three sets of operational amplifier layout information are also prepared as a library in correspondence with the three kinds of shrink factors. At each shrink factor, the bias voltage is varied between upper and lower limits to vary the bias current.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: April 27, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kuniyuki Tani, Atsushi Wada
  • Patent number: 6724248
    Abstract: A differential amplifier includes first and second outputs and first and second supply rails. The differential amplifier further includes offset cancellation circuitry. The offset cancellation circuitry is operable during a calibration mode to generate an offset cancellation signal when the first and second outputs are both coupled to a voltage between the first supply rail and the second supply rail. The offset cancellation signal is for facilitating at least partial cancellation of an offset voltage associated with the first and second outputs during a normal operation mode of the differential amplifier.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: April 20, 2004
    Assignee: Tripath Technology, Inc.
    Inventor: William D. Llewellyn
  • Publication number: 20040027195
    Abstract: A digitally adjustable amplifier with adjustable input offset voltage and amplification parameters for use in integrated circuits. Such adjustments are carried out by a binary counter which controls a non-binary weighting element which by a non-binary weighting of each stage to the next stage intentionally has a non-linearity of the ideal characteristic curve because of greater negative steps at increasing value count so that the steps remain below one least significant bit. Thus greater errors even can be tolerated, and a desired value can be very closely attained.
    Type: Application
    Filed: August 7, 2003
    Publication date: February 12, 2004
    Inventor: Albrecht Schmidt
  • Patent number: 6657492
    Abstract: In a method for estimating a non-linear characteristic of an amplifier, an input signal is provided, a reference signal is determined based on the power of the input signal, the input signal is amplified using said amplifier in order to produce an amplified signal, a measurement signal is determined based on the power of the amplified signal and respective samples of the measurement signal are associated with respective samples of the reference signal. A gain value of said amplifier for each sample is determined from the respective samples of the reference signal and the measurement signal. An operating range of the amplifier is divided into a plurality of power sections and an averaged gain value is produced for each power section. Thereafter, a measure of the deviation of the gain values associated with a power section from said averaged gain value is determined. Then, averaged gain values are rejected which have a measure of the deviation which exceeds a predetermined threshold.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: December 2, 2003
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Rainer Perthold, Heinz Gerhauser, Gerald Ulbricht
  • Patent number: 6642784
    Abstract: A power amplifier module includes an input for receiving a signal having an input power level, at least one power amplifier coupled to the input to increase the input power level of the signal to an output power level and a power calibration and control module coupled to the power amplifier for measuring the output power level and correcting the output power level measurement based on a set of factors. The power calibration and control module further controls the at least one power amplifier to produce an output power level equivalent to a target power level. The power calibration and control module may include a power detector, a power calibrator and a power controller. The power amplifier module may further include a power set interface coupled to the power calibration and control module for providing the target power level.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: November 4, 2003
    Assignee: Analog Devices, Inc.
    Inventor: Robert J. McMorrow