Abstract: A semiconductor integrated circuit device includes: a substrate which has a first conductivity type and in which a first amplifier area and a second amplifier area are defined; a first well which has a second conductivity type, a first pocket well which has the first conductivity type and is separated from the first well, and a first deep well which has the second conductivity type, surrounds the first pocket well, and is separated from the first well; and a second well which has the second conductivity type, a second pocket well which has the first conductivity type and is separated from the second well, and a second deep well which has the second conductivity type, surrounds the second pocket well, and is separated from the second well The first well, the first pocket well, and the first deep well are formed in the first amplifier area of the substrate, and the second well, the second pocket well, and the second deep well are formed in the second amplifier area of the substrate.

Abstract: A generator for use with an electrosurgical device is provided. The generator has a gain stage electrically disposed between a first voltage rail and a second voltage rail, wherein the gain stage includes an input and an output. A voltage source operably coupled to the gain stage input and configured to provide an input signal thereto responsive to a drive control signal is also provided. The generator also has one or more sensors configured to sense an operational parameter of the amplifier and to provide a sensor signal corresponding thereto and a controller adapted to receive the sensor signal(s) and in response thereto provide a drive control signal to the voltage source.

Abstract: An amplifier circuit includes a modulation signal generating circuit, a driving stage circuit and an output stage circuit. The modulation signal generating circuit generates a pair of modulation signals according to a pair of differential input signals and a plurality of clock signals. The driving stage circuit generates a pair of driving signals according to the pair of modulation signals. The output stage circuit generates a pair of amplified output signals according to the pair of driving signals.

Abstract: Because of input of a digital signal, PWM-input, separately excited, class-D amplifier systems are less prone to be affected by noise than in the conventional case that an analog signal is input. Since a ramp wave that is synchronized with a PWM signal is used as a comparison clock, no beats occur between a PWM clock and a reference clock, making is possible to provide a class-D amplifier system which exhibits a large S/N ratio. Furthermore, the fact that an external clock can be varied provides another advantage that no beat noise occurs even in a set that is disposed close to a radio receiver.

Abstract: A switching amplifier with an embedded harmonic rejection filter is disclosed. In an exemplary design, the switching amplifier includes a generator circuit and a plurality of output circuits. The generator circuit receives an input signal and a carrier signal at a carrier frequency and generates a plurality of versions of a drive signal associated with different delays. The drive signal may be a pulse width modulation (PWM) signal. The plurality of versions of the drive signal may be generated by delaying the carrier signal, or the input signal, or the drive signal. The output circuits receive the plurality of versions of the drive signal and provide an output signal. The output circuits have outputs that are coupled together and implement a finite impulse response (FIR) filter based on the plurality of versions of the drive signal. The FIR filter has a frequency response with zeros at harmonics of the carrier frequency.

Abstract: A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (Vcc) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits.

Abstract: A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd1) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd1). The driver circuit may include a cascode stage (M3) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd2) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M5, M6) to couple a control terminal of an active load transistor (M9) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).

Abstract: A multi-input differential amplifying device of the present invention includes: a differential amplifier having an inverting input terminal and a non-inverting input terminal; and an input portion configured to apply a first input voltage to a first input terminal that is one of the inverting input terminal and the non-inverting input terminal and apply a second input voltage to a second input terminal that is the other input terminal, the first input voltage corresponding to first input signals that are a plurality of input signals for the first input terminal, the second input voltage corresponding to a second input signal that is one input signal for the second input terminal. The input portion is configured to correct an offset voltage between the first input voltage and the second input voltage.

Abstract: An audio system includes a speaker and a class D amplifier with a class-D PWM (pulse width modulation) modulator configured for generating first and second PWM signals, each with three differential output levels. The class-D amplifier also has a differential output driver configured for driving a first and a second output signals onto a first and a second output terminals in response to the first and the second PWM signals, wherein each of the first and the second output signals has three differential output levels. An inverse common-mode signal generator is coupled to first and second output signals for providing an inverse common-mode signal. The audio system also includes one or more output terminals for providing the inverse common mode signal, and further includes a wire or a trace on a PCB (printed circuit board) inverse common mode signal.

Abstract: A class D power amplifier is provided. The class D power amplifier includes a class D driver circuit having a plurality of output transistors, at least one active clamp circuit coupled to at least one output transistor of the plurality of output transistors, and at least one filter bank circuit coupled to the at least one active clamp circuit for controlling a voltage of the at least one output transistor. Accordingly, a voltage across a drain node and source node (VDS), a voltage across a gate node and source node (VGS), and a voltage across the gate node and drain node (VGD) of the output transistors is reduced to increase reliability of the power amplifier while consuming less power and utilizing less die area.

Abstract: The present invention relates to a voltage variable type digital audio amplifying device for noise compensation and a method therefore, and more specifically, varies the power according to an audio input signal, and compensates for the noise generated when varying the power, thereby enhancing audio output efficiency and easily removing noise.

Abstract: An amplifier includes first and second stages. The first stage includes an input node for receiving an analog input signal, an analog digital converter for converting the analog input signal to a digital input signal, and a first switching circuit for outputting a first analog intermediate output signal in response to receiving a digital pulse width modulated signal that is based on the digital input signal. The second stage is configured to receive a pulse width modulation quantization error of the first stage, scale the pulse width modulation quantization error of the first stage by a gain factor to produce a scaled pulse width modulation quantization error of the first stage, and output a second analog intermediate output signal based on the scaled pulse width modulation quantization error of the first stage. A summation circuit combines the first and second analog intermediate output signals to generate an amplified output signal.

Abstract: A method of adjusting the frequency or phase of operation of a Class-D amplifier is disclosed. The method comprises making a series of step changes in the frequency or phase to adjust the frequency or phase from a start value to a desired end value, each step change in frequency or phase causing a corresponding disturbance of an output of the Class-D amplifier to produce a series of disturbances, each of which varies from an initial magnitude in first and second senses to exhibit a first peak and then in the first sense to exhibit a second peak. The time between the step changes is selected so that the second peak of each disturbance other than a final disturbance in the series overlaps the first peak of an immediately succeeding disturbance.

Abstract: In an aspect of the disclosure, a class D power amplifier with an overcurrent protection (OCP) circuit is provided. The class D power amplifier includes a plurality of output transistors, and the OCP circuit is mirrored to at least one output transistor of the plurality of output transistors in a closed-loop feedback configuration for precisely controlling a sensing current of the OCP circuit with respect to an output current of the at least one output transistor. The class D power amplifier with the OCP circuit in the closed-loop feedback configuration mitigates a variation in a current threshold value for triggering interruption of the class D power amplifier.

Abstract: A power amplification apparatus that performs an inverse fast Fourier transformation on data allocated to a plurality of sub-carriers, converts time-domain data output in parallel from the inverse fast Fourier transformation into a time-domain analog signal, performs a power amplification on the time-domain analog signal, wherein a saturation output level of the power amplification is adjustable in accordance with a switching signal. The power amplification apparatus also compares an amplitude of a signal in each time slot of the time-domain analog signal with a predetermined threshold and switches the saturation output level of the power amplification based on an output of the comparing.

Abstract: A class D audio amplifier having: an audio control circuit configured to provide a switching signal based on an input signal and a reference signal; an input capacitor coupled between the input signal and the first input terminal of the audio control circuit; an inductor having a first terminal coupled to the switching terminal of the audio control circuit, and a second terminal; an output capacitor having a first terminal coupled to second terminal of the inductor and a second terminal coupled to a load; and a noise suppression circuit having a first terminal coupled to the first input terminal of the audio control circuit, and a second terminal coupled to the switching terminal of the audio control circuit, wherein the noise suppression circuit charges the input capacitor and the output capacitor to reach a preset value.

Abstract: A pulse width modulation (PWM) amplifier includes a first amplifier stage, a second amplifier stage, and a gain module. The first amplifier stage is configured to amplify an analog input signal in the analog and digital domains using a first pulse width modulation (PWM) generator, to provide a first stage output for coupling to a load. The gain module is configured to amplify a quantization error of the first PWM generator by a predetermined gain. The second amplifier stage is configured to spectrally shape and attenuate the amplified quantization error of the first PWM generator using a second PWM generator, to provide a second stage output for coupling to the load.

Abstract: A 3-level class D amplifier circuit comprises a first comparator for comparing an input with a first triangular reference and a second comparator for comparing the input with a second triangular reference. A phase relationship between the signals to the first comparator is 180 degrees shifted relative to a phase relationship between the signals to the second comparator. An amplifier stage generates a three-level PWM output signal using the outputs of the first and second comparators. A shared feedback path is used from the three-level PWM output signal.

Abstract: An audio power amplifier includes a first and a second amplification unit, each including a switching voltage amplifier, an output filter, a current compensator, an inner current feedback loop feeding a measurement of current measured at the output inductor back to a summing input of the current compensator, a voltage compensator coupled to the summing input of the current compensator, and an outer voltage feedback loop. A controlled signal path provides the output of the voltage compensator of the first amplification unit to the current compensator of the second amplification unit. The first and second amplification units are operable with separate loads, in parallel driving a common load, or across a bridge-tied-load. A second pair of amplification units may be added and operated together with the first pair to drive a single speaker with a parallel pair of amplifiers on each side of a bridge-tied-load.

Abstract: System and method for amplifying an input signal to generate an output signal. The system includes a current generator, an oscillator, and a comparator. The current generator is configured to receive a first voltage signal, and generate a first current signal based on at least information associated with the first voltage signal and the first reference signal. The oscillator is configured to receive at least the first current signal and a second reference signal, and to generate a second voltage signal based on at least information associated with the first current signal and the second reference signal, the second voltage signal being associated with a modulation frequency. Additionally, the comparator is configured to receive the second voltage signal and a third voltage signal, and to generate a modulation signal related to the modulation frequency based on at least information associated with the second voltage signal and the third voltage signal.

Abstract: An audio amplifier system may include an audio CODEC/output (AOP) path featuring analog class-D amplifiers, and using Natural Sampling Pulse Width Modulation (PWM) to convert an analog input into a series of Rail-to-Rail pulses. The audio signal may be encoded in the average value of the PWM pulse train and may be recovered from the PWM signal by analog low pass filtering. The Class-D amplifiers may be designed with a negative feedback loop/network to compare the output signal with the input signal and suppress non-idealities introduced by the Class-D switching stage. Furthermore, operation of the AOP may be designed according to a separate signal transfer function and a separate noise transfer function, and 2nd order noise shaping may be performed at low power, with an optimized filter included in the feedback loop to achieve the best noise reduction at low power.

Abstract: A method of operating a switched-mode power supply (SMPS) for supplying power to a load circuit, which draws a supply current that varies with an input signal to the load circuit is disclosed. The method comprises monitoring the input signal and controlling the amount of accumulated energy transferred for consumption by the load circuit, in use, in accordance with the input signal.

Abstract: The present application describes an apparatus and method for reducing distortion in a class-D amplifier. The power output section of the amplifier is driven by an adjusted PWM signal, rather than by a PWM signal created directly from the input analog signal. A reference output, designed to closely track the input analog signal, is compared to the amplifier output. The resulting difference is an error signal which is inverted and summed with a second analog signal corresponding to the directly created PWM signal and changes the timing of the voltage transitions of the second analog signal. The changed voltage transitions are used to create the adjusted PWM signal. The inversion of the error signal causes negative feedback which results in the adjustment of the PWM signal being in a direction which reduces the error signal and thus the distortion of the amplifier.

Abstract: Output circuits using pulse width modulation (PWM) and/or pulse density modulation (PDM) are described. In one aspect, a PWM output circuit includes a PWM modulator that operates based on a square wave signal instead of a sawtooth or triangular wave signal. In another aspect, a PDM output circuit includes a PDM modulator that uses variable reference voltages to reduce variations in switching frequency. In yet another aspect, a dual-mode output circuit supports both PWM and PDM and includes a pulse modulator and a class D amplifier. The pulse modulator performs PWM on an input signal if a PWM mode is selected and performs PDM on the input signal if a PDM mode is selected. The class D amplifier receives a driver signal from the pulse modulator and generates an output signal.

Abstract: A method is provided. A first enable signal is asserted so as to enable a first driver, where the first driver has a first output and a first parasitic capacitance. A second enable signal is asserted so as to enable a second driver, where the second driver has a second output and a second parasitic capacitance. The first and second outputs are coupled together by a switching network when the second driver is enabled. Pulses from complementary first and second radio frequency (RF) signals are applied to the first driver, where there is a first set of free-fly intervals between consecutive pulses from the first and second RF signals, and pulses from complementary third and fourth RF signals are applied to the second driver, wherein there is a second set of free-fly interval between consecutive pulses from the third and fourth RF signals.

Abstract: An amplifier includes first and second stages. The first stage includes an input node for receiving an analog input signal, an analog digital converter for converting the analog input signal to a digital input signal, and a first switching circuit for outputting a first analog intermediate output signal in response to receiving a digital pulse width modulated signal that is based on the digital input signal. The second stage is configured to receive a pulse width modulation quantization error of the first stage, scale the pulse width modulation quantization error of the first stage by a gain factor to produce a scaled pulse width modulation quantization error of the first stage, and output a second analog intermediate output signal based on the scaled pulse width modulation quantization error of the first stage. A summation circuit combines the first and second analog intermediate output signals to generate an amplified output signal.

Abstract: A switching amplifying method or a switching amplifier for obtaining one or more linearly amplified replicas of an input signal, is highly efficient, and does not have the disadvantage of “dead time” problem related to the class D amplifiers. Said switching amplifier comprises: an inductance means; a switching unit for switching a current from a DC voltage to the inductance means; a switching power transmitting unit for blocking a current when the switching unit switches on, and conducting the current from the inductance means to a filter unit positively or negatively according to the polarity of the input signal when the current from the DC voltage to the inductance means is switched off; an amplifier control unit to control the switching unit and the switching power transmitting unit according to the input signal; said filter unit filtering the current from the switching power transmitting unit to get an output signal.

Abstract: An amplifier circuit includes an amplifier unit that is configured to receive an input signal and generate a switching output signal. A level shifter is configured to shift the amplitude of the input signal to have a shifted amplitude that is proportional to a peak-to-peak amplitude of the switching output signal.

Abstract: Apparatus and method for switching audio amplification. In an embodiment, an apparatus for switching audio amplification includes an output circuit. The output circuit is coupled to a plurality of different voltage potentials and a first voltage potential, and outputs an output signal to drive a load, wherein each of the different voltage potentials is greater than the first voltage potential. In an exemplary embodiment, a control circuit controls the output circuit to generate the output signal based on one of the different voltage potentials and first voltage potential selectively so as to enable the output signal to switch between any two adjacent corresponding voltage levels of the different voltage potentials and the first voltage potential.

Abstract: The present disclosure generally relates to the field of digital Class-D amplifiers and more specifically to a technique for reducing output waveforms distortion of a digital class-D amplifier implementing a ternary modulation scheme.

Abstract: Provided is a hybrid envelope amplifier having improved efficiency, and more particularly, to an envelope amplifier using a dual switching amplifier and having improved efficiency in which power consumption is reduced by controlling a switching current of a switching region according to a magnitude of an envelope input signal, thereby improving efficiency compared to a conventional hybrid envelope amplifier. The envelope amplifier using a dual switching amplifier and having improved efficiency comprises a linear amplifier and a switching amplifier, wherein the switching amplifier includes two or more switching stages that are selectively operated according to a magnitude of an input signal.

Abstract: A circuit for providing audio signals to a load such as a speaker is provided that uses the speaker or headphone amplifier structure as a current to voltage converter, thereby eliminating a separate current to voltage converter from the circuit. Such a design removes one of the elements that creates noise in the circuit architecture and improves the dynamic range for the audio signal. For example, the output of a digital to analog converter is a single ended output provided to the speaker or headphone amplifier. The digital to analog converter can include a series of current sources that are summed up to provide the single ended output. Where the current sources have positive and negative current source mismatch, a feedback mechanism is employed to correct for the mismatch and reduce introduction of harmonic noise into the signal through the digital to analog converter.

Abstract: A method is provided. A first enable signal is asserted so as to enable a first driver, where the first driver has a first output and a first parasitic capacitance. A second enable signal is asserted so as to enable a second driver, where the second driver has a second output and a second parasitic capacitance. The first and second outputs are coupled together by a switching network when the second driver is enabled. Pulses from complementary first and second radio frequency (RF) signals are applied to the first driver, where there is a first set of free-fly intervals between consecutive pulses from the first and second RF signals, and pulses from complementary third and fourth RF signals are applied to the second driver, wherein there is a second set of free-fly interval between consecutive pulses from the third and fourth RF signals.

Abstract: Techniques are disclosed relating to charging and discharging gates of transistors. In one embodiment, an apparatus includes first and second drivers. The first driver is configured to discharge a gate of a first transistor, and to send a charge indication to the second driver in response to reaching a Miller plateau for the first transistor. The second driver is configured to charge a gate of a second transistor above a threshold voltage in response to receiving the charge indication. In some embodiments, the second driver is configured to begin charging the gate of the second transistor to a voltage below the threshold voltage when the first driver begins discharging the gate of the first transistor begins, and to wait to charge the gate of the second transistor above the threshold voltage until the charge indication has been received.

Abstract: A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (Vcc) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits.

Abstract: A class-D amplifier circuit includes an amplifier that generates pulse-width modulated output signals according to input signals which have phases reverse to each other and are supplied to a first input end and a second input end, a first transistor interposed between a first input path extending from the first input end to the amplifier and a second input path extending from the second input end to the amplifier, and a voltage applying circuit that applies a control voltage corresponding to a predetermined value to a control terminal of the first transistor so that a current flowing between both ends of the first transistor increases in accordance with increase of levels of the input signals within a range in which the levels of the input signals are higher than the predetermined value.

Abstract: An integrated circuit comprising a Class-D amplifier for amplifying an input signal at an input terminal is disclosed. The Class-D amplifier is switchable between an operational mode, in which a comparator (4) is directly coupled to an output stage (5), and a test mode, in which the comparator (4) is coupled to the output stage (5) via a sampler (15) and the output stage (5) is coupled to the input terminal via a feedback network, whereby a digital representation of the input signal is available at an output of the sampler (15).

Abstract: A power amplifier circuit uses an output transistor and a cascode transistor. First and second drive circuits apply gate control signals to the two transistors, which rise and fall in synchronism, and this is such that the voltage drop across the cascode transistor is reduced (compared to a constant gate voltage being applied to the output transistor).

Abstract: An apparatus and method for communications are disclosed. The apparatus may include an a quantizer having three levels, and a switching power amplifier configured to drive a load having first and second terminals, wherein the switching power amplifier is further configured to switch the first and second terminals between first and second power rails only if the output from the quantizer is at one of the three levels.

Abstract: Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier.

Abstract: An enhanced radio frequency transmitter suitable for use in a nuclear magnetic resonance logging tool, may employ a power amplifier that comprises two pairs of switching amplifiers and a summation stage. The first pair of switching amplifiers together generate a first pair of pulse sequences having an adjustable phase difference, while the second pair of switching amplifiers generate a second pair of pulse sequences, each pulse sequence in the second pair being provided a fixed phase offset from a respective pulse sequence in the first pair. The summation stage forms a combined signal from the pulse sequences in both said first and second pairs. The fixed phase offset operates to at least partly cancel a higher harmonic of the pulse sequences from the combined signal, thereby reducing energy losses downstream from the transmitter.

Abstract: A high efficiency amplifier system may include multiple output stages cooperatively operating to produce an amplified output signal. The amplifier system may be used in an audio system. The amplifier system may include a non-switchmode amplifier stage cooperatively operating with a switchmode amplifier stage to generate the amplifier output signal. The non-switchmode amplifier stage may selectively enable and disable the switchmode amplifier stage to optimize efficient operation. In addition, the switchmode amplifier stage may include multiple switching stages operated with interleave. The switching stages may be controlled to balance current output of the respective switching stages based on a measured current flow in at least one of the switching stages.

Abstract: A switching amplifier includes first and second output terminals that may be connected to a load. A pulse-width modulator receiving an input signal to obtain respective positive and negative values of the input signal. The modulator is connected to first and second switching circuits. The first switching circuit applies a plurality of pulses to the first output terminal that, in response to the positive samples, have a constant frequency and are pulse-width modulated, and, in response to the negative samples, have a varying frequency and a constant width. Similarly, the second switching circuit applies a plurality of pulses to the second output terminal that, in response to the negative samples, have a constant frequency and are pulse-width modulated, and, in response to the positive samples, have a varying frequency and a constant width. The varying phase of the constant width pulses disperses RF interference across a wider spectrum.

Abstract: A power amplifier includes: a modulator pulse-modulating a drive waveform signal serving as a reference of a drive signal applied to an actuator and outputting a plurality of modulated signals; a digital power amplifier having a plurality of digital power amplifier stages each including a pair of push-pull switching elements, amplifying the power of the plurality of modulated signals, and outputting multi-value amplified digital signals; and a low pass filter smoothing the amplified digital signals and outputting the drive signal, wherein the modulator includes a control section switching one of a state where the same modulated signal is connected to two or more of the digital power amplifier stages and a state where different modulated signals are connected to different digital power amplifier stages to the other.

Abstract: The present invention is related to an improved power amplifier and a method for restraining power of the improved power amplifier. The improved power amplifier has an output power restraint unit, and the output power restraint unit is capable of restraining output power of the improved power amplifier when the output power is exceedingly large. A method for restraining power of a power amplifier, the method comprises the steps of: determining whether power of output powers signal are exceedingly large through a power signal transformation unit, if yes, adjusting two variable resistor of an input amplifier unit for adjusting the power of the power signals, and outputting the adjusted power signals for driving a load via output terminals of the power amplifier.

Abstract: A method of optimizing cross current in class D amplifiers and simultaneously minimizing the harmonic distortion is provided. The method overcomes the problem of using the limited speed voltage comparators often used in cross current preventing circuits. Method embodiments are based on introducing a replica amplifier with a current sensor matched to a main amplifier. The duration of a sensed cross current within the replica amplifier is compared by a current comparator with a small enough reference current. The comparator output generates a pulse with a duration equal to the duration of the cross current event in the replica amplifier. The duration of that pulse is measured and used to generate a dead time pulse for blanking amplifier pre-driver inputs.

Abstract: A Class-D amplifier arrangement is disclosed that implements an auxiliary feedback loop and a primary feedback loop. The auxiliary feedback loop operates upon an input signal when the Class-D amplifier arrangement is operating under a power-up condition and a power-down condition so that a modulated signal is confined within the auxiliary feedback loop during the power-up condition and the power-down condition. The confinement of the modulated signal within the auxiliary feedback loop during the power-up condition and the power-down condition diverts transient signals coupled onto the modulated signal from an output device. The primary feedback loop operates upon the input signal when the Class-D amplifier arrangement is operating under a normal condition so that the modulated signal is introduced to the output device during the normal condition.

Abstract: Disclosed is an amplifier circuit configured to amplify a pulse stream. The amplifier circuit comprises a switching block including a first switch operable to couple an output node of the switching block to a positive reference voltage, a second switch operable to couple the output node to a ground reference voltage and a third switch operable to couple the output node to a negative reference voltage. The amplifier circuit is configured to amplify the pulse stream into an amplified signal detectable at the output node such that the amplified signal has a common-mode voltage level substantially equal to zero volts. In one embodiment, the amplifier circuit is configured to amplify the pulse stream in accordance with a Class-D amplification scheme. In one embodiment, the output node can be directly connected to a load device without a DC blocking capacitor being interposed between the output node and the load device.

Abstract: There is provided an amplifying apparatus which can prevent characteristic deterioration while reducing costs. The amplifying apparatus includes a first amplifier connected between an input terminal to which a high-frequency signal is input and an output terminal through which the high-frequency signal is output, including a bipolar transistor, and amplifying the high-frequency signal input from the input terminal; a second amplifier including a bipolar transistor, amplifying the high-frequency signal input from the input terminal, and having a lower maximum output power than that of the first amplifier; and a switching unit connected between the second amplifier and the output terminal, and selectively outputting the high-frequency signal amplified by the second amplifier through the output terminal.

Abstract: A class-D amplifier includes a quantized amplifier, having no quantization error feedback circuit, coupled to receive a digital input signal, according to which an output signal is generated to be switched between power rails. The digital input signal is pre-compensated to correct an error. A low-pass filter is configured to operate on the output signal to generate a filtered output signal.