Abstract: A concurrent multi-band RF amplifying circuit may include: an input impedance matching unit performing impedance matching on each of first and second band signals included in an input signal input through one input terminal; an input amplifying unit including first and second band amplifying units each amplifying the first and second band signals input through the input impedance matching unit; a common ground circuit unit connected between a first common node commonly connected to the first and second band amplifying unit and a ground and including an impedance device for matching of an input impedance; and an output amplifying unit amplifying signals from each of the first and second band amplifying units.

Abstract: Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.

Abstract: Current sense amplifiers with extended input common mode (CM) voltage range, including an extended CM input voltage amplifier that includes a low voltage (LV) p-type metal oxide semiconductor (PMOS) input module coupled to a positive supply rail, wherein said supply rail provides a voltage that is the maximum between a positive input signal (IN+) applied to the amplifier and an internal power supply voltage. The amplifier further includes a voltage regulator coupled to the supply rail that generates a decreased voltage level relative to the supply rail voltage that is provided to the LV PMOS input module via a high voltage ground (HV_GND) line. At least part of the LV PMOS input module is powered by a voltage difference between the positive supply rail and the HV_GND line. The voltage regulator maintains said voltage difference within an operating range of LV devices within the LV PMOS input module.

Abstract: Aspects of the invention include a differential amplifier circuit with a differential amplifier operated with a first power supply voltage applied thereto to amplify a differential voltage between paired input voltages, an inverting amplifier operated with a second power supply voltage applied thereto to carry out inverting amplification of the output of the differential amplifier and output the amplified output to the outside, and a voltage step-up circuit producing the first power supply voltage higher than the second power supply voltage from the second power supply voltage and applying the produced first power supply voltage to the differential amplifier. This satisfies at one time the requirement for producing the high power supply voltage necessary for the differential amplifier and the requirement for securing the power supply current necessary for the inverting amplifier on the basis of the externally supplied second power supply voltage.

Abstract: Provided is a fully differential signal system including a first amplification unit including first and second output terminals configured to output an output differential signal generated based on an input differential signal and a common mode feedback signal; a common mode detection unit configured to detect a common mode signal included in the output differential signal; a second amplification unit including a feedback signal output terminal configured to output the common mode feedback signal generated based on the detected common mode signal and a reference signal; a first stabilization unit connected between the first output terminal and the feedback signal output terminal; and a second stabilization unit connected between the second output terminal and the feedback signal output terminal. The fully differential signal system stably operates and an operation performance of the fully differential signal system is improved.

Abstract: An electronic device includes an output terminal, an output transistor having a control terminal and a conduction terminal coupled to the output terminal, and a resistor-capacitor (RC) compensation network configured to act on the control terminal of the output transistor. In addition, the electronic device includes a transconductance amplifier configured to drive the output terminal through the control terminal of the output transistor, and a Miller effect stage coupled to the RC compensation network and having an input port coupled to the transconductance amplifier and an output port coupled to the control terminal of the output transistor.

Abstract: An amplifier receives a differential signal and, in response, generates a first negative input current and a first positive input current. In a first operating mode, the amplifier receives a second differential signal, and, in response, generates a second negative input current and a second positive input current. In a second operating mode, the amplifier receives the second differential signal, and, in response, generates a third negative input current and a third positive input current. When the device is operating in the first operating mode, the first negative input current is summed with the second negative input current and the first positive input current is summed with the second positive input current. When the device is operating in the second operating mode, the first negative input current is summed with the third negative input current and the first positive input current is summed with the third positive input current.

Abstract: The differential signals at the outputs of a differential amplifier quickly change in response to common mode changes in the output differential signals. The amplified input signals amplified by the differential amplifier quickly change in response to common mode changes in the differential signals input into the differential amplifier. A bias voltage input to the differential amplifier is isolated to remove low-frequency components from the bias voltage.

Abstract: A wide common-mode range receiver includes an input module, voltage level shift module, voltage level shift control module, and output module. The receiver can also include an equalizer. The receiver translates data originating from a circuit powered from an external voltage supply to a circuit powered by an internal voltage supply. The voltage level shift may be scaled based on differences between the voltage supplies or by determining the difference between an input common-mode voltage and a reference voltage, and driving a servo based on the difference.

Abstract: An apparatus is provided. The apparatus includes a calibration circuit configured to generate a reference signal and at least one differential circuit each being configured to operate at a calibrated transconductance over process or condition variations based on the reference signal. The calibration circuit may be configured to generate the reference signal independent of the at least one differential circuit. A method for operating at least one differential circuit is provided. The method includes generating a reference signal and operating the at least one differential circuit at a calibrated transconductance or gain over process or condition variations based on the reference signal. The reference signal may be generated independently of the at least one differential circuit.

Abstract: A sense amplifier measures a state of a memory cell coupled to a sense node. The sense amplifier receives a control signal to enable the sense amplifier. The sense amplifier generates a voltage based on an amplifier current that is based on a sense current flowing through the sense node. The sense amplifier generates a feedback current based on the voltage to compensate variations of the sense current. The sense amplifier receives a reference control signal to enable a reference circuit to generate a reference current. The sense amplifier provides an output based on a result of comparing the sense current with the reference current, the output representing the state of the memory cell.

Abstract: An operational amplifier comprises a first input pair, a second input pair, a switch and a first current mirror. The first input pair comprises a different type of MOS transistor from the second input pair. The switch determines which one of the first or the second input pair is functioning and the operating input pair is configured to output voltage. The switch is further connected to the first input pair and the first current mirror. The first current mirror is further connected to the second input pair, and is configured to copy a current passing through the switch to the second input pair. Therefore an increase of transconductance of the first input pair is compensated by a decrease of transconductance of the second input pair, and the operational amplifier has a substantially constant transconductance no matter which of the first input pair and the second input pair is functioning.

Abstract: A processing system for equalizing a data transfer. The processing system may include a trans-conductance generator that may obtain a first clock signal. The trans-conductance generator may generate a first bias signal using a first switched capacitor and the first clock signal. The first switched capacitor may charge according to the first clock signal. The processing system may further include a biasing circuit. The biasing circuit may obtain a second clock signal. The biasing circuit may generate a second bias signal using a second switched capacitor and the second clock signal. The second switched capacitor may charge according to the second clock signal. The processing system may further include a peaking amplifier. The peaking amplifier may generate an output signal using an input signal, the first bias signal, and the second bias signal.

Abstract: A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.

Abstract: A precision, high voltage, low power differential input stage including static and dynamic gate protection is disclosed herein. The differential input stage incorporates the performance of low voltage transistors with the high voltage capability of high voltage transistors. The transistors may be MOSFETs or the like. In addition, gate protection is provided to protect against large DC voltages and AC voltage transitions. The differential input stage includes a pair of input circuits, such as positive and negative input circuits, each including a cascode combination of low and high voltage transistors. In each cascode stage, the low voltage transistor is fabricated with a gate threshold voltage that is as high or higher than that of the high voltage transistors. The low voltage, high threshold transistors in the cascode stages may be configured to match each other. Resistors and capacitors may be provided to protect against excessive input current and voltage.

Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor may be coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor may be capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground. The second inductor may be embedded within the first inductor.

Abstract: An electronic device includes a transimpedance amplifier stage having an amplifier end stage of the class AB type and a preamplifier stage coupled between an output of a frequency transposition stage and an input of the amplifier end stage. A self-biased common-mode control stage is configured to bias the preamplifier stage. The preamplifier stage is formed by a differential amplifier with an active load that is biased in response to the self-biased common-mode control stage.

Abstract: Gain control in complementary common gate and common source amplifiers is disclosed. In an exemplary embodiment, an apparatus includes a first amplifier stage configured to amplify an input signal at an input terminal to generate a first amplified signal. The first amplifier stage includes a current diverter that selectively diverts current to set a gain of the first amplifier stage. The apparatus also includes a second amplifier stage configured to amplify the input signal at the input terminal to generate a second amplified signal. The second amplifier stage includes a gain control circuit to set a gain of the second amplifier stage.

Abstract: There are disclosed herein various implementations of a group III-V power conversion circuit including a monolithically integrated half bridge having a depletion mode III-Nitride field-effect transistor (FET), and a normally OFF composite cascoded switch including a depletion mode III-Nitride FET and an enhancement mode group IV FET. In one exemplary implementation, the monolithically integrated half bridge includes a high side depletion mode III-Nitride FET having an enable switch coupled in the conduction path of the high side depletion mode III-Nitride FET.

Abstract: Embodiments of the invention are generally directed driving data of multiple protocols through a single set of pins. An embodiment of an apparatus includes a transmitter connected to two pads on an IC the transmitter including a differential driver to transmit a differential signal, wherein the differential driver has a first branch and a second branch, each branch of the differential driver including a protection device connected to one of the pads; and a common mode driver to transmit a common mode signal, the common mode driver having a first branch and a second branch, each of the branches of the common mode driver including a protection device connected to one of the pads. The first and second switch devices are not turned on simultaneously, based on data to be transmitted, one of the switch devices being turned on and the other being turned off.

Abstract: In one embodiment, a circuit includes a differential amplifier having a differential pair with a first transistor and second transistor. Each of the first and the second transistors include a front gate contact and a back gate contact. A first digital feedback loop is coupled between an output of the differential amplifier to the back gate contact of the first transistor. A second digital feedback loop is coupled to the back gate contact of the second transistor. The first digital feedback loop is configured to be opposite in phase to the second digital feedback loop.

Abstract: A voltage converting device with a self-reference feature for an electronic system includes a differential current generating module, implemented in a Complementary metal-oxide-semiconductor (CMOS) processing for generating a differential current pair according to a converting voltage; and a voltage converting module, coupled to the differential current generating module, a first supply voltage and a second supply voltage of the electronic system for generating the converting voltage according to the differential current pair, the first supply voltage and the second supply voltage.

Abstract: An apparatus and method for a voltage reference circuit with improved precision. The voltage reference circuit utilizes threshold voltage difference between a pair of MOSFETs. A voltage reference circuit between a power supply node and a ground node and configured for generating a reference voltage, includes a first current mirror with a first NMOS transistor and a second NMOS transistor wherein said first NMOS transistor threshold voltage is not equal to said second NMOS transistor threshold voltage, a second current mirror with a first PMOS transistor, a second and third PMOS transistor configured to be coupled to said power supply node, a current source configured to be provide current to said second current mirror, an amplifier configured with a first and second input configured to be connected to the drains of said first NMOS transistor and said second NMOS transistor and, a feedback loop configured to be the output of said amplifier.

Abstract: In one embodiment, a circuit comprising a passive input network of an input impedance configured to couple an input voltage to a first circuit node; an adaptive current source configured to output an adaptive bias current to the first circuit node; a cascode device controlled by a control voltage and configured to receive a sum current from the first circuit node and output an output current to a second circuit node; and a load network of a load impedance configured to provide termination to the second circuit node, wherein the adaptive bias current is dynamically adapted to track a deterministic noise component in the input voltage.

Abstract: The present disclosure provides a buffer circuit comprising a plurality of operational amplifiers and a switch module. Each operational amplifier forms a buffer. The operational amplifier has an output stage. The stage has a first transistor and a second transistor. The first transistor and the second transistor are connected to an output terminal. The first transistor has a first control terminal. The second transistor has a second control terminal. The switch module is connected to the first control terminal of the first transistor and the second control terminal of the second transistor. The switch module connects together at least two of the first terminals of the first transistor according to a control signal. The switch module connects together at least two of the second terminals of the second transistor according to the control signal.

Abstract: The present invention discloses pre-amplifier with a selectable threshold voltage in a decision feedback equalization circuit to reduce tap weight variation. A decision feedback equalization circuit includes a summer circuit and a pre-amplifier with an offset generator, wherein the pre-amplifier includes a pair of differential amplifiers and each biased by a respective current bias and each having first and second output nodes coupled to a supply voltage via a respective resistive element, R. The resistive elements may be implemented, for example, using diode-configured transistors, biased transistors, resistor, or any other active or passive circuitry for establishing a resistance. The inputs of first differential amplifier are coupled to the summer's output. The inputs of second differential amplifier are coupled to a reference voltage circuit that comprised of a resistive element and a respective current DAC (IDAC).

Abstract: An amplification circuit includes an input portion, a first load portion, a second load portion, and a duty cycle adjustment portion. The input portion changes a voltage level of an output node, which outputs a voltage level thereof as an output signal, in response to an input signal. The first load portion and a second load portion are coupled to the output node. The duty cycle adjustment portion is coupled between the first load portion and the second load portion, and provides a correction current to the output node.

Abstract: An instrumentation amplifier includes: a first input stage configured to shift a level of a first input voltage applied to a first input terminal and to output the level-shifted voltage; a second input stage configured to shift a level of a second input voltage applied to a second input terminal and to output the level-shifted voltage; a first resistor configured to generate a differential current corresponding to a difference between the voltage output from the first input stage and the voltage output from the second input stage; a second resistor configured to convert the differential current into a first output voltage; a third resistor configured to convert the differential current into a second output voltage; a first output stage configured to output the first output voltage from a first output terminal; and a second output stage configured to output the second output voltage from a second output terminal.

Abstract: Improved sensing circuits for use in low power nanometer flash memory devices are disclosed.

Abstract: In certain embodiments, a circuit for image frequency rejection includes an analog adder-amplifier that has a transistor pair. The adder-amplifier is configured to receive a plurality of downmixed or upmixed in-phase and quadrature-phase signals, and to add an in-phase signal and a quadrature-phase signal applied at control inputs of both transistors of the transistor pair. Both transistors of the transistor pair are connectable to a same load resistor for addition of the in-phase signal and the quadrature-phase signal applied at the control inputs of both transistors. The adder-amplifier is configured to output, based on adding the in-phase signal and the quadrature-phase signal applied at the control inputs of both transistors of the transistor pair, one or more summed signals.

Abstract: To achieve low power consumption of a semiconductor device including a plurality of function blocks capable of being in either an operating state or a not-operating state, by effective use of electric charge discharged from a not-operating function block. In a semiconductor device including a plurality of function blocks, a capacitor is electrically connected to the plurality of function blocks so that electric charge discharged from a not-operating function block is accumulated in the capacitor. Then, the electric charge accumulated in the capacitor is supplied to a function block to be in an operating state, and then power is supplied from a power source to the function block.

Abstract: An automatically calibrated differential amplifier including: an input stage differential amplifier configured to receive a input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations. The differential amplifier may be included, for example, in a comparator and a multilevel receiver.

Abstract: In aspects of the invention, an operational amplifier circuit includes: an N-MOS auxiliary current source connected in parallel to the N-MOS differential pair, the N-MOS auxiliary current source turning ON when the N-MOS differential pair turns OFF caused by a decreased common mode input voltage given to the pair of voltage input terminals, drawing a current from the active load for the P-MOS differential pair. Aspects of the invention also include a P-MOS auxiliary current source connected in parallel to the P-MOS differential pair, the P-MOS auxiliary current source turning ON when the P-MOS differential pair turns OFF caused by an increased common mode input voltage given to the pair of voltage input terminals, delivering a current to the active load for the-N-MOS differential pair.

Abstract: A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.

Abstract: An amplifier is provided having a first mixed-length MOS device set for receiving an input signal and outputting an output signal, and a first load for providing termination for the output signal, wherein the first mixed-length MOS device set comprises a parallel connection of a plurality of MOS devices having different channel lengths including at least a short channel length MOS device and a long channel length MOS device. In one configuration, a threshold voltage of the short channel length MOS device is greater than a threshold voltage of the long channel length MOS device. A related method is also provided.

Abstract: A circuit for equalizing the impedances of a PMOS device with an NMOS device includes a first reference voltage coupled to the source of the first PMOS device. A second reference voltage is coupled to the source of the NMOS device. A first node has a common mode voltage between the first reference voltage and the second reference voltage. A second node is located between the PMOS device and the NMOS device. A first gate voltage is coupled to the gate of either the PMOS device or the NMOS device. An operational amplifier has a first input coupled to the first node and a second input coupled to the second node, the output of the operational amplifier is a second gate voltage that is coupled to the gate of one of either the PMOS device or the NMOS device that is not coupled to the first gate voltage.

Abstract: A device can include an operational amplifier (op amp) circuit having a differential transistor pair, a first transistor of the differential transistor pair being formed in a first well of a substrate and a second transistor of the differential transistor pair being formed in a second well of the substrate; a body bias generator configured to generate at least a first body bias voltage for the first well, and not the second well, that varies in response to a first body bias control value; and a control circuit configured to selectively generate the first body bias control value in response to an input offset voltage of the op amp.

Abstract: A voltage reference circuit includes three or more current mirrors, an operational amplifier, a voltage buffer, two or more diodes, and one or more resistors. The operational amplifier has two inputs separately coupled to an output of two of the three or more current mirrors and an output coupled to the three current mirrors. The voltage buffer has an input coupled to an output of the other one of the three or more current mirrors and another input coupled to an output of the voltage buffer. Each of the diodes is coupled between the output of the two of the three or more current mirrors and one of ground and a negative supply. The one or more resistors are coupled to an output of one or more of the three or more current mirrors to tune effects of input current and establish a first set absolute voltage and temperature coefficient on a voltage reference.

Abstract: An active inductor includes a first transistor, a capacitor, a second transistor, a first resistor, a second resistor, and a bias current source. A source terminal of the first transistor is a first terminal of the active inductor and connected to a first voltage source. The capacitor is connected to the source terminal and gate terminal of the first transistor. A drain terminal of the second transistor is connected to the source terminal of the first transistor. A gate terminal of the second transistor is connected to a drain terminal of the first transistor. The first resistor is connected between the drain terminal of the first transistor and a second terminal of the active inductor. The second resistor is connected to a source terminal of the second transistor. The bias current source is connected between the second resistor and a second voltage source.

Abstract: In one embodiment, a differential amplifier is provided. Gates of a first differential pair of transistors, of a first conductivity type, and a second pair or transistors, of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.

Abstract: A low noise amplifier for radio frequency integrated circuits having an adaptive input and operating mode selection. The low noise amplifier comprises two inputs which can be operated in different configurations. The operating mode may be chosen in such way that the inputs are used respectively one at the time for single-ended configuration or both inputs are used for differential configuration. Additionally, in single-ended operation, inputs can be matched to different frequencies. The information regarding the operating mode is obtained from an external component. The operating mode to be used may be determined when the device using a particular radio frequency integrated circuit is designed or it can be determined dynamically by the device using the radio frequency integrated circuit.

Abstract: An IF-noise-shaping transistorized current-mode lowpass filter is applied to quadrature in a balanced circuit. A first pair of transistors receiving current inputs from a mixer are connected so that each of the first pair of transistors has its gate cross coupled to the output of the other of the first pair of transistors. A second pair of transistors are connected in series with respected outputs of respective ones of the first pair of transistors and having gates connected to a first common voltage node, and a capacitance is used to connect the current inputs of one of the first and second pairs of transistors. An active inductive load is connected between the current inputs of one of the first and second pairs of transistors.

Abstract: A transmitter, comprises: a first branch for providing a positive output having a first set of serially-connected transistors; a second branch for providing a negative output having a second set of serially-connected transistors; and a biasing circuit, wherein the biasing circuit generates a first biasing voltage and a second biasing voltage as a function of the positive output, the negative output, and a predefined threshold voltage, and wherein the first biasing voltage, the second biasing voltage, and a differential input signal drive the first set of serially-connected transistors and the second set of serially-connected transistors.

Abstract: A circuit may include one or more transistors connected directly to an output, and a biasing network connected to at least one of a substrate, a well, and a back-gate of at least one of the transistors. The biasing network may bias the at least one of the substrate, the well, and the back-gate to a virtual floating bias, such that the virtual floating bias shifts in voltage level based upon an AC input signal of the circuit, to reduce the parasitic capacitance of the output node of the circuit.

Abstract: A high-frequency amplifier circuit includes a balanced-unbalanced converter converting a single-ended signal into differential signals. The output of a first amplifier amplifying the single-ended signal is connected to the signal terminal on the unbalanced side of the balanced-unbalanced converter. The input of a second amplifier amplifying one of the differential signals is connected to one signal terminal on the balanced side of the balanced-unbalanced converter. The input of a third amplifier amplifying another of the differential signals is connected to another signal terminal on the balanced side of the balanced-unbalanced converter. An impedance element is inserted between an element on the balanced side of the balanced-unbalanced converter and a ground.

Abstract: An amplification circuit including: an input for receiving an input voltage; an output for exhibiting an output voltage; a primary amplifier configured to receive the input voltage from the input, receive a primary control voltage, first amplify the input voltage by a primary gain dependent on the control voltage, the output voltage corresponding to the first amplified input voltage, and supply the output voltage to the output; and a secondary amplifier configured to receive the input voltage from the input, second amplify the input voltage by a secondary gain, the primary control voltage corresponding to the second amplified input voltage, and supply the primary control voltage to the primary amplifier. The secondary amplifier has in operation an input admittance of at least 1 millisiemens.

Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.

Abstract: A single-stage folded cascode buffer including an amplifier, a first analog comparator, a second analog comparator, a first transistor, and a second transistor, The amplifier includes a first input terminal, a second input terminal, and an output terminal coupled to the second input terminal of the amplifier. The first analog comparator includes a first input terminal, a second input terminal, and an output terminal. The second analog comparator includes a first input terminal, a second input terminal, and an output terminal. The first transistor includes a first terminal, a second terminal coupled to the output terminal of the first analog comparator, and a third terminal coupled to the output terminal of the amplifier. The second transistor includes a first terminal coupled to the output terminal of the amplifier, a second terminal coupled to the output terminal of the second analog comparator, and a third terminal.

Abstract: Disclosed is a differential power amplifier using mode injection, which includes: a first transistor of which the gate receives a first signal and the source is connected to the ground; a second transistor of which the gate receives a second signal and the source is connected to the ground; a third transistor of which the source is connected to the source of the first transistor; a fourth transistor of which the source is connected to the source of the second transistor; a fifth transistor of which the source is connected with the drain of the first transistor and the drain is connected with a first output port and the drain of the third transistor; and a sixth transistor of which the source is connected with the drain of the second transistor and the drain is connected with a second output port and the drain of the fourth transistor.

Abstract: A signal generation apparatus includes a digital-to-analog converter, a bias stage and a class AB output stage. The digital-to-analog converter is arranged for outputting a current as an input signal. The bias stage is coupled to the digital-to-analog converter, and is arranged for generating a bias signal according to at least the input signal. The class AB output stage is coupled to the bias stage, and is arranged for generating an output signal at an output node of the signal generation apparatus according to the bias signal, wherein the output signal includes a first signal component and a second signal component, both the first signal component and the second signal component correspond to the input signal, and there is a linear relation between the output signal and the input signal.