Including Differential Amplifier Patents (Class 330/252)
  • Patent number: 10797674
    Abstract: The present application provides an apparatus for processing signals of a high-voltage loop, a detector, a battery device, and a vehicle. The apparatus includes a filter circuit connected to an element to be detected and configured to filter signals from the element to be detected; a differential amplification circuit connected to the filter circuit and configured to amplify the filtered signals; and a processor connected to the differential amplification circuit and configured to process the amplified signals.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 6, 2020
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Zhimin Dan, Wei Zhang, Yizhen Hou, Jia Xu
  • Patent number: 10771070
    Abstract: A low voltage inverter-based amplifier includes a first inverter-based amplification module, a second inverter-based amplification module, an inverter-based feedforward module, and an inverter-based common mode detector. The first inverter-based amplification module receives an input signal. The second inverter-based amplification module receives the input signal through the inverter-based feedforward module, and receives a first output signal from the first inverter-based amplification module. The inverter-based common mode detector receives an amplified signal from the second inverter-based amplification module, and outputs a feedback signal to the second inverter-based amplification module. Since the first and the second inverter-based amplification modules are both inverter-based, the supply voltage of the low voltage inverter-based amplifier is provided to supply one PMOS and one NMOS for normal operation.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 8, 2020
    Assignee: KAIKUTEK INC.
    Inventors: Pang-Ning Chen, Chen-Lun Lin, Ying-Chia Chen, Wei-Jyun Wang, Mike Chun-Hung Wang
  • Patent number: 10742184
    Abstract: An instrumentation amplifier configured for providing high common mode rejection is described and includes an input differential stage configured to receive a differential input voltage and a folded cascode amplifying stage configured to receive output current mode signals provided from the input differential pair. A plurality of feedback networks is provided to improve the input stage. The amplifier may operate to provide an enhanced common mode rejection ratio of a single gain block in the instrumentation amplifier. In some examples, the circuitry may have a differential folded cascode amplifying stage which permits high precision and low distortion of amplified signals without degrading the common mode rejection ratio.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: August 11, 2020
    Assignee: Harman International Industries, Incorporated
    Inventors: Dimitri Danyuk, Todd A. Eichenbaum
  • Patent number: 10732931
    Abstract: A negative-operand compatible subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes two sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of two sets of scaled capacitors electrically connected to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground. A control circuit of the subtractor is configured to, in conjunction with the reset circuit, draw the difference output node to a reset voltage.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Phil Paone, David Paulsen, George Paulik, John E. Sheets, II, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10727797
    Abstract: A circuit includes a first signal swapper including a first terminal coupled to a first current source, a second terminal coupled to a second current source, a third terminal coupled to a first current terminal of a first transistor, and a fourth terminal coupled to a third current terminal of a second transistor. The first signal swapper couples the first and second terminals to the third and fourth terminals responsive to a first control signal. First and second switches couple to a gate of the first transistor. The first switch receives the input oscillation signal and the second switch receives a first reference voltage. Third and fourth switches couple to a gate of the second transistor. The third switch receives the input oscillation signal and the fourth switch receives the first reference voltage. A second signal swapper couples to the first signal swapper and to the first and second transistors.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: George Reitsma
  • Patent number: 10715358
    Abstract: A circuit for receiving signals in an integrated circuit device. The circuit comprises a first equalizer circuit having a first input for receiving a first input signal and generating an output signal at a first output; a second equalizer circuit having a second input for receiving the output signal generated at the first output of the first equalizer circuit and having a second output; and a control circuit having a control output coupled to the second output of the second equalizer circuit; wherein the control circuit provides an offset cancellation signal or a loopback signal to the second output of the second equalizer circuit. A method of receiving signals in an integrated circuit is also described.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 14, 2020
    Assignee: XILINX, INC.
    Inventors: Wenfeng Zhang, Stanley Y. Chen, Hsung Jai Im, Parag Upadhyaya
  • Patent number: 10615750
    Abstract: A preamplifier circuit includes a first transconductor and a floating transconductor. The first transconductor receives a differential voltage from a sample-and-hold circuit and drives the floating transconductor. The first and floating transconductors output amplified versions of the differential voltage that are not affected by capacitive division, which makes the preamplifier circuit fast. The preamplifier circuit also has a low input capacitance because the floating transconductor is not connected to any external circuitry.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: April 7, 2020
    Assignee: NXP B.V.
    Inventors: Sushil Kumar Gupta, Hitesh Kumar Garg
  • Patent number: 10608602
    Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajendrakumar Joish
  • Patent number: 10574194
    Abstract: In a general aspect, a circuit can include an amplifier circuit including a first amplifier, a first feedback path, and a second feedback path. The first feedback path can provide a feedback path from a positive output of the first amplifier to a negative input of the first amplifier. The second feedback path can provide a feedback path from a negative output of the first amplifier to a positive input of the first amplifier, The circuit can also include a loop circuit including a second amplifier, The loop circuit can be configured to provide a local feedback loop for the first amplifier and configured to control current flow into the positive input of the first amplifier and into the negative input of the first amplifier.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: February 25, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Tyler Daigle, Hrvoje Jasa, Andrew Jordan, Gregory Maher
  • Patent number: 10476457
    Abstract: The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET) and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programmed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel/W/L of drain channel).
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: November 12, 2019
    Assignee: Circuit Seed, LLC
    Inventors: Susan Marya Schober, Robert C. Schober
  • Patent number: 10425042
    Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: September 24, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ani Xavier, Neeraj Shrivastava, Arun Mohan, Shagun Dusad
  • Patent number: 10425043
    Abstract: An operational amplifier with a constant transconductance bias circuit and a method thereof are introduced. The operational amplifier includes a differential difference amplifier and the constant transconductance bias circuit. The differential difference amplifier has at least one first differential transistor pair and at least one second differential transistor pair. The constant transconductance bias circuit is electrically connected to the differential difference amplifier, and configured to output a first bias voltage to bias the at least one first differential transistor pair and output a second bias voltage to bias the at least one second differential transistor pair. The first bias voltage and the second bias voltage are configured to maintain constant transconductance of the differential difference amplifier.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 24, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventors: Jhih-Siou Cheng, Keko-Chun Liang
  • Patent number: 10418953
    Abstract: The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET) and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programmed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel/W/L of drain channel).
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: September 17, 2019
    Assignee: Circuit Seed, LLC
    Inventors: Susan Marya Schober, Robert C. Schober
  • Patent number: 10409307
    Abstract: A low dropout (LDO) device with improved linear mode comprising an error amplifier, a programmable attenuation factor circuit coupled to said error amplifier, a feedback network whose input is electrically connected to said programmable attenuation factor circuit and whose output is electrically coupled to the negative input of said error amplifier, a high side (HS) pre-drive circuit whose input is a high impedance (HiZ) mode signal, a low side (LS) pre-drive circuit whose input is a low pull-down input mode signal, a high side (HS) output stage element electrically coupled to said high side (HS) pre-drive circuit, a low side (LS) output stage element electrically coupled to said low side (LS) pre-drive circuit, and a high side sense (HSENSE) output stage element whose gate is electrically coupled to said high side (HS) pre-drive circuit, and whose gate and source are electrically connected to the output of said error amplifier.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: September 10, 2019
    Assignee: Dialog Semiconductor GmbH
    Inventors: Zakaria Mengad, Mykhaylo Teplechuk
  • Patent number: 10395591
    Abstract: A display device including a display unit which has a plurality of pixels and a plurality of driving lines for driving the plurality of pixels; a driving circuit which drives the plurality of pixels through the plurality of driving lines; and a control unit which adjusts a driving capability of the driving circuit according to the number of simultaneous driving lines of the driving circuit.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: August 27, 2019
    Assignee: SATURN LICENSING LLC
    Inventor: Teisuke Kishikawa
  • Patent number: 10396144
    Abstract: Provided is an inductor structure. In embodiments of the invention, the inductor structure includes a first laminated stack. The first laminated stack includes layers of an insulating material alternating with layers of a first magnetic material. The inductor structure includes a laminated second stack formed on the first laminated stack. The second laminated stack includes layers of the insulating material alternating with layers of a second magnetic material. The second magnetic material has a greater permeability than does the first magnetic material.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 10389400
    Abstract: Radio frequency switch circuitry is disclosed having first and second port terminals, a switch branch having first and second branch terminals, and a branch control terminal, wherein the switch branch is configured to pass an RF signal between the first and second branch terminals in an on-state and block the RF signal from passing between the first and second branch terminals in an off-state in response to a control signal that is coupled with the RF signal and received at the first port terminal. Control signal decoupling circuitry has a control signal input terminal coupled to the first port terminal to receive the control signal coupled to the RF signal and a control signal output terminal coupled to the branch control terminal, wherein the control signal decoupling circuitry is configured to decouple the control signal from the RF signal and provide the control signal to the branch control terminal.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: August 20, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Ali Tombak, Daniel Charles Kerr, Edward T. Spears
  • Patent number: 10295573
    Abstract: A coil that includes compensation.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 21, 2019
    Assignee: Veris Industries, LLC
    Inventor: Martin Cook
  • Patent number: 10277171
    Abstract: An amplifying unit includes a converter and a feedback mechanism. The converter has a supply input coupled to a supply node. The converter further has an input terminal configured to receive an input signal. The converter is configured to amplify the input signal from the input terminal to generate an output signal. The feedback mechanism is coupled to the input terminal of the converter and is configured to cause a constant bias current to flow from the supply node through the converter based on the input signal.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limted
    Inventors: An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh, Wen-Sheng Chen
  • Patent number: 10263585
    Abstract: An amplifier system includes a main amplifier, a cross-over current detector and a controller. The main amplifier includes at least a first driving transistor and a second driving transistor serving as a differential pair, wherein the first driving transistor and the second driving transistor are arranged to receive a first input signal and a second input signal, respectively. The cross-over current detector is coupled to the main amplifier, and is arranged for detecting a cross-over current of the main amplifier, wherein the cross-over current of the main amplifier is an overlapped current from the differential pair. The controller is coupled to the main amplifier and the cross-over current detector, and is arranged for generating a control signal to control a gain of the main amplifier according to an output of the main amplifier and the cross-over current of the main amplifier.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: April 16, 2019
    Assignee: MEDIATEK INC.
    Inventor: Lai-Ching Lin
  • Patent number: 10200056
    Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 5, 2019
    Assignee: AnDAPT, Inc.
    Inventors: Maheen Samad, Patrick J. Crotty, John Birkner, Herman Cheung, Kapil Shankar
  • Patent number: 10199997
    Abstract: Certain aspects of the present disclosure generally relate to using cross-coupled transistors for source degeneration of an amplification stage. For example, the amplification stage generally includes a differential amplifier comprising transistors, cross-coupled transistors coupled to the differential amplifier, and an impedance coupled between drains of the cross-coupled transistors. In certain aspects, the differential amplifier comprises a push-pull amplifier, and the transistors of the push-pull amplifier comprise cascode-connected transistors.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: February 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Rahul Karmaker
  • Patent number: 10193540
    Abstract: An apparatus and method and system therefor relates generally to decision threshold control. In such an apparatus, an ac-coupler circuit is configured as a high-pass circuit path for a first frequency range. A buffer amplifier circuit is coupled in parallel with the ac-coupler circuit. The buffer amplifier circuit is configured as a low-pass circuit path for a second frequency range. An offset injection circuit is coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: January 29, 2019
    Assignee: XILINX, INC.
    Inventors: Jaeduk Han, Hsung Jai Im
  • Patent number: 10177147
    Abstract: A semiconductor device is provided. Gates of first PMOS and NMOS transistors are coupled together for receiving an input signal. Gates of second PMOS and NMOS transistors are coupled together. Gates of third PMOS and NMOS transistors are coupled together. Gates of fourth PMOS and NMOS transistors are coupled together. Drains of fourth PMOS and NMOS transistors are coupled together for providing an output signal. When the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, the output signal is provided according to the input signal and a first logic function. When the first and second NMOS transistors are connected in serial and the first and second PMOS transistors are connected in serial, the output signal is provided according to the input signal and a second logic function.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: January 8, 2019
    Assignee: MEDIATEK INC.
    Inventor: Yiwei Chen
  • Patent number: 10152942
    Abstract: A display apparatus includes a timing controller, a data driver and a display panel. The data driver generates a positive polarity data voltage and a negative polarity data voltage based on image data compensated by the timing controller. The display panel includes a first pixel driven based on the positive polarity voltage and a second pixel driven based on the negative polarity voltage. The display panel receives a storage voltage applied to the first pixel and the second pixel. The timing controller compensates the image data when a variation on a level of the storage voltage occurs. The compensation shifts a level of the first data voltage from a first normal level to a first compensation level in a direction, and shifts a level of the second data voltage from a second normal level to a second compensation level in the same direction.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sang Yong No, Kwihyun Kim, Youngsoo Sohn
  • Patent number: 10149347
    Abstract: Front-end integrated circuit for wireless local area network WLAN applications. In some embodiments, a semiconductor die can include a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to facilitate the transmit and receive operations.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: December 4, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventors: Chun-Wen Paul Huang, Lui Lam, Mark M. Doherty, Michael Joseph McPartlin
  • Patent number: 9998135
    Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 12, 2018
    Assignee: AnDAPT, INC.
    Inventors: Maheen Samad, Patrick J. Crotty, John Birkner, Herman Cheung, Kapil Shankar
  • Patent number: 9998080
    Abstract: A circuit includes a differential input pair stage including bipolar transistors and configured to receive an RF input signal; a cascode stage coupled between the differential input pair stage and an output node, the cascode stage including bipolar transistors; and a current source including a first bipolar transistor coupled to a first output of the differential input pair stage and a second bipolar transistor coupled to a second output of the differential input pair stage.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: June 12, 2018
    Assignee: Infineon Technologies AG
    Inventor: Saverio Trotta
  • Patent number: 9977446
    Abstract: In the example of a voltage regulator outputting a negative voltage, its feedback voltage will also be negative. The feedback voltage is typically created using a resistor divider. A controller IC is powered by only a positive voltage and receives the negative feedback voltage at a high impedance input of an inverting amplifier. Therefore, the inverting amplifier does not load the resistor divider, resulting in an accurate regulated output voltage. The inverting amplifier converts the negative feedback voltage to a positive feedback voltage for further processing by the controller IC. An error amplifier and a power good monitor receive both the original feedback voltage and the inverted feedback voltage and use whichever feedback voltage is the more positive one. Therefore, the controller IC may be used in voltage regulators that generate either negative or positive output voltages.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 22, 2018
    Assignee: Linear Technology Corporation
    Inventors: Hezekiel D. Randolph, Min Chen, Niranjan G. Kumar
  • Patent number: 9952616
    Abstract: A differential circuit includes a first constant current circuit, a second constant current circuit having the same constant current value as the first constant current circuit, a current mirror including a first transistor having a current sink terminal connected to the first constant current circuit, a current drain terminal to which a first input voltage is applied, and a gate short-circuited to the current sink terminal, and a second transistor having a gate connected to the current sink terminal of the first transistor and a current drain terminal to which a second input voltage is applied, and a current output terminal connected to a connection node between a part in which a current based on an output current of the current mirror flows and the second constant current circuit.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: April 24, 2018
    Assignee: Rohm Co., Ltd.
    Inventor: Tadashi Akaho
  • Patent number: 9941868
    Abstract: A buffer circuit may include an amplification circuit, a main load circuit, and a sub-load circuit. The amplification circuit and the main load circuit may generate first and second output signals by amplifying first and second input signals. The sub-load circuit may compensate mismatch between rising timing and falling timing of the first output signal based on the first input signal.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: April 10, 2018
    Assignee: SK hynix Inc.
    Inventors: Jong Joo Shim, Jee Yeon Keh
  • Patent number: 9935048
    Abstract: An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: April 3, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Yossi Smeloy, Eyal Frost
  • Patent number: 9935583
    Abstract: A power amplifier circuit includes an input that receives a first input signal having a first phase and a second input signal having a second phase, a first transistor that includes a source that is supplied with a first voltage, and a gate that receives the first input signal, a second transistor that includes a source that is supplied with the first voltage, and a gate that receives the second input signal, a first neutralizing circuit that neutralizes a parasitic element, a second neutralizing circuit that neutralizes a parasitic element, N third transistors, N being an integer equal to or higher that 1, N fourth transistors, and an output that is connected between a drain of the N-th third transistor and a drain of the N-th fourth transistor and outputs a first output signal having a third phase and a second output signal having a fourth phase.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: April 3, 2018
    Assignee: PANASONIC CORPORATION
    Inventors: Takayuki Abe, Junji Sato
  • Patent number: 9912344
    Abstract: A sort-and-delay time-to-digital converter (TDC) is provided, made up of a plurality of serially connected sort-and-delay circuits. Each sort-and-delay circuit accepts a time-differential input signal with a first edge separated from a second edge by an input duration of time. The first and second edges are selectively routed as a time-differential output signal with a delayed edge separated from a trailing edge by an output duration of time representing a compression of the input duration of time. Each sort-and-delay circuit also supplies a TDC coded bit (e.g., Gray code) indicating the order in which the first and second edges are routed as leading and trailing edges. The TDC outputs a digital output signal representing the initial input duration of time associated with the initial time-differential input signal received by the initial sort-and-delay circuit. Associated TDC, sort-and-delay, and time amplification methods are also provided.
    Type: Grant
    Filed: September 17, 2017
    Date of Patent: March 6, 2018
    Assignee: IQ-Analog Corp.
    Inventor: Mikko Waltari
  • Patent number: 9912295
    Abstract: A method for pre-amplifying an input voltage signal to a pre-amplified voltage signal. The method includes receiving the input voltage signal; obtaining a high-pass filtered voltage signal by applying a high-pass filter to the input voltage signal; processing the high-pass filtered voltage signal to a current signal that corresponds to the high-pass filtered voltage signal; transmitting the current signal through a differential transmission line; converting the transmitted current signal to a converted voltage signal that corresponds to the high-pass filtered voltage signal; and outputting the converted voltage signal as the pre-amplified voltage signal. An integrated circuit chip implementing the method is also disclosed.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: March 6, 2018
    Assignee: Marvell International Ltd.
    Inventors: Xiao Yu Miao, Peng Sun, Shilpa Kumar
  • Patent number: 9898978
    Abstract: The present disclosure relates to a liquid crystal panel and the driving circuit. The liquid crystal panel includes a plurality of source driving circuits and a plurality of sub-pixel rows extending along a row direction. Each of the sub-pixel rows includes a plurality of sub-pixels of different colors and the sub-pixels are arranged periodically along the row direction. Within one scanning frame, polarity of driving voltage of at least one sub-pixel within the arranging period is opposite to that of other sub-pixels. Each of the source driving circuit includes at least two output ends respectively connecting to at least two sub-pixels having the same polarity of driving voltage within the same scanning frame to provide the driving voltage of the same polarity to the at least two sub-pixels. In this way, the power consumption of the source driving circuit may be reduced.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: February 20, 2018
    Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd, WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventors: Xingling Guo, Jinjie Zhou, Yujie Bai
  • Patent number: 9891761
    Abstract: There are provided a touch sensing device and a touchscreen device. The touch sensing device includes: a driving circuit applying a driving signal having a predetermined first period to a node capacitor; a buffer circuit converting capacitance of the node capacitor into a voltage signal; a buffer capacitor being charged and discharged depending on an output voltage from the buffer circuit; and an integration circuit integrating voltages charged in the buffer capacitor, wherein, in a normal touch mode, the buffer circuit integrates capacitance of the node capacitor to generate the voltage signal, and, in a proximity touch mode, the buffer circuit generates the voltage signal by following the voltages charged in the node capacitor.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: February 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byeoung Hak Jo, Moon Suk Jeong, Yong Il Kwon, Tah Joon Park
  • Patent number: 9871492
    Abstract: An analog amplifier is provided. The analog variable amplifier includes a first amplifier stage configured to amplify a bias current to output a first output voltage and a second output voltage that respectively depend on a magnitude of a first input voltage and a second input voltage, a second amplifier stage configured to receive the first output voltage and the second output voltage of the first amplifier stage as inputs and to amplify the received first output voltage and the second output voltage, and at least one auxiliary bias current source coupled to an electrical connection between the first amplifier stage and the second amplifier stage through which the second amplifier stage receives the first output voltage, and coupled to an electrical connection between the first amplifier stage and the second amplifier stage through which the second amplifier stage receives the second output voltage.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: January 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Woo Lee, Byung-Hak Cho, Jae-Hyun Lim
  • Patent number: 9853607
    Abstract: A low-noise amplifier comprises first and second input ports respectively configured to receive a positive and negative input voltages; first and second resonance circuit, first and second transistor; wherein a first voltage output port of the first resonance circuit is connected to the second transistor, and a second voltage output port of the second resonance circuit is connected to the first transistor, the first and second voltage output ports are crossed coupled to a second node of both the first transistor and the second transistor via a first and second capacitor respectively; the second node of the second transistor is connected to both the second input port via a third capacitor and a third node of the first transistor, and the second node of the first transistor is connected to both the first input port via a fourth capacitor and a third node of the second transistor.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: December 26, 2017
    Assignee: BEKEN CORPORATION
    Inventors: Jiazhou Liu, Dawei Guo
  • Patent number: 9837973
    Abstract: A differential input circuit (FIG. 3A) is disclosed. The circuit includes a first input terminal (drain of 310) and a second input terminal (drain of 312). A first input transistor (310) has a first control terminal and has a current path coupled to the first input terminal. A second input transistor (312) has a second control terminal and has a current path coupled to the second input terminal. A third transistor (306) has a third control terminal and has a current path between a first differential input terminal (Vin+) and the first control terminal. A fourth transistor (308) has a fourth control terminal and has a current path between a second differential input terminal (Vin?) and the second control terminal.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: December 5, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Steven Graham Brantley, Vadim Valerievich Ivanov
  • Patent number: 9813032
    Abstract: A negative impedance circuit including: a first and a second bipolar transistors having a common collector, a base of the first transistor being connected to an emitter of the second transistor; a third and a fourth bipolar transistors having a common collector, a base of the third transistor being connected with an emitter of the fourth transistor; and at least one first impedance formed of one or of a plurality of passive components coupling the common collector of the first and second transistors to the common collector of the third and fourth transistors, a base of the second transistor being coupled to the collector of the third and fourth transistors and a base of the fourth transistor being coupled to the collector of the first and second transistors.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: November 7, 2017
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventors: Lotfi Batel, Jean-François Pintos, Lionel Rudant
  • Patent number: 9807189
    Abstract: A data transfer device compresses and transfers data according to a priority given to a CPU-constraint process imposing a constraint to a compression processing speed over a NW bandwidth-constraint process imposing a constraint to a transfer processing speed. It is necessary to select a compression algorithm, applied to the CPU-constraint process or the NW bandwidth-constraint process, based on a NW bandwidth, compressibility, and compression processing speed maximizing an effective throughput. When the amount of compressed data held in a temporary hold part is smaller than the predetermined value, the compressed data of the NW bandwidth-constraint process is stored in a temporary hold part. When the amount of compressed data held by the temporary hold part is larger than the predetermined value, the compressed data of the CPU-constraint process is stored in the temporary hold part. Thus, it is possible to improve an effective throughput by effectively using NW bandwidths.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: October 31, 2017
    Assignee: NEC CORPORATION
    Inventor: Masumi Ichien
  • Patent number: 9780838
    Abstract: A data communications receiver including a receiver coil, a first amplification stage coupled to the receiver coil, the first amplification circuitry to differentially amplify at least part of signal received by the receiver coil relative to a threshold, a second amplification stage coupled to receive the differentially amplified signal from the first amplification stage, the second amplification stage comprising a current mirror, and hysteretic level shifting circuitry to shift a level of part of the signal received by the receiver coil, the threshold or part of the signal received by the receiver coil and the threshold such that, in response to the at least part of the signal received by the receiver coil having crossed the threshold, a threshold crossing in the other direction is delayed.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: October 3, 2017
    Assignee: CT-Concept Technologie GmbH
    Inventors: Matthias Peter, Jan Thalheim
  • Patent number: 9774315
    Abstract: Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable inductive peaking of the load is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: September 26, 2017
    Assignee: XILINX, INC.
    Inventors: Jinyung Namkoong, Wenfeng Zhang, Parag Upadhyaya
  • Patent number: 9742361
    Abstract: Disclosed here is an apparatus that comprises an amplifier having first and second input nodes, first and second resistors, a first electrostatic discharge protection circuit coupled between the first input node and the first resistor, and a second electrostatic discharge protection circuit coupled between the second input node and the second resistor.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Kazuhiro Yoshida, Hisayuki Nagamine
  • Patent number: 9729179
    Abstract: Systems and methods for interference cancellation in a receiver of wireless signals include receiving a signal comprising an aggressor and a desired signal. The received signal is amplified in a low noise amplifier (LNA) to generate an amplified received signal. The aggressor is extracted from the received signal in a feed-forward path between an input of the LNA and an output of the LNA, to generate an extracted aggressor and the extracted aggressor is subtracted from the amplified received signal to provide the desired signal. An amplify and rotate block in the feed-forward path is used to align a phase of the aggressor to a phase of the amplified received signal in order to enable the subtraction.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: August 8, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Mohammad Emadi, Mazhareddin Taghivand, Yann Ly-Gagnon
  • Patent number: 9722554
    Abstract: When the offsets of the first and second differential units have polarities different from each other, the first and second differential units are both set to a normal connection state, i.e., a state in which the input voltage is supplied to the first input terminal of each of the first and second differential units and the output voltage is supplied to the second input terminal of each of the first and second differential units. When the offsets of the first and second differential units have the same polarity, on the other hand, the first differential unit is set to the above normal connection state and the second differential unit is set to a chopping connection state in which the output voltage is supplied to the first input terminal and the input voltage is supplied to the second input terminal.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 1, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Koji Higuchi
  • Patent number: 9711109
    Abstract: A data processing apparatus includes a compressor and an output interface. The compressor generates a compressed display data by compressing a display data according to a compression algorithm. The output interface appends first indication information in a first output bitstream, appends second indication information in a second output bitstream, and outputs the first output bitstream and the second output bitstream via a display interface. The first output bitstream is derived from the compressed display data. The first indication information is set in response to the compression algorithm employed by the compressor. The first indication information is different from the second indication information. The display interface is arranged for coupling to a driver circuit.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: July 18, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chi-Cheng Ju, Tsu-Ming Liu
  • Patent number: 9705451
    Abstract: An envelope tracking system is employed in a power amplification module that supports multiple frequency bands. The power amplification module includes multiple power amplification circuits, each of which includes: a first transformer to which a radio frequency signal is input; a differential amplification circuit, in which a first radio frequency signal output from transformer is input to a control electrode and in which a second radio frequency signal output from the transformer is input to a control electrode, the differential amplification circuit outputting an amplified signal obtained by amplifying a difference between the first and second radio frequency signals; and a second transformer for supplying, to the first differential amplification circuit, power-supply voltage varying according to the amplitude of the radio frequency signal and to which the first amplified signal is input.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: July 11, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kiichiro Takenaka, Tsuyoshi Sato, Masahiro Ito, Hidetoshi Matsumoto, Satoshi Tanaka
  • Patent number: 9699551
    Abstract: An analog signal processing circuit of a microphone includes a bias circuit including a first sub-circuit which receives a signal from the microphone to output a first signal and a second sub-circuit which receives a reference voltage to output a second signal. A fully differential circuit receives the first signal and the second signal to output a fully differential signal. Each of the first sub-circuit and the second sub-circuit includes a bias sub-circuit to apply a bias voltage.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: July 4, 2017
    Assignee: Hyundai Motor Company
    Inventors: Sang-Hyeok Yang, Sang Gyu Park