Abstract: Examples of amplifier circuitry regulate a transconductance value (Gm) of operational transconductance amplifiers (OTAs) in the amplifier to be approximately the same, which value is based on a supply voltage and a reference voltage applied to a reference OTA and the internal resistance of the reference OTA. The reference OTA generates an output current based on Gm and the reference voltage, which current is compared to current generated by the supply voltage and internal resistance of the reference OTA. A tail current transistor of each of the reference OTA and a main OTA that mirrors the Gm of the reference OTA provide a tail current feedback path by which Gm is regulated. Amplifying circuitry is coupled to the main OTA to receive current signals. Based on the received current signals, amplifying circuitry generates a differential output voltage signal. The gain of the amplifying circuitry is proportional to the supply voltage and remains relatively constant across process temperature variations.

Abstract: A transceiver circuit includes a first interface and a second interface that are connected to an optical transceiver device, a receiver circuit, a transmitter circuit, and a compensation circuit. The receiver circuit includes a differential amplifier, where a first phase input terminal of the differential amplifier is coupled to the first interface, and a second phase input terminal of the differential amplifier is coupled to the second interface. The transmitter circuit includes a first transistor, where a terminal of the first transistor is coupled to the second phase input terminal, and another terminal of the first transistor is coupled to a ground terminal. The compensation circuit is configured to provide a leakage path for the first phase input terminal, or provide a compensation current for the second phase input terminal.

Abstract: An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

Abstract: A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.

Abstract: A distributed amplifier includes: a transmission line having an input end that an input signal is input to; a transmission line having an output end that an output signal is output from; an input termination resistor connected to an end terminal of the transmission line; a plurality of unit cells arranged along the transmission lines, and having input terminals connected to the transmission line and output terminals connected to the transmission line; and a variable current source having one end connected to the end terminal of the transmission line and another end connected to a power supply voltage, and capable of adjusting a current amount between the transmission line and the power supply voltage.

Abstract: Methods and apparatus for capacitively isolated first communication channels with common mode noise suppression. In embodiments, a driver on the first circuit transmits a data signal on the first communication channel to a receiver on the second circuit. A common mode suppression circuit on the second circuit is coupled to the receiver, output of the suppression circuit is coupled to a node between the first capacitor and the resistor network and an input is coupled to a ground of the first circuit via a second capacitor. The common mode suppression circuit is configured to detect a common mode movement signal due to a noise pulse to the second circuit on the input and generate a corresponding signal on the output to maintain a current level across the resistor network for suppressing common mode noise from the pulse.

Abstract: An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.

Abstract: A switched-capacitor amplifier includes a sampling capacitor, a first switch, a differential amplifier, a reference power supply, a second switch, a third switch, and a controller configured to execute on and off control of the first to third switches. The second switch includes a series circuit of first and second metal oxide semiconductor (MOS) transistors and a potential holding capacitor connected between a node that is a common connection point of the first and second MOS transistors and a ground.

Abstract: Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system or a 6th-Generation (6G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system. A frequency multiplier of a wireless communication system is provided.

Abstract: A transconductor circuitry (10) with adaptive biasing comprises a first input terminal (E10a) to apply a first input signal (inp), and a second input terminal (E10b) to apply a second input signal (inn). A control circuit (200) is configured to control a first controllable current source (110) in a first current path (101) and a second controllable current source (120) in a second current path (102) in response to at least one of a first potential of a first node (N1) of the first current path (101) and a second potential of a second node (N2) of the second current path (102). The first node (N1) is located between a first transistor (150) and the first controllable current source (110), and the second node (N2) is located between a second transistor (160) and the second controllable current source (120).

Abstract: The present application discloses a trimming circuit of differential amplifier, wherein an output end of the differential amplifier is coupled to a first input end of the differential amplifier through a first voltage-dividing resistor; a shift voltage is coupled to a second input end of the differential amplifier through a second voltage-dividing resistor; the first voltage-dividing resistor and the second voltage-dividing resistor respectively form a T-shaped resistor network structure; the T-shaped resistor network structure comprises: a k-bit resistive network coupled to a T-shaped node and a reference power supply end, wherein a low n-bits of the k-bit resistive network is an R-2R resistive network, and part of branches are connected in series with at least one trimming resistor, and each trimming resistor is connected in parallel with a switch.

Abstract: A radio frequency (RF) equalizer in an envelope tracking (ET) circuit is disclosed. A transmitter chain includes an ET circuit having an RF equalizer therein. The RF equalizer includes a two operational amplifier (op-amp) structure that provides a relatively flat gain and a relatively constant negative group delay across a frequency range of interest (e.g., up to 200 MHz). The simple two op-amp structure provides frequency response equalization and time tuning adjustment and/or creates a window Vcc signal.

Abstract: An optical device for optical signals comprises: a photodiode configured to receive the optical signals; and a linear transimpedance amplifier (TIA) having an input stage, an output stage, and at least one variable gain amplifier (VGA) provided between the input stage and the output stage. The optical device also comprises: an automatic gain control loop configured to rectify an output of the at least one VGA and compare the rectified output with a threshold gain setting to generate an automatic gain control voltage; and a detection circuitry being configured to detect a rate of change in the automatic gain control voltage and being configured to determine a first state indicative of an absence of the optical signals at the photodiode. At least in response to the determined first state, the detection circuitry is configured to disable the output stage of the linear TIA.

Abstract: A first primary line has a first node at one end and a third node at another end and transmits a radio-frequency signal between the first node and the third node. A second primary line has a second node at one end and a fourth node at another end and transmits a radio-frequency signal between the second node and the fourth node. A first secondary line has a portion connected to the second node and is electromagnetically coupled to the first primary line. The second secondary line has a portion connected to the first node and has another end connected to a portion of the first secondary line. The second secondary line is electromagnetically coupled to the second primary line. A first capacitor is connected in parallel to a portion of the second primary line or a portion of the second secondary line.

Abstract: A power amplifier is capable of operating in a first power mode and a second power mode with a gain lower than a gain of the first power mode. The power amplifier is connected to a first common terminal of the first switch. Two or more filters are connected to two or more first selection terminals other than at least one first selection terminal among three or more first selection terminals of the first switch. The at least one first selection terminal of the first switch and at least one second selection terminal of a second switch are connected. The first switch is capable of switching between a first path passing through at least one of the two or more filters and a second path not passing through any of the two or more filters but passing through the at least one first selection terminal.

Abstract: Technologies are provided for variable gain amplifiers (VGAs).

Abstract: In one embodiment, a method includes generating, through a first transistor of an impedance trimming circuit, a precision current based on a reference voltage and an automatic test equipment (ATE) in a first phase of the impedance trimming circuit, wherein the ATE is coupled to the impedance trimming circuit to receive the precision current; mirroring the precision current into a second transistor and a first on-die resistor; sending a first internal voltage feedback at an internal node VFBINT to the ATE, wherein the internal node VFBINT is coupled to the second transistor and the first on-die resistor; and receiving a first trimming code to trim the first on-die resistor, wherein the first trimming code is based on a comparison of the first on-die resistor and a target on-die resistor by the ATE.

Abstract: Provided are an output matching circuit and a power amplifier comprised thereof. The output matching circuit comprises an impedance transformation component and a first matching component connected to the input end of the impedance transformation component to establish matching. The first matching circuit comprises an impedance element and a controllable switch element whose on/off is controlled by an external control signal to form different impedances. The output matching circuit realizes the reconstruction of the output stage matching circuit and the switching of the output operating frequency band. It can be used for high frequency/medium frequency/low frequency, which reduces the cost, the number of components, and the design difficulty, and is easy to be integrated. It can be used for multi-band multiplexing power amplifiers. The wide-band amplifier is realized, the number of components and material cost are reduced, and the system integration degree of the power amplifier is increased.

Abstract: An example SC integrator can include first and second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. The SC integrator can be configured for adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at one or more cycles of a master clock and can be configured for keeping the time distance/delay between those samples relatively small across a range of master clock frequencies.

Abstract: A power amplification circuit includes a first amplifier that amplifies a signal split from an input signal, a second amplifier that amplifies a signal having a different phase from the aforementioned signal, third and fourth amplifiers, and a matching network. The matching network includes a first wiring having a first end connected to an output terminal of the first amplifier and a second end connected to an input terminal of the third amplifier, a second wiring having a first end connected to the input terminal of the third amplifier, and electromagnetically coupled to the first wiring, a third wiring having a first end connected to an output terminal of the second amplifier and a second end connected to an input terminal of the fourth amplifier, and a fourth wiring having a first end connected to the input terminal of the fourth amplifier, and electromagnetically coupled to the third wiring.

Abstract: Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.

Abstract: An envelope stacking power amplifier system reduces current for a given output power level without sacrificing the ability to support large voltage swings at saturation and therefore increases efficiency at the maximum linear operating power and all power levels below that. The system includes a stack/unstack controller including circuitry configured to switch the RF power amplifier system between a stacked mode in which first and second RF amplifiers are coupled in a stacked configuration and an unstacked mode in which the first and second RF amplifiers are coupled in an unstacked configuration in response to one or more mode-control signals, the stacked configuration providing reduced current compared to the unstacked configuration.

Abstract: Apparatus and methods for oscillation suppression of cascode power amplifiers are provided herein. In certain implementations, a power amplifier system includes a cascode power amplifier including a plurality of transconductance devices that operate in combination with a plurality of cascode devices to amplify a radio frequency input signal. The power amplifier system further includes a bias circuit that biases the plurality of cascode devices with two or more bias voltages that are decoupled from one another at radio frequency to thereby inhibit the cascode power amplifier from oscillating.

Abstract: Embodiments relate to an amplifier circuit. The amplifier circuit includes multiple transistors. Each transistor is configured to receive an input signal and output an amplified signal. The amplifier circuit additionally includes a set of input chopper circuits and a set of output chopper circuits. Each output chopper circuit corresponds to one input chopper of the set of input choppers. Each input chopper circuit and its corresponding output chopper are controlled by one or more control signals from a set of control signals. Each input chopper circuit is configured to selectively connect each transistor of a transistor pair to a first input terminal or a second input terminal based on a value of the one or more control signals. Moreover, each output chopper circuit is configured to selectively connect each transistor of the transistor pair to a first output terminal or a second output terminal based on the value of the one or more control signals.

Abstract: Envelope tracking power supply circuitry includes a look up table (LUT) configured to provide a target supply voltage based on a power envelope measurement. The target supply voltage is dynamically adjusted based on a delay between the power envelope of an RF signal and a provided envelope tracking supply voltage. The envelope tracking supply voltage is generated from the adjusted target supply voltage in order to synchronize the envelope tracking supply voltage with the power envelope of the RF signal.

Abstract: Provided is a control circuit of a buck converter, comprising three transistors, seven resistors and a comparator. Also provided is a server. In this solution, when a phase voltage of a buck converter changes, a controller in the buck converter is controlled to output a signal for turning off a lower MOS transistor, so that after the signal is transmitted through the line, the lower MOS transistor can be controlled to be exactly turned off just when the current is reversed. Such an accurate reverse current detection function can reduce the voltage loss of the buck converter, thereby improving the efficiency of a system in standby or having a light load.

Abstract: One example discloses a level-shifter circuit, comprising: a pre-driver stage configured to receive differential inputs and generate differential pre-driver outputs; a first output stage coupled to receive the differential pre-driver outputs and generate a single-ended first stage output; a second output stage coupled to receive the differential pre-driver outputs and generate a single-ended second stage output; and wherein the first and second stage outputs together form a differential output.

Abstract: Disclosed is a phase shifter, which includes a signal generator that generates a first signal and a second signal having a phase orthogonal to a phase of the first signal, and outputs the first signal and the second signal, an operator that generates a first current and a second current, and amplifies the first current and the second current, and a signal converter converting a first digital signal and a second digital signal. The operator includes an input circuit converting the first signal and the second signal, a path selection circuit determining paths of the generated first current and the generated second current, and a cascode circuit buffering the first current and the second current. The operator sums the first current and the second current, controls a vector of the first current and a vector of the second current, and generates a voltage signal through an output load.

Abstract: An example transconductance circuit includes a first portion that includes a first degeneration transistor, configured to receive a first input voltage, and a second portion that includes a second degeneration transistor, coupled to the first degeneration transistor and configured to receive a second input voltage. The first portion further includes a first input transistor, coupled to the first degeneration transistor and configured to provide a first output current, while the second portion further includes a second input transistor, coupled to the second degeneration transistor and configured to provide a second output current. Such a transconductance circuit may be used as an input stage capable of reliably operating within drain-source breakdown voltage of the transistors employed therein even in absence of any other protection devices, and may be significantly faster, consume lower power, and occupy smaller die area compared to conventional transconductance circuits.

Abstract: In an embodiment, an electronic circuit includes: an input differential pair including first and second transistors; a first pair of transistors in emitter-follower configuration including third and fourth transistors, and an output differential pair including fifth and sixth transistors. The third transistor has a control terminal coupled to the first transistor, and a current path coupled to a first output terminal. The fourth transistor has a control terminal coupled to the second transistor, and a current path coupled to a second output terminal. The fifth transistor has a control terminal coupled to the first transistor, and a first current path terminal coupled to the first output terminal. The sixth transistor has a control terminal coupled to the second transistor, and a first current path terminal coupled to the second output terminal. First and second termination resistors are coupled between the first pair of transistors and the output differential pair.

Abstract: A data driving integrated circuit of the present embodiment may include a digital to analog converter configured to change a digital signal into an analog signal and an amplifier configured to receive the analog signal through an input terminal and output a data voltage to a pixel connected to a data line, wherein the amplifier may receive, as feedback, one of a plurality of output signals from a plurality of output terminals.

Abstract: An amplifier includes a first stage and a second stage. The first stage includes a floating current source to maintain current within a threshold. The first stage also includes a local common mode feedback configured to provide gain to an input signal. Moreover, the second stage includes a driver that provides a load current to a load coupled to the amplifier.

Abstract: Embodiments disclosed herein relate to isolating a receiver circuit of an electronic device from a transmission signal and leakage of the transmission signal. To do so, an isolation circuit is disposed between the receiver circuit and a transmission circuit. The isolation circuit may include multiple variable impedance devices and one or more antennas. The impedances of the variable impedance devices may be balanced such that a signal at a particular frequency or within a particular frequency band can pass through or is blocked by the isolation circuit. The isolation circuit may include one or more double balanced duplexers to achieve the improved isolation. The isolation circuit may also increase bandwidth available for wireless communications of the electronic device.

Abstract: A variable gain amplifier system includes a variable gain amplifier circuit configured to receive an input signal, apply a gain to the input signal, and generate an output signal in accordance with the gain applied to the input signal. The variable gain amplifier circuit is further configured to receive a gain control signal and a bandwidth control signal. A control module is configured to generate the gain control signal to adjust the gain of the variable gain amplifier circuit and generate, separately from the gain control signal, the bandwidth control signal to adjust a bandwidth of the variable gain amplifier circuit by selectively varying an amount of inductance contributed by an inductor circuit of the variable gain amplifier circuit.

Abstract: Aspects of this disclosure relate to a segmented receiver for a wireless communication system. The segmented receiver includes a first receiver segment and a second receiver segment configured to receive respective radio frequency signals. The radio frequency signals can be orthogonally polarized. Branch circuits in each receiver segment can provide a radio frequency signal to different mixers. The different mixers can be included in different receiver segments and receive local oscillator signals from independent local oscillators. Each receiver segment can process a different bandwidth of the radio frequency signal. Two different bandwidths of the radio frequency signal can be processed concurrently by different receiver segments.

Abstract: Regulator circuitry includes first to third output transistors, a first control transistor and a circuit stage. The first and second output transistors, and the first control transistor have a first channel conductivity type. The second output transistor has a second channel conductivity type. The first and second output transistors have a drain coupled to an output node and a source coupled to a first power supply line. The third output transistor has a drain coupled to the output node and a source coupled to a second power supply line. The circuit stage is configured to drive the gates of the first output transistor, the third output transistor, and the first control transistor based on a specified level of the output voltage.

Abstract: A linear power supply circuit includes an output transistor provided between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, and a driver configured to drive the output transistor based on the difference between a voltage based on the output voltage and a reference voltage. The driver includes a differential amplifier, a converter, and a first capacitor provided between the output of the differential amplifier and a ground potential. The linear power supply circuit further includes a source follower circuit including a first transistor, and moreover includes a second transistor connected in series with the output transistor and constituting together with the first transistor a current mirror circuit, and a second capacitor connected to the control terminal of the first transistor.

Abstract: Disclosed is an operational amplifier based on a metal-oxide TFT. The operational amplifier includes an auxiliary amplifier and a bootstrap gain-increasing amplifier. The auxiliary amplifier adopts a two-stage positive feedback structure, including a fifth transistor, a seventh transistor, an eleventh transistor, a first amplifying unit, and a second amplifying unit. A gate of the fifth transistor serves as an input end of the operational amplifier. The bootstrap gain-increasing amplifier includes two second circuits in mutual symmetry. Each of the second circuits includes a first transistor, a second transistor, and a current source unit with a bootstrap structure.

Abstract: Examples of the disclosure include an amplifier system comprising an amplifier having an input to receive an input signal, and an output to provide an amplified output signal, the amplifier having a power level indicative of at least one of the input signal power and the amplified output signal power, and a linearizer coupled to the amplifier and having a plurality of modes of operation including a fully disabled mode and a fully enabled mode, the linearizer being configured to determine the power level of the amplifier, select a mode of operation of the plurality of modes of operation based on the power level of the amplifier, determine one or more linearization parameters corresponding to the selected mode of operation, and control linearization of the amplified output signal based on the determined one or more linearization parameters.

Abstract: An automatic gain control circuit includes a linear-to-log conversion circuit, a current amplifier circuit, and an amplitude sense circuit. The current amplifier circuit includes a current input terminal coupled to an output terminal of the linear-to-log conversion circuit. The amplitude sense circuit includes an input terminal coupled to an output terminal of the current amplifier circuit, and an output terminal coupled to a gain control input terminal of the current amplifier circuit.

Abstract: A voltage-to-current converter circuit comprises an amplifier, a resistor, first and second feedback circuits, and an output circuit. The amplifier is configured to receive a differential input voltage signal. The resistor is coupled between first and second nodes of the amplifier. The first feedback circuit is coupled to a third node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a first range, and is turned off otherwise. The second feedback circuit is coupled to a fourth node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a second range different from the first range, and is turned off otherwise. The output circuit produces a differential current output signal having a value according to the value of the input voltage signal.

Abstract: Methods and devices to support multiple frequency bands in radio frequency (RF) circuits are shown. The described methods and devices are based on adjusting the effective width of a transistor in such circuits by selectively disposing matching transistors in parallel with the transistor. The presented devices and methods can be used in RF circuits including low noise amplifiers (LNAs), RF receiver front-ends or any other RF circuits where input matching to wideband inputs is required.

Abstract: A first transmission line and a second transmission line that are connected in series to each other are disposed at different positions in a thickness direction of a substrate. A third transmission line is disposed between the first transmission line and the second transmission line in the thickness direction of the substrate. The third transmission line includes a first end portion connected to one end portion of the first transmission line, and a second end portion that is AC-grounded. The first transmission line and the second transmission line are electromagnetically coupled to the third transmission line.

Abstract: An example apparatus includes: a receiver operable to receive a modulated input signal at a receiver input and output a demodulated signal at a receiver output, the receiver comprising a switch having a first current terminal and a first control terminal, the first current terminal coupled to the receiver output. The example apparatus includes a capacitor having a first terminal and a second terminal, the second terminal coupled to the first control terminal and the first terminal coupled to the receiver input. The example apparatus includes a resistor having a third terminal and a fourth terminal, the fourth terminal coupled to the first control terminal. The example apparatus includes a voltage offset source having an input and an output, the output coupled to the third terminal. The example apparatus includes a current source coupled to the first current terminal.

Abstract: In a limiting circuit that limits an output voltage of an operational amplifier, the signal quality of the output voltage is improved. The limiting circuit includes a short-circuit transistor and a gate voltage supply unit. In the limiting circuit, the short-circuit transistor short-circuits a path between an input terminal and an output terminal of the operational amplifier in a case where a voltage between the input terminal of the operational amplifier and the gate is higher than a predetermined threshold voltage. Furthermore, in the limiting circuit, the gate voltage supply unit supplies a voltage to the gate, the voltage depending on the threshold voltage and the output voltage of the output terminal.

Abstract: A transimpedance amplifier (TIA) device design is disclosed. Symmetric components include first and second resistors Ri, Rfb, Re, Rm, Rx, Rc, and Rl, and transistors Q1-Q4. An optional mixer or cascode adds transistors Q5-Q8. Values for resistor components Rx provide extended feedback gain tuning in a TIA-based current amplifier or mixer implementations without greatly affecting the input impedance or requiring more attenuators. Example values for resistor components Rx range from about 50 to about 350 ohms.

Abstract: A transimpedance amplifier circuit for generating an output voltage in accordance with an input current includes an offset resistor, a common emitter inverting amplifier having a first input and a first output, the first input receiving the input current, an emitter follower having a second input and a second output, the second input being coupled to the first output through the offset resistor, the second output outputting the output voltage, a feedback resistor connected between the second output and the first input, a variable current source connected to a node between the offset resistor and the second input, the variable current source configured to provide an offset current to the offset resistor, the offset current having a current value varied in accordance with a control signal, and a control circuit configured to generate the control signal so that an average voltage of the first output approaches a preset voltage value.

Abstract: An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.

Abstract: In a solid-state imaging element provided with a differential pair of transistors, noise of a signal from the differential pair is reduced. The semiconductor integrated circuit includes a pixel circuit and a pair of TFETs (Tunnel Field Effect Transistors). In the semiconductor integrated circuit, the pixel circuit photoelectrically converts incident light to generate a pixel signal. Further, in the semiconductor integrated circuit, the pair of TFETs amplifies the difference between the pixel signal generated by the pixel circuit and a predetermined reference signal that changes with time, and outputs the amplified difference as a differential amplification signal.