Abstract: An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.

Abstract: A slew rate acceleration circuit in a buffer circuit, is configured at least to detect a current flowing through a load stage of the buffer circuit, compare a value of the detected current with a reference value, and supply an adjusting driving voltage to an output stage of the buffer circuit based on results of the comparison for increasing a slew rate of the buffer circuit.

Abstract: In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Abstract: A power amplifier circuit according to the present disclosure includes an amplifier circuit serving as a differential amplifier circuit configured to be activated by a supply voltage that is variable in accordance with amplitude of a signal, a bias circuit configured to output a bias to be supplied to the amplifier circuit, and first and second dispersion circuits respectively provided for a pair of differential signals outputted from the amplifier circuit and configured to control dependence of gain of the differential amplifier circuit on the supply voltage.

Abstract: Provided is an image sensor including: a pixel section configured to include a plurality of pixels arranged therein; and an AD conversion unit configured to perform analog-to-digital (AD) conversion on a pixel signal on the basis of a result of comparison between a first voltage of a signal, which is obtained by adding, via capacitances, the pixel signal of the pixel and a reference signal that linearly changes in a direction opposite to the pixel signal, with a second voltage serving as a reference.

Abstract: A constant voltage generator circuit includes a first amplifier circuit that drives a transistor controlling an output current based on a reference voltage; a second amplifier circuit that drives the transistor based on the reference voltage from the power source; a protection circuit that limit an output current flowing through the load from the transistor; and a control circuit that controls operation of the second amplifier circuit. The control circuit controls the second amplifier circuit to operate or not to operate based on a relationship between the output current and predetermined first or second threshold. The second amplifier circuit further includes a first operation voltage potential fixing circuit that fixes an operation voltage potential of an internal node of the second amplifier circuit during non-operation thereof.

Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.

Abstract: Disclosed is an amplifier having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a slew rate improvement circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a first slew rate improvement circuit, and a second slew rate improvement circuit.

Abstract: An interface circuit that interfaces a digital-to-analog converter (DAC) to a vertical-cavity surface emitting laser. The apparatus includes a first cascode amplifier that receives as input positive and negative differential outputs of the DAC and provides a positive amplified output and a negative amplified output, and a second cascode amplifier having a positive input and a negative input. The positive input of the second cascode amplifier being coupled to the positive amplified output of the first cascode amplifier. The second cascode amplifier is configured to generate a positive amplified current and a negative amplified current at a negative amplified output. The positive amplified current and the negative amplified current are combined and a resulting output current is provided as input to an anode of the laser. A transformer is coupled between the negative amplified output of the first cascode amplifier and the negative input of the second cascode amplifier.

Abstract: A receiver circuit has a first stage circuit having a first stage input and a first stage output, the first stage output setting a first stage common mode voltage; a second stage circuit having a second stage input connected to the first stage output, and a second stage output setting a second stage common mode voltage; and a buffer circuit having a trip point voltage, connected to the second stage output. The first stage circuit can include circuit elements configured to establish the first stage common mode voltage so that the second stage common mode voltage matches the trip point voltage. The second stage circuit can include a self-biased amplifier.

Abstract: An amplifier circuit comprises a variable degeneration circuit connected to emitter terminals of transistors, and a variable negative capacitance circuit connected to differential output signal terminals. The variable degeneration circuit includes a variable capacitor and a resistor. The variable negative capacitance circuit, which is a variable current source, includes a transistor, a capacitor, and a variable current source. The variable negative capacitance circuit includes transistors, a capacitor, and variable current sources.

Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.

Abstract: A circuit (to shape a follower voltage for a follower circuit) includes a tie-low circuit and an anti-noise circuit. The tie-low circuit is connected between a follower node and a first reference voltage. The tie-low circuit is responsive to a second reference voltage. The follower node is connectable to the follower circuit. The anti-noise circuit is connected between the follower node and the second reference voltage. The anti-noise circuit is configured to protect the follower voltage at the follower node from otherwise being distorted by a noise voltage being coupled capacitively to the follower node.

Abstract: A system may include a first power domain defined by a first supply rail and a first ground rail, a second power domain defined by a second supply rail and a second ground rail, and a configurable switch coupled between the first ground rail and the second ground rail such that when the configurable switch is enabled, the first ground rail and the second ground rail are electrically shorted to one another and when the configurable switch is disabled, the first ground rail and the second ground rail are electrically isolated from one another.

Abstract: A tapped transmission line for distributing an electrical signal, such as an RF signal, to multiple modules, and/or aggregating signals from multiple modules. Embodiments of the invention provide a tapped transmission line based on a transmission-line medium along which tap elements are dispersed, so that the tap elements have a predominantly capacitive loading of the transmission-line medium. Methods for compensating the loss of the transmission-line medium are presented as well. Applications for distribution of transmitted signals, of local oscillator signals, and to aggregation of signals from multiple oscillators are disclosed. The invention is particularly applicable to integrated circuits (IC, ASIC, RFIC), and to multichannel RF systems such as phased array and MIMO systems.

Abstract: In a described example, a circuit includes a first bipolar junction transistor (BJT) having a first base, a first emitter and a first collector. A second BJT has a second base, a second emitter and a second collector, in which the first collector is coupled to the second collector. A bandgap core circuit has first and second core inputs and a bandgap output. The first core input is coupled to the first emitter, the second core input is coupled to the second emitter, and the first and second bases are coupled to the bandgap output.

Abstract: A voltage reference circuit included in a computer system includes two bipolar devices with two different current densities which are used to generate two base-emitter voltages, which are scaled using divider circuits. The voltage reference circuit also includes a feedback circuit that generates a reference voltage using the scaled base-emitter voltages and a feedback signal. The feedback signal is generated using the reference signal and combined with one of the scaled base-emitter voltages to compensate for variations in load current from the reference circuit.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: The amplifier includes an input circuit configured to convert an input signal into a current; an output circuit comprising at least one switching element for reducing a voltage change of an output end of the input circuit and configured to provide an output signal; and a biasing circuit connected to the at least one switching element to form a feedback loop for reducing the voltage change of the output end of the input circuit.

Abstract: A constant current generation circuit for optocoupler isolation amplifier and a current precision adjustment method are provided. The constant current generation circuit includes a start circuit, a current generation circuit and a precision adjustment and output circuit integrated into a same substrate. The start circuit can generate and output a first start current and a second start current. The current generation circuit includes a negative temperature change rate current generation circuit connected to a first start current output and a positive temperature change rate current generation circuit connected to a second start current output. The precision adjustment and output circuit outputs constant current meeting application requirements of optocoupler isolation amplifier by adjusting proportional precision of two currents output from a current generation circuit.

Abstract: Disclosed is an amplifier capable of minimizing shortcircuit current of an output stage of a buffer upon transition of an output voltage while having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a short-circuit current minimization circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a short-circuit current minimization circuit, and a slew rate improvement circuit.

Abstract: Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.

Abstract: A semiconductor integrated circuit is capable of electrically connecting to a capacitance variable capacitor whose electrostatic capacitance changes corresponding to an environmental change between a first and a second capacitances and determines whether the electrostatic capacitance of the capacitance variable capacitor has changed to exceed a reference capacitance value.

Abstract: The present invention discloses a circuit for improving linearity and channel compensation of PAM4 receiver analog front end, comprising a first stage and a second stage, the first stage comprising first to twentieth transistors, a first resistor, a pair of second resistors, a pair of first capacitors, and a pair of second capacitors. In the first stage circuit, the ninth and tenth transistors are directly coupled to the ground, eliminating the electrical connection to the bias current source. The Input terminals of the ninth and tenth transistors are coupled to the output signals of the preceding nineteenth and twentieth transistors, so that the ninth and tenth transistors serve as both input pairs and current source transistors. The overall current is limited by the thirteenth and fourteenth transistors, which results in a lower power supply voltage for the first stage consisting of the ninth through fourteenth transistors.

Abstract: A sensor interface circuit (5) for an amperometric electrochemical sensor (3). The circuit includes: a current-to-voltage converter (9, Rf) connected to a first terminal (WRK) of the sensor (3) for converting an electric current through the sensor (3) to a voltage at an output terminal (10) of the current-to-voltage converter (9, Rf); a first amplifier (7) connected between a second terminal (REF) and a third terminal (CNTR) of the sensor (3) for maintaining a substantially fixed voltage difference between the first and second terminals (WRK, REF) of the sensor (3); a power supply (11) for powering the voltage converter (9, Rf) and for powering a first portion (31) of the first amplifier (7); and a negative voltage converter (17) configured to power a second portion of the first amplifier (7) through its low-side supply terminal (41), while a high-side supply terminal (39) of the second portion of the first amplifier (7) is configured to be connected to the power supply (11).

Abstract: A system includes an instrumentation amplifier (INA) including a first transistor coupled to a first input node, and a second transistor coupled to a second input node. The INA also includes a resistor coupled between the first transistor and the second transistor. The INA includes a gain resistor network coupled to the resistor and to the first and second transistors, where the gain resistor network includes two or more gain resistors. The system also includes a voltage to current converter, where the voltage to current converter is coupled to the resistor and the gain resistor network.

Abstract: A trans-impedance amplifier (TIA) may include an input stage and an output driving stage. The input stage may include a pair of input PMOS transistors, a pair of input NMOS transistors, and a pair of differential voltage input nodes. The output driving stage may include a pair of output circuits, each may include a first pair of PMOS and NMOS transistors electrically connected in parallel, a second pair of PMOS and NMOS transistors electrically connected in series, a pair of capacitors electrically connected in series, a differential output node, a third PMOS transistor, and a fourth pair of NMOS transistors cross-coupled between the pair of output circuits of the output driving stage. The structure can lead to a reduced noise level and a reduced peak transient current level of the TIA.

Abstract: A network TAP includes four serial transceivers on a printed circuit board. Each serial transceiver has a medium-dependent interface and a serial differential interface that includes a differential input and a differential output. A passive tap circuit arrangement is configured to be operative at up to 10 Gbps or a higher data rate and configures the differential output signal from the differential output of the first serial transceiver as two single-ended signals that are received respectively by the respective differential inputs of the second and third serial transceivers. It also configures the differential output signal from the differential output of the second serial transceiver as two single-ended signals that are received respectively by the respective differential inputs of the first and fourth serial transceivers. In one embodiment according to the present invention, the four serial transceivers are pluggable transceiver modules.

Abstract: The present disclosure relates to a magnetic field sensor circuit including at least one coil for measuring a magnetic field, a first stage amplifier circuit coupled to the coil and having a first transfer function with a pole at a first frequency, and a second stage amplifier circuit coupled to an output of the first stage amplifier circuit and having a second transfer function with a zero at the first frequency. In some embodiments, a temperature dependent frequency drift of the pole of the first transfer function corresponds to a temperature dependent frequency drift of the zero of the second transfer function.

Abstract: An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal. The bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. None of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage is directly set by the input signal of the single-stage amplifier.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: Differential amplifier circuitry including: first and second main transistors of a given conductivity type: and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

Abstract: A differential operational transconductance amplifier, or DOTA, intended to be used in zero-drift precision operational amplifiers as chopper amplifier stage is disclosed. The DOTA is configured to function with a low-voltage power supply and to have good performance based on circuitry configured to provide a constant gain over a range of common-mode voltages, or VCM. The DOTA further includes bias circuitry configured to respond to the common mode voltage in order to prevent large currents, which can result from the constant gain circuitry, from negatively affecting performance. The DOTA further includes current sources that are configured to prevent temperature variations from negatively affecting performance. The DOTA further includes VCM-driven bias voltages used to optimize the operating point of the differential output stage. The DOTA uses input and input replica transistors having medium threshold voltage, which results in capability to operate at low supply voltages.

Abstract: In an embodiment, a method includes receiving, between a positive input terminal and a negative input terminal, a supply voltage, receiving a data signal, generating, by a voltage generator in a branch of a plurality of branches, a branch current as a function of a respective driving signal and of a regulated voltage, each branch connected between the positive input terminal and the negative input terminal, selectively activating the voltage generator as a function of a respective enabling signal and providing, between a positive output terminal and a negative output terminal, the regulated voltage to one or more driving circuits.

Abstract: Examples are disclosed herein that relate to automatically limiting an output current of a voltage regulator circuit responsive to detecting that the voltage regulator is in a current overload mode. In one example, a voltage regulator circuit includes an amplifier stage and a current limiter stage electrically connected to an output of the amplifier stage. The amplifier stage is configured to output a DC voltage based on a reference voltage and feedback from an output voltage. The current limiter stage is configured to operate in a quiescent mode and an overload mode. In the quiescent mode, the current limiter stage is configured to operate as a buffer stage that forms a closed feedback loop to an input of the amplifier stage. In the overload mode, the current limiter stage is configured to act as a current source that clamps an output current to a designated current.

Abstract: Provided is a track-and-hold circuit capable of reducing the power consumption of a differential amplifier circuit while preserving the broadband nature (without narrowing the bandwidth). In the track-and-hold circuit 1 including a differential amplifier circuit 10, a switch circuit 20, and a hold capacitor C21, the differential amplifier circuit 10 includes a first resistor R11 having one end connected to a collector electrode of a first transistor Q11 constituting a differential pair, a second resistor R12 having one end connected to the collector electrode of a second transistor Q12 constituting the differential pair, and a third resistor R13 to which the other end of the first resistor R11 and the other end of the second resistor R12 are connected and which is connected between the other ends and a power supply VCC.

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

Abstract: A system includes a power supply source and a power control circuit coupled to the power supply source, in which the power control circuit includes a pass field-effect transistor (FET). The system also includes a short-to-ground protection circuit coupled to an output of the pass FET. The short-to-ground protection circuit includes a sense circuit configured to detect when a magnitude and a change rate of a voltage drop at the output of the pass FET is greater than respective thresholds. The short-to-ground protection circuit also includes a control node at the output of the sense circuit. The sense circuit is configured to induce a control current at the control node in response to the magnitude and the change rate of a voltage drop at the output of the pass FET being greater than respective thresholds. The control current is used to turn off the pass FET.

Abstract: A filter can perform two filtering processes. The filter includes a switching circuit, a first filter circuit, and a second filter circuit. The first filter circuit is coupled to the switching circuit. The second filter circuit is coupled to the switching circuit. The first filter circuit performs a first filtering process on an input signal according to a state of the switching circuit. The first filter circuit and the second filter circuit work together to perform a second filtering process on the input signal according to the state of the switching circuit.

Abstract: A SerDes system is provided. The SerDes system includes channel circuits, a PLL circuit, first and second buffers, and first and second capacitors. Each channel circuit is coupled to the first and second clock lines. The PLL circuit generates a first differential signal including first and second clock signals. The first buffer buffers the first clock signal. The second buffer and buffers the second clock signal. The first capacitor receives the buffered first clock signal and outputs a third clock signal to the first clock line. The second capacitor receives a buffered second clock signal and outputs a fourth clock signal to the second clock line. A swing of a second differential signal comprising the third clock signal and the fourth clock signal is smaller than a swing of the first differential signal.

Abstract: A data transmission circuit includes: a main driver circuit suitable for driving data to an output line; an amplitude equalization window generator circuit suitable for detecting the data transitioning from a first level to a second level; an auxiliary driver circuit suitable for driving the output line with the second level in response to a detection result of the amplitude equalization window generator circuit; and a phase equalization window generator circuit suitable for detecting whether the data consecutively has the first level, wherein the main driver circuit changes a time point of driving the data in response to a detection result of the phase equalization window generator circuit.

Abstract: An impedance circuit includes a first impedance terminal, a second impedance terminal, a first transistor, a second transistor, a low frequency signal blocking element, and a current-voltage transform circuit. The first transistor is coupled to the first impedance terminal, and controlled by a first voltage. The second transistor is coupled to the first impedance terminal, and controlled by a second voltage. The low frequency signal blocking element is coupled to the first transistor and the second impedance terminal. The current-voltage transform circuit is coupled to the first impedance terminal. The current-voltage transform circuit adjusts a terminal voltage at the first terminal of the current-voltage transform circuit according to a current flowing through the current-voltage transform circuit. The impedance circuit provides impedance between the first and the second impedance terminals according to the terminal voltage and the first voltage.

Abstract: A differential comparator circuit is provided that includes a differential input pair, an active load, a pair of cross voltage generation devices and a pair of switches. The differential input pair has a pair of input terminals and a pair of first connection terminals. The active load has a pair of second connection terminals. The cross voltage generation devices are electrically coupled between the first connection terminals and the second connection terminals, wherein the cross voltage generation devices are configured to be electrically activated to establish a cross voltage therebetween in a reset phase and electrically deactivated to become a short circuit in an operation phase. The switches are configured to electrically couple the pair of input terminals respectively to the pair of first connection terminals in the reset phase and not electrically couple the pair of input terminals respectively from the pair of first connection terminals.

Abstract: In an embodiment, an amplifier includes first, second, and third stages, and a feedback network. The first stage has a first passband and is configured to generate a first output signal in response to first and second input signals, and the second stage has a second passband that is higher in frequency than the first passband and is configured to generate a second output signal in response to third and fourth input signals. The third stage has a first input node coupled to receive the first output signal, a second input node coupled to receive the second output signal, and an output node. And the feedback network is coupled between the second input node and the output node of the third stage. For example, where the first, second, and third stages are respective operational-transconductance-amplifier stages, such an amplifier may be suitable for low-power applications.

Abstract: A radio-frequency module includes a substrate, a low-noise amplifier circuit being a first amplifier circuit arranged in a first area in the substrate, a power amplifier circuit being a second amplifier circuit arranged in a second area in the substrate, and a duplexer being a component arranged between the first area and the second area in the substrate and having a heat generating property lower than that of the power amplifier circuit. The low-noise amplifier circuit includes a bias circuit configured to generate a bias current dependent on temperature characteristics of a first diode, a voltage generating circuit configured to generate a voltage dependent on temperature characteristics of a second diode as an operating voltage for the bias circuit, and an amplifier circuit configured to operate at an operating point determined by the bias current.

Abstract: According to one embodiment, the amplifier circuit includes a first and second differential amplifier. The first differential amplifier includes first and second transistors, a first current source, and a second current source that is configured to supply a current to the first and second transistors via a first switch element. The second differential amplifier includes third and fourth transistors, a third current source, and a fourth current source that is configured to supply a current to the third and fourth transistors via a second switch element. A first signal is input to the first and third transistors. The first switch elements are controlled by third and fourth signals, respectively. The third signal and the fourth signal are complementary.

Abstract: An apparatus and method are provided. The apparatus includes a multiplexer, including first, second, and third inputs, and an output; a first transistor, including a gate connected to the multiplexer, and first and second terminals; a first variable capacitor, including a first terminal connected to the first transistor, a second terminal, and an input; a first inductor, including a first terminal connected to the first transistor, and a second terminal connected to the second terminal of the first variable capacitor; a second transistor, including a gate connected to the output of the multiplexer, a first terminal, and a second terminal connected to the second terminal of the first inductor; a second inductor mutually coupled to the first inductor, including a first and second terminals; and a balun-bias switch, including first, second, and third inputs, and an output connected to the second terminal of the second inductor.

Abstract: A differential amplifier includes a pair of cascode amplifiers. A voltage clamp is coupled to the pair of cascode amplifiers.

Abstract: A power amplifier system includes a differential power amplifier and a bias circuit. The differential power amplifier is arranged for receiving a differential input pair to generate an output signal. The bias circuit is arranged for generating a bias voltage to bias the differential power amplifier, and the bias circuit comprises a source follower for receiving a reference voltage to generate the bias voltage.