Abstract: A differential amplifier includes a pair of cascode amplifiers. A voltage clamp is coupled to the pair of cascode amplifiers.

Abstract: A power amplifier system includes a differential power amplifier and a bias circuit. The differential power amplifier is arranged for receiving a differential input pair to generate an output signal. The bias circuit is arranged for generating a bias voltage to bias the differential power amplifier, and the bias circuit comprises a source follower for receiving a reference voltage to generate the bias voltage.

Abstract: Provided herein are amplifiers, such as buffers, with increased headroom. An amplifier stage includes a follower transistor and current source configured to receive a power supply voltage comprising an alternating current component and a direct current component. The alternating current component of the power supply voltage has substantially the same frequency and magnitude as the input signal received by the follower transistor. In radio frequency (RF) and intermediate frequency (IF) buffer applications, for example, the increased headroom can allow for linear buffering of an input signals with increased amplitude so that the output power one decibel (OP1dB) compression point can be increased.

Abstract: A buffer is provided where a part of the buffer is implemented in switched capacitor or other analog discrete time processing circuitry and a dynamic response characteristic, such as an effective gain or charge transfer coefficient between the input stage and an output stage is digitally controllable. This means that the buffer can be driven as if it was a system controlled by, for example a three (3) term controller, giving rise to greater, digital flexibility in tailoring the buffer's transient response.

Abstract: One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Abstract: A switching amplifier provided, at a minimum, with: a first input transistor into which one of two input signals that operate in a complementary manner is input; a first cascode transistor cascade-connected between the first input transistor and a power supply; a second input transistor into which the other of the two input signals is input; and a second cascode transistor cascade-connected between the second input transistor and the first input transistor; the switching amplifier extracting an output signal, a connection point between the first input transistor and the second cascode transistor being used as an output terminal; wherein a first potential limiting circuit and a second potential limiting circuit for limiting the potential fluctuation range are respectively connected to the input terminal of the first cascode transistor and the input terminal of the second cascode transistor.

Abstract: An electronic circuit including a current conveyor connected to a load is provided. The load delivers at least one first voltage output and one second voltage output. Such a circuit is noteworthy in that the second voltage output has what is called a non-linear behavior relative to the magnitude of the input current of the electronic circuit in a given range.

Abstract: A charge pump comprises a charge pump circuit with bipolar switching devices with a common emitter. A collector line which comprises a first current source connects to the high potential provider. An emitter line connects the common emitter to a low potential provider and comprises a second current source. The output is provided by or connected to the collector of the second bipolar switching device and provides said output voltage. A driving stage circuit applies a charge pump circuit driving signal across the bases of the bipolar switching devices and controls the charge pump circuit driving signal in accordance with a driving stage input signal. The driving stage circuit effects a shift of a DC operating point of the charge pump circuit driving signal as an increasing function of the output voltage function of the output voltage of the charge pump circuit.

Abstract: A current source circuit flowing an output current to at least one detection element including a first terminal to which a first voltage is supplied and a second terminal being connected to the current source circuit includes a reference resistance, a current mirror circuit including at least one first transistor and at least one second transistor, and a control circuit controlling a voltage of a common wire that is connected to a terminal provided at the first transistor and a terminal provided at the second transistor such that a voltage of a terminal provided at the reference resistance comes to be equal to a reference voltage.

Abstract: Methods and systems for compensating for temperature variation in the performance of electronic circuits and systems are disclosed. In some embodiments, the systems are configured to store compensation parameters determined in calibration, where the compensation parameters are used by the systems to modify performance. In some embodiments, the systems are part of an automatic test equipment (ATE) system.

Abstract: To provide a current detection circuit capable of suppressing the occurrence of a large potential difference between input terminals of a differential amplifier circuit, and preventing degradation of input transistors. A differential amplifier circuit is equipped with a clamp circuit which limits gate-source voltages of a pair of PMOS transistors each having a bulk and a source connected to each other with the sources of the pair of PMOS transistors as input terminals.

Abstract: A differential amplifier circuit and display drive circuit having the same are disclosed herein. In one example, a differential amplifier circuit includes a differential pair transistor configure to receive a differential input signal. A current source is connected in series to the differential pair transistor and an output transistor that drives an output terminal on the basis of the differential input signal. The output transistor is configured to increase a current value of a current source on the basis of a timing at which a voltage level of the output terminal is caused to transition. The output transistor is configured to drive the output terminal only during a period in which the output terminal is caused to transition, and thus a slew rate is improved by increasing a bias current of the differential pair transistor in the period.

Abstract: Described herein is an electronic device. The electronic device includes a unity gain buffer having an input coupled to an input node to receive an input voltage and an output coupled to an output node. A current sink circuit operates in a sleep mode in an absence of a sink current flowing into the output node, and operates in a sinking mode to sink the sink current from the output node to a reference supply node when the sink current flows into the output node.

Abstract: Provided is a technology capable of preventing arithmetic operation accuracy from deteriorating even when a bipolar transistor used to form a Gilbert multiplier core has poor characteristics. A correction current generating circuit (3) uses a constant current source (301) to feed a constant current I0 to an emitter of a bipolar transistor (Q7) being a first replica transistor having the same current gain ? as bipolar transistors (Q1 to Q4) that form the Gilbert multiplier core (101), to generate a current of ?·I0 on a collector side thereof. The current is output as a correction current ?·I0, and is added to each of one of input signals (±K1·Vy) of the Gilbert multiplier core (101) as a bias current, to thereby eliminate influence of the current gain ? on an output signal being a multiplication result.

Abstract: Disclosed is a compensation circuit for a common voltage according to a gate voltage, which compensates the common voltage in accordance with variation in gate high voltage, to obtain an optimal common voltage. The compensation circuit includes a divider to divide a gate high voltage, an adder to add a fed-back common voltage to a voltage output from the divider, and a differential amplifier to differentially amplify a voltage output from the adder, and to output the amplified voltage as a compensated common voltage.

Abstract: A high slew rate operational amplifier including an input terminal, an output terminal, and at least one slew-rate enhancing circuit is disclosed. Each slew-rate enhancing circuit includes a first stage enhancing unit and a second stage enhancing unit. The first stage enhancing unit is coupled between the input terminal and the output terminal. The first stage enhancing unit and the second stage enhancing unit are coupled. The slew-rate enhancing circuit has a threshold voltage and the threshold voltage is related to the size of the first stage enhancing unit. When the threshold voltage is driven, the slew-rate enhancing circuit will rapidly start the second stage enhancing unit to perform a slew rate compensation on the high slew rate operational amplifier.

Abstract: A pixel compensation circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a switch unit and a light emitting diode. The first transistor, the third transistor, the fourth transistor, the fifth transistor, and the switch unit are used to receive a respective switch signal. The pixel compensation circuit can compensate a threshold voltage of transistor automatically; and consequentially a driving current of light emitting diode is prevented from being affected by the change of the threshold voltage or the voltage drop of the light emitting diode.

Abstract: A differential amplifier with cascade transistors connected in series to switching transistors is disclosed. The base bias of the cascade transistors is set higher than the output LOW level of the cascade transistors by a preset amount of 0.1 to 0.2V, or lower than the input HIGH level of the switching transistors by the preset amount adding to a forward voltage of a junction diode, to provide a discharge current of the base-emitter junction Cbe from the bias control, or from the upstream stage to drive the differential circuit.

Abstract: A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor. Each of the multiplexers has an input coupled to one of the monitor nodes and a respective node of the amplifier circuit. In operation, the multiplexers selectively insert the degradation test transistor into either the integrated circuit or the amplifier circuit so that when inserted into the integrated circuit the degradation test transistor is subjected to stress degradation voltages in the integrated circuit. When the degradation test transistor is inserted into the amplifier circuit, an output signal is generated that is indicative of stress degradation of the integrated circuit.

Abstract: A voltage measurement apparatus is provided that includes: a potential attenuator configured to be electrically connected between first and second conductors, which are electrically coupled to a source, wherein the potential attenuator includes a first impedance and a reference impedance arrangement in series with each other, wherein the reference impedance arrangement has an electrical characteristic that can be changed in a known fashion; and further including a processing arrangement configured to acquire at least one signal from the reference impedance arrangement, the at least one signal reflecting change of the electrical characteristic in the known fashion; and to determine a voltage between the first and second conductors in dependence on the fashion in which the electrical characteristic is changed being known and the at least one signal.

Abstract: An operational amplifier circuit includes: a first differential amplifier section containing a P-type differential pair of P-type transistors; a second differential amplifier section containing an N-type differential pair of N-type transistors; an intermediate stage connected with outputs of the first and second differential amplifier sections and containing a first current mirror circuit of P-type transistors, and a second current mirror circuit of N-type transistors; and an output stage configured to amplify an output of the intermediate stage in power. The first differential amplifier section includes a first current source and a first capacitance between sources of the P-type transistors of the P-type differential pair and a positive side power supply voltage. The second differential amplifier section includes a second current source and a second capacitance between sources of the N-type transistors of the N-type differential pair and a negative side power supply voltage.

Abstract: A method for reducing the non-linearity effect of a digital-analog converter on an electronic interface circuit of a capacitive sensor. The electronic circuit includes an amplifier connected to the common electrode by a switching unit, a logic unit connected to the amplifier for supplying first and second digital measuring signals, and a digital-analog converter for supplying a measuring voltage to the electrodes. The method includes firstly biasing the capacitor electrodes by the measuring voltage, then biasing the fixed electrode of the first capacitor at a regulated voltage and the fixed electrode of the second capacitor at a low voltage, then biasing the capacitor electrodes by the measuring voltage, and finally biasing the fixed electrode of the first capacitor at a low voltage and the fixed electrode of the second capacitor at a regulated voltage.

Abstract: Differential amplifier circuits for LDMOS-based amplifiers are disclosed. The differential amplifier circuits comprise a high resistivity substrate and separate DC and AC ground connections. Such amplifier circuits may not require thru-substrate vias for ground connection.

Abstract: Differential power amplifier circuitry includes a differential transistor pair, an input transformer, and biasing circuitry. The base contact of each transistor in the differential transistor pair may be coupled to the input transformer through a coupling capacitor. The coupling capacitors may be designed to resonate with the input transformer about a desired frequency range, thereby passing desirable signals to the differential transistor pair while blocking undesirable signals. The biasing circuitry may include a pair of emitter follower transistors, each coupled at the emitter to the base contact of each one of the transistors in the differential transistor pair and adapted to bias the differential transistor pair to maximize efficiency and stability.

Abstract: A clamping circuit for a class AB amplifier includes a reference voltage circuit, four NPN Darlington transistors having inputs coupled to the reference voltage circuit, and outputs for providing four clamped voltages and a split NPN Darlington transistor having an input coupled to the reference voltage circuit, and four separate outputs for providing four AC ground voltages.

Abstract: An amplifier includes a first transformer configured to output first differential signals, a first differential amplifier coupled to the first transformer, a second transformer coupled to the first differential amplifier, a second differential amplifier coupled to the second transformer, a third transformer configured to transform second differential signals output from the second differential amplifier to a single-ended output signal, and a first bias circuit configured to supply a first bias voltage to a first secondary coil of the first transformer, wherein the first bias circuit sets the first bias voltage to a voltage greater than or equal to a first voltage based on the input signal in a first operating area where power of the output signal is greater than or equal to a first power so that power-gain characteristics of the output signal become closer to characteristics where gain of the output signal becomes constant.

Abstract: An amplifier circuit includes an input terminal and an output terminal. A current sinking transistor includes a first conduction terminal coupled to the output terminal and a second conduction terminal coupled to a reference supply node. A voltage sensing circuit has a first input coupled to the input terminal and a second input coupled to the output terminal. An output of the voltage sensing circuit is coupled to the control terminal of the current sinking transistor. The voltage sensing circuit functions to sense a rise in the voltage at the output terminal which exceeds the voltage at the input terminal, and respond thereto by activating the current sinking transistor.

Abstract: Provided is a power amplifier which includes: a first transistor and a second transistor each having a first end connected to a first power source supplying a first voltage and to which signals having a same size but opposite polarities are input; a third transistor and a fourth transistor having first ends respectively connected to the first ends of the first transistor and the second transistor; and a fifth transistor having a first end connected to second ends of the third and fourth transistors and controlling oscillation of the third or fourth transistor.

Abstract: A differential amplifier is described that provides a high common mode rejection ration (CMRR) without requiring the use of precisely matched components. One variation employs a method of noise reduction to increase the SNR of the device. The differential amplifier may be used in an apparatus for measuring biopotentials of a patient, such as an electrode for measuring brain activity. The electrodes can communicate the measured biopotentials with a remote system for further processing, while providing electrical isolation to the patient.

Abstract: An operational transconductance amplifier for connection with multiple input voltage sources includes a resistance simulation unit, two current cancellation units, a first differential output unit, two current division units, and a second differential output unit. The resistance simulation unit is to simulate resistance. The two current cancellation units are to receive and convert the voltage of the input voltage sources into two first currents. The two first currents flow to two first output ends of the first differential output unit, respectively. The two current division units are to receive and convert the voltage of the input voltage sources into two second currents. The two second currents flow to two second output ends of the two second differential output units, respectively, and include the same potential as the two first currents.

Abstract: Embodiments and methods herein operate as two-stage voltage controlled current sources (i.e., dynamic current sources) operating in class AB mode. Phase-delayed current injection circuits are associated with first-stage bias, second-stage bias, or both. The current injection circuits operate to quickly re-charge inter-stage parasitic capacitance associated with the active side of the class AB dynamic current source shortly after that side becomes inactive. Doing so quickly dissipates an otherwise slowly-decaying residual drive signal to prevent the output stage from continuing to conduct after the associated side of the current source becomes inactive. Excessive current consumption and possible destructive operation of the output stage are mitigated as a result.

Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a wa

Abstract: A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as “non-Foster circuits.” The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).

Abstract: Embodiments of the invention are generally directed to improving the slew rate of an amplifier as the amplifier charges or discharges a capacitive load. In one embodiment, the amplifier is coupled to a slew-enhancing circuit which uses a control signal from the amplifier to aid the amplifier when charging or discharging the load. For example, the control signal may be an internal voltage used by the amplifier to control circuit elements within the amplifier. By routing the control signal to the slew-enhancing circuit, the control signal biases the circuit elements within the slew-enhancing circuit to source a boost current when charging the capacitive load or sink the boost current when discharging the capacitive load.

Abstract: A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.

Abstract: Biasing methods and devices for amplifiers are described. The described methods generate bias voltages proportional to the amplifier output voltage to control stress voltages across transistors used within the amplifier.

Abstract: Low power low noise input bias current compensation for an amplifier input stage is provided by recycling the tail current of the differential pair transistors. A local amplifier regulates the tail current and buffers the base current of the tail current transistor, which is mirrored back to the input transistors to provide input bias current compensation.

Abstract: An operational amplifier includes a selective differential stage including a first current mirror and a current distribution circuit. First and second legs of the first current mirror are responsive to current in first and second paths of the current distribution circuit, which distributes a tail current in response to a first signal received by a first input of the operational amplifier. Current in a first path of a selection circuit in the second path of the current distribution circuit is responsive to a second signal received by a second input of the operational amplifier. Current in the second path of the selection circuit is responsive to a third signal received by a third input of the operational amplifier. An output stage generates an output signal responsive to a difference between the first signal and one of the second and third signals.

Abstract: Exemplary embodiments are directed to systems, devices, and methods for enhancing a telescopic amplifier. An amplifier may include a differential pair of input transistors including at least one transistor configured to receive a first input and at least one other transistor configured to receive a second input. The amplifier may further include a cascode circuit including a first pair of transistors coupled to the at least one transistor of the differential pair to form a first plurality of current paths configured to generate a first output. The cascode circuit may also include a second pair of transistors coupled to the at least one other transistor of the differential pair to form a second plurality of currents paths configured to generate a second output.

Abstract: An operational amplifier circuit includes an output stage circuit. The output stage circuit includes a first and a second output transistors, a capacitor unit, and a switch unit. A drain of the first output transistor is coupled to a drain of the second output transistor via an output terminal of the output stage circuit. The switch unit is coupled between gates of the first and the second output transistors and coupled to a first terminal of the capacitor unit. A second terminal of the capacitor unit is coupled to the output terminal of the output stage circuit. The switch unit determines to conduct a signal transmission path between the gate of the first output transistor and the first terminal of the capacitor unit or conduct a signal transmission path between the gate of the second output transistor and the first terminal of the capacitor unit according to a control signal.

Abstract: An amplifier for an output buffer includes an operational amplifier including a first input terminal, a second input terminal, and an output terminal, the operational amplifier is configured to generate an input bias current and amplify a voltage difference between signals applied to the first input terminal and the second input terminal, and to output the amplified voltage difference; and a self-bias circuit connected to the first input terminal and the second input terminal, the self-bias circuit is configured to generate first and second current paths when the voltage difference is equal to or greater than a predetermined voltage, to generate a tail current on the first or second current path, and to add the generated tail current to the input bias current of the operational amplifier, wherein the second input terminal is connected to the output terminal.

Abstract: A differential amplifier circuit that includes a negative resistor in parallel to synthesize a larger source resistance is disclosed. In one or more implementations, a differential amplifier circuit includes a first transistor and a second transistor. The first transistor is configured to receive a first differential input and the second transistor is configured to receive a second differential input. The differential amplifier circuit also includes a third transistor and a fourth transistor that form a pair of cross-coupled transistors coupled to the first transistor and the second transistor. The pair of cross-coupled transistors are configured to generate a negative impedance at an output node, and the negative impedance, combined with an impedance of the first transistor, is configured to generate a sufficient termination impedance for a transmission line electrically connected to the output node.

Abstract: A drive circuit of an organic light emitting display and an offset voltage adjustment unit thereof are provided. The offset voltage adjustment unit can be used in an operational amplifier of the drive circuit having a differential input stage, a bias stage, and an output stage. The offset voltage adjustment unit coupled between the bias stage and a ground including a resistor string and a plurality of latch units. The resistor string has a first-end, a second-end, and a plurality of resistors series-connected between the first-end and the second-end forming a plurality of junctions. The latch units are coupled between the junctions and the ground, respectively. The latch units are sequentially conducted to adjust a bias current of the bias stage according to a control signal. The latch units enter a latch state upon receiving a latch signal to calibrate an output offset voltage of the operational amplifier.

Abstract: A signal receiver includes a current source providing a current having a current value, a pair of active input devices, and a pair of resistors. Each active input device includes a control node, a first conduction node, and a second conduction node. One of the control nodes receives an input signal. The first conduction nodes are connected to each other and receive the current. One of the second conduction nodes serves as an output node. The active input devices output an output signal to a core circuit according to the current and the input signal. Each resistor has a resistance value. A target voltage value is determined according to the resistance value and the current value, such that a voltage swing of the output signal is limited within the target voltage value, and an operating voltage of the core circuit is substantially equal to the target voltage value.

Abstract: A differential circuit with a function to compensate the gain enhancement due to the self-heating of the transistor is disclosed. The differential circuit includes an equalizer unit coupled with one of paired transistors. The other of the paired transistor receives the input signal to be amplified. The base level, or the base-emitter bias, is oppositely modulated by the input signal through the common emitter, which causes the modification of the base current. The equalizer unit reduces the variation of the base level only in low frequencies where the self-heating effect of the transistor appears.

Abstract: An apparatus comprises a differential amplifier circuit and a current source. The differential amplifier circuit is configured to receive a voltage at an input, wherein the differential amplifier circuit generates an output voltage having a magnitude proportional to the received voltage over a voltage range to be measured at a specified output common mode voltage. The current source is electrically connected to an input of the differential amplifier circuit and is configured to subtract a midpoint of a voltage range of the battery voltage to be measured at the input of the differential amplifier, wherein a circuit supply voltage provided to the differential amplifier circuit and the current source is less than the voltage at the input.

Abstract: A differential amplifier provides an amplifier circuit including two differential pairs. A first differential pair is connected in series to a second differential pair. The second differential pair is connected in a crosswise manner at least indirectly to a differential output signal of the first differential pair. The first differential pair and the second differential pair form a first differential current path and a second differential current path. A first emulation device is connected in parallel to the first current path. A second emulation device is connected in parallel to the second current path.

Abstract: A system includes a first variable gain amplifier configured to receive an input signal and a first down-mixer coupled to the first variable gain amplifier. Also, the system includes a first current conveyor coupled to the first down mixer, where the first current conveyor includes a first cascode and a second cascode coupled to the first cascode. Additionally, the system includes a first channel filter coupled to the first current conveyor and a second variable gain amplifier coupled to the first channel filter.

Abstract: A bias circuit includes a first p-n junction element supplied with a current by a first current source connected to a low-voltage side of the first p-n junction element and a base terminal of a second transistor, a second p-n junction element supplied with a current by a second current source, the second current source connected to a low-voltage side of the second p-n junction element and a base terminal of a first transistor, the first and second transistors connected at their emitter terminals to a third current source and receiving base voltages generated by the first and second p-n junction elements, respectively. The second transistor and the first transistor constitute a differential pair in which, at a collector terminal of the second transistor, a current having a temperature coefficient that is substantially twice the temperature coefficient of the current of the second current source is obtained.