Abstract: An offset voltage temperature coefficient reduction system for a differential operational amplifier is disclosed. In one embodiment, the offset voltage temperature coefficient reduction system comprises a first current source generating a first current with a positive temperature coefficient and a second current source generating a second current with a negative temperature coefficient, where the first current source and the second current source are coupled to their respective output nodes of the differential op amp such that an error due to an input offset voltage of the differential operational amplifier is approximately constant over a range of temperature, and where a difference between the first current and the second current is approximately zero at a reference temperature. In similar manner, the offset voltage temperature coefficient can be also adjusted to desired value other than zero.

Abstract: The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, there is no need extra frequency compensating component for compensating the transistor of the output stage circuit, and to save circuit layout area and cost can be achieved by the present invention.

Abstract: Embodiments relate to a current cell circuit in a digital-analog converter. According to embodiments, a current cell circuit in a digital-analog converter may include a current source connected to a power voltage terminal to generate current having a predetermined magnitude, a first current switch transferring current provided from the current source to a first output terminal, a first current generator detecting output voltage from the first output terminal and generating the amount of reduced current from the detected voltage, and a first current supplier supplying the amount of current generated from the first current generator to the first current switch. According to embodiments, current variations at a constant output voltage may be minimized. This may make it possible to obtain more stable frequency characteristics.

Abstract: A method for actuating an amplifier to generally eliminate a pop is provided. Accordingly, a plurality of current sources is actuated in an input stage, and a plurality of bias voltages are applied to the input stage. After a predetermined period after the step of applying a plurality of bias voltages to the input stage and the step of actuating a plurality of current sources in an input stage, a control circuit is actuated, and a transistor within a control amplifier stage is turned on at a predetermined rate.

Abstract: A timing circuit that can function as an accurate persistent node in an RFID tag includes a power capture circuit for capturing power from a power source, and a counter circuit that provides a count representing a progression of time. The count can then be compared to a reference value representing a time constant of the circuit.

Abstract: An OP-amp circuit includes a first circuit unit configured to generate an operating voltage in response to an enable signal, a second circuit unit configured to amplify a difference between respective voltages received through an inverting terminal and a non-inverting terminal in response to the operating voltage and to output a result of the amplification as a first drive voltage, a third circuit unit configured to output a second drive voltage according to a voltage level of the first drive voltage inputted thereto, and a fourth circuit unit configured to divide an input voltage inputted thereto into a divided voltage according to two resistances having respective resistive values varying according to the first and second drive voltages and to output the divided voltage through an output terminal.

Abstract: An operational amplifier has an input stage that branches a first current according to first and second input signals. An output stage generates an output signal from a second current and one of the branch currents in the input stage. A first transistor supplies the first current to the input stage. A second transistor supplies the second current to the output stage. A first gate line supplies a first bias potential to the gate terminal of the first transistor. A second gate line supplies a second bias potential to the gate terminal of the second transistor. The first gate line and the second gate line are electrically isolated from each other, preventing unwanted feedback of the output signal to the input stage by leakage through the gate lines.

Abstract: An operational amplifier capable of enhancing slew rate is disclosed. The operational amplifier includes a first current generator for generating a first bias current, a second current generator for generating a second bias current, an amplification stage, coupled to the first current generator, for generating a amplification signal according to an input signal, an output stage, coupled to the second current generator and the amplification stage, for generating an output signal according to the amplification signal, and a bias current allocation unit, coupled to the first current generator, the second current generator, the amplification stage and the output stage, for reallocating current intensities of the first bias current and the second bias current according to a control signal.

Abstract: Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.

Abstract: The invention provides an operational amplifier. In one embodiment, the operational amplifier includes an input stage circuit, a feedback circuit, a fixed stage circuit, and an output stage circuit. The input stage circuit receives a positive input voltage and a negative input voltage, and amplifies the positive input voltage and the negative input voltage to output a first positive output voltage and a first negative output voltage. The feedback circuit generates a reference positive output voltage equal to the first positive output voltage according to the positive input voltage and the negative input voltage. The fixed stage circuit equally amplifies the first negative output voltage and the reference positive output voltage to generate a second positive output voltage and a second negative output voltage. The output stage circuit generates an output voltage according to a difference voltage between the second positive output voltage and a second negative voltage.

Abstract: A comparator circuit. A comparator circuit may include a differential amplifying unit to amplify a difference between a voltage at a first node and a voltage at a second node and/or output a resultant voltage, and/or a current source to supply a first bias current to a first node and/or supply a second bias current to a second node. A comparator may include a first bias switch to bias a current flowing from a first node to a ground voltage source, a second bias switch to bias a part of a current flowing from a second node to a ground voltage source, a third bias switch to bias a remaining part of a current flowing from a second node to a ground voltage source, and/or a bias converting unit to supply a third bias current to a second node.

Abstract: Systems and methods for providing a self-mixing adaptive bias circuit that may include a mixer, low-pass filter or a phase shifter, and a bias feeding block. The self-mixing adaptive bias circuit may generate an adaptive bias signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit increases the bias voltage or bias current such that the amplifier will save current consumption at low power operation levels and obtain better linearity at high power operation levels compared to conventional biasing techniques. Moreover, the adaptive bias output signal can be used to cancel the third-order intermodulation terms (IM3) to further enhance the linearity as a secondary effect.

Abstract: An operational amplifier includes a first stage and a second stage, the first stage for receiving two input signals and the second stage being coupled to the first stage, wherein the second stage includes a first part with a first output of the operational amplifier, and a second part with a second output of the operational amplifier. A method includes providing a first current to the first part of the second stage, and providing a second current to the second part of the second stage. The method further includes adjusting the first current based on a current consumption of the first part of the second stage, and adjusting the second current based on a current consumption of the second part of the second stage, wherein the sum of the first current and the second current is substantially constant.

Abstract: Systems and methods for providing an adaptive bias circuit that may include a differential amplifier, low-pass filter, and common source amplifier or common emitter amplifier. The adaptive bias circuit may generate an adaptive bias output signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit may increase the bias voltage or bias current of the adaptive bias output signal. A power amplifier (e.g., a differential amplifier) may be biased according to the adaptive bias output signal in order to reduce current consumption at low power operation levels.

Abstract: Provided is a CMOS operational amplifier circuit that can operate with low noise, with low current consumption, and with stability. A cascode bias voltage of a folded cascode circuit in the CMOS operational amplifier circuit is modulated by a current at an input differential stage, thereby enabling operation with low noise, with low current consumption, and with stability.

Abstract: A differential amplifier comprises a left amplifier having transistors, a right amplifier having transistors, a negative feedback network having a resistor, and a negative feedback network having a transformer with a center tap. Phase compensation networks comprising a capacitor and a resistor, a capacitor and a resistor, and a capacitor and a resistor are further added to the amplifier. Both ends of a secondary winding of the transformer are connected to the output terminals of the right and left amplifiers, and the center tap of the secondary winding is grounded, so that a differential amplified output signal can be fed back to a single-phase input using one transformer, thereby reducing a cost and an area.

Abstract: In one embodiment, an amplification circuit charges a filter capacitor (14) and an input capacitor (12) with a substantially constant current and subsequently forms a delay prior to operating the amplification circuit to amplify input signals.

Abstract: Methods and corresponding systems for amplifying an input signal include inputting first and second differential input signals into first and second circuit legs, respectively, wherein the first circuit leg includes a first transistor coupled in series with a first variable current source, and wherein the second circuit leg includes a second transistor coupled in series with a second variable current source. The first and second variable current sources are dynamically set to provide first and second bias currents in response to the first and second differential input signals, wherein the first bias current is set inversely proportional to the second bias current. The first and second bias currents are sunk in the first and second circuit legs, respectively. First and second differential output signals are output from the first and second circuit legs, respectively.

Abstract: A differential amplifier is constituted of first emitter-follower transistors, second emitter-follower transistors, and amplification transistors whose bases are alternately connected to the emitters of the second emitter-follower transistors and whose collectors are connected to the emitters of the first emitter-follower transistors, as well as emitter resistors and constant current sources, whereby it is possible to reduce distortions of output signals in response to large-amplitude input signals, thus ensuring high-speed operation. It is possible to further incorporate base-grounded transistors and diodes, by which substantially the same collector-emitter voltage is applied to the emitter-follower transistors and amplification transistors, thus achieving the same power consumption and the same temperature variations with respect to these transistors.

Abstract: The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, extra frequency compensating components for compensating the transistor of the output stage circuit is no longer necessary, and saving circuit layout area and cost can be achieved by the present invention.

Abstract: A low frequency analog circuit and a method for designing the same are provided. In a low frequency analog circuit according to the present invention, a part of MOS transistors employed in the circuit are operated at a weak inversion region.

Abstract: In one aspect, a resistor process invariant transconductor is provided. The transconductor comprises a voltage input configured to receive at least one voltage signal, a current output configured to provide at least one current signal, wherein a ratio between the at least one voltage signal and the least one current signal forms a total transconductance for the transconductor, and a circuit including at least one integrated resistor connected between the voltage input and the current output, the circuit adapted to maintain the total transconductance substantially constant across variation of the at least one integrated resistor.

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

Abstract: A variable bias current is provided for the differential pair of an operational transconductance amplifier to improve the gain performance, especially to overcome the slew rate limit of the operational transconductance amplifier. The bias current is adjusted according to the differential input to the differential pair, the difference between the currents of the differential pair, or any one of the currents of the differential pair.

Abstract: An amplifier gain control circuit for the wireless transceiver comprises at least one amplifier, an analog to digital converter (ADC), a digital to analog converter (DAC) and a bias circuit, wherein the ADC is used for receiving an analog gain control voltage to generate a digital control signal that can be used for controlling the gain of the amplifier, the DAC is used for receiving the digital signal to generate an analog signal, and the bias circuit is used for receiving the analog signal and the analog gain control voltage to further fine-tune the gain of the amplifier by the analog process for correcting the least bit error during the digital process, therefore, the amplifier during the gain adjustment will be prevented to operate in the nonlinear area.

Abstract: An apparatus includes an input-bias node and an internal load. The input-bias node is configured to simultaneously receive an input signal and a bias signal through an input-bias port. The internal load is connected between the input-bias node and multiple output ports, at least one of the output ports outputting an output signal based on the input signal received at the input-bias node.

Abstract: A differential two-stage Miller compensated amplifier system with capacitive level shifting includes a first stage differential transconductance amplifier including first and second output nodes and an output common mode voltage, a second stage differential transconductance amplifier including non-inverting and inverting inputs and outputs and an input common mode voltage, and a level shifting capacitor circuit coupled between the first and second output nodes and the non-inverting and inverting inputs for level shifting between the output common mode voltage of the first stage and the input common mode voltage of the second stage.

Abstract: A variable gain amplifying device that amplifies an input signal and outputs the amplified signal, has a controlling circuit that controls the gain by controlling turning on and off of first MOS transistors and third MOS transistors so that the sum of the number of first MOS transistors turned on and the number of third MOS transistors turned on is “n” by outputting a control signal to the gates of the first MOS transistors and the third MOS transistors.

Abstract: A low-voltage differential communication system includes a low- and programmable-swing voltage-mode transmitter that delivers a low-voltage differential signal to a receiver via differential channel. The receiver employs two input transistors, each in a common-gate configuration, to recover the low-voltage differential signal. A current source in the receiver biases the input transistors such that their source voltages are nominally biased at the common-mode voltage of the differential signal, and their gate-source voltages remain essentially constant with common-mode-voltage fluctuations.

Abstract: Aspects of a method and system for a highly efficient power amplifier (PA) utilizing dynamic biasing and predistortion are presented. Aspects of the system may include a processor that enables computation of a value of a variable bias component of a bias current based on a bias slope value and an amplitude of an envelope input signal. The processor may enable computation of a value of the bias current based on the selected constant bias current component value and the variable bias current component value. A PA may enable generation of an output signal in response to a generated baseband signal by utilizing the bias current to amplify an amplifier input signal. The bias current may be generated based on the envelope input signal. A feedback signal may be generated based on the output signal, which may be used to predistort a subsequent baseband signal.

Abstract: Protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, in transition, exceed desirable levels is provided by limiting the voltage across any two device terminals under power down conditions.

Abstract: A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.

Abstract: In an offset fixing operational amplifier circuit, an operational amplifier circuit includes an input stage containing a first constant current source, a second constant current source, a first differential pair and a second differential pair. A bias circuit supplies a bias voltage to the operational amplifier circuit. An offset fixing circuit controls the input stage in accordance with an input voltage of the operational amplifier circuit.

Abstract: A device for providing low noise transconductance amplification is presented. The device includes a PMOS transconductance section configured to receive a differential RF input signal, a PMOS cascode section coupled to the PMOS transconductance section, an NMOS transconductance section configured to receive the RF differential input signal, and an NMOS cascode section coupled to the NMOS transconductance section, where the PMOS and NMOS cascode sections provide a differential quadrature output signal and a differential in-phase output signal. A method for amplifying an RF signal is also presented. The method includes receiving a differential RF input signal, converting the differential RF input signal into current signals, buffering the current signals to provide a differential quadrature output signal and a differential in-phase output signal.

Abstract: An IQ mixer and a method thereof. The IQ mixer comprises a pair of Gilbert cells and a degeneration inductor. Each pair of Gilbert cells comprises a pair of first current generators and a pair of switching networks. The pair of first current generators converts an RF signal pair to currents respectively. The pair of switching networks, coupled to the first current generator, modulates the converted RF signal pair with an oscillation signal pair to generate a mixed signal pair. The degeneration inductor is coupled to all pairs of the first current generators, such that it is shared by the pair of Gilbert cells.

Abstract: Provided are a differential amplifier circuit and a method of generating a bias voltage in a differential amplifier circuit. The differential amplifier circuit is turned on or turned off in response to an input voltage and includes a differential amplifier and a bias circuit. The bias circuit provides a first bias voltage to a gate of a pull-down transistor included in the differential amplifier when the differential amplifier is turned on and provides second bias voltage which is lower than the first bias voltage to the gate of the pull-down transistor when the differential amplifier is turned off.

Abstract: A rail-to-rail operational amplifier capable of reducing current consumption includes an amplification stage circuit including a first compensation output terminal and a second compensation output terminal, for generating an amplified signal according to an input signal, an output stage circuit coupled to the amplification stage circuit, for outputting the amplified signal, and a compensation circuit coupled to the amplification stage circuit and the output stage circuit. The compensation circuit includes a first voltage generator for generating a first voltage, a second voltage generator for generating a second voltage, a first compensation capacitor, a second compensation capacitor, and four switches named from a first switch to a fourth switch, wherein the first voltage is approximately a steady state voltage of the first compensation output terminal and the second voltage is approximately a steady state voltage of the second compensation output terminal.

Abstract: A driving circuit of enhancing response speed is disclosed. The driving circuit includes an operational amplifier and a slew rate enhancement unit. The operational amplifier is utilized for generating a driving voltage according to an input voltage. The slew rate enhancement unit is coupled to the operational amplifier, and is utilized for generating a compensation current to the operational amplifier to enlarge a bias current of the operational amplifier according to voltage difference between the input voltage and the driving voltage when variation of the input voltage occurs.

Abstract: An input bias cancellation stage for an audio operational amplifier is provided. The input bias cancellation stage includes an input differential pair, a current mirror, and a bias duplicator transistor that substantially duplicates the input bias current. The bias duplicator transistor receives substantially the same emitter current as the transistors in the input differential pair, and has substantially the same Vce as the transistors in the input differential pair. The current mirror mirrors the duplicated bias current and subtracts it from the bases of the transistors in the input differential pair so that the input bias current is substantially cancelled.

Abstract: A differential amplifier circuit is provided with a first input stage including a transistor pair of a first conductivity type, of which transistor pair receives differential input signals; a first output stage connected to the first input stage; a second input stage including a transistor pair of a second conductivity type different from the first conductivity type, of which transistor pair receives the differential input signals; a second output stage connected to the second input stage; and an output terminal.

Abstract: A differential stage which uses a bias generator circuit to set the operating currents of the input stage FETs to make the incremental Gm primarily a function of a single resistor embedded in the biasing circuit, such that the input stage has a Gm which only gradually departs from nominal under overdrive, and continues to supply output currents which increase with an increasing differential input signal.

Abstract: A semiconductor device includes a phase compensation circuit 6 using a MOS capacitor with a structure in which an insulating film is disposed between a gate electrode formed on a semiconductor substrate and a diffusion layer. The phase compensation circuit includes first and second MOS capacitors 14, 15. A gate electrode terminal of the first MOS capacitor is connected equivalently to a diffusion layer terminal of the second MOS capacitor that is a terminal opposite to the gate electrode terminal. A potential difference generating element 16 that generates a potential difference by allowing a current to flow therethrough is connected between a diffusion layer terminal of the first MOS capacitor and a gate electrode terminal of the second MOS capacitor. When the MOS capacitors having the voltage dependence are used, e.g.

Abstract: A differential amplifier circuit at the input stage is configured with a twin differential type having a first differential amplifier circuit (11) and a second differential amplifier circuit (12), respective outputs of which are received by a first and a second source-grounded amplifier (M5, M10). The second source-grounded amplifier (M10) is connected to a current mirror circuit (M11, M12), which is driven by the drain current of the second source-grounded amplifier (M10). With this configuration, the dynamic range for the upper half portion of an alternating signal output from an output terminal (OUT) is determined by the current supply capability of the first source-grounded amplifier (M5) and the dynamic range for the lower half portion is determined by the current supply capability of the second source-grounded amplifier (M10). This eliminates the need of a constant current circuit of a large current for generating a signal having lower half portion in which the waveform distortion is improved.

Abstract: A transconductor to convert an input voltage to an output current, includes: a primary transconductance stage to provide the output current from the input voltage and a driving current; an adaptive transconductance stage coupled in series with the primary transconductance stage to generate the driving current from the input voltage; and a bias circuit coupled to provide a primary bias voltage to the primary transconductance stage and an adaptive bias voltage to the adaptive transconductance stage.

Abstract: An output stage includes two transistors (switching transistor and biasing transistor) coupled in series in a pullup current path between a VDDA node and an output node, and also includes two transistors (switching transistor and biasing transistor) coupled in series in a pulldown current path between the output node and a ground node. Providing the biasing transistors reduces the maximum voltage dropped across the transistors, thereby allowing the transistors to have lower breakdown voltages than VDDA. An adaptive biasing circuit adjusts the gate voltage on a biasing transistor based on the output node voltage. If the output voltage is in a midrange, then the gate voltage is set farther away from a rail voltage in order to reduce voltage stress. If the output voltage is in a range closer to the rail voltage, then the gate voltage is set closer to the rail voltage, thereby facilitating rail-to-rail output voltage swings.

Abstract: Disclosed is a differential amplifier which includes first and second input terminals, an output terminal, first and second differential pairs, and first and second current sources for supplying currents to the first and second differential pairs. The first differential pair has first and second inputs of an input pair connected to the first input terminal and the output terminal, respectively. The second differential pair has first and second inputs of an input pair connected to the second input terminal the output terminal, respectively.

Abstract: A semiconductor device including: a gain control circuit; a first circuit which is controlled a gain to be constant by the gain control circuit; and a bias circuit connected to the first circuit, wherein the first circuit including a first transistor; and a load resistance, an amplification factor or an attenuation factor of the first circuit is proportionate to a product of a transconductance of the first transistor and a resistance value of the load resistance, and a voltage applied to the load resistance is set as an output of the semiconductor device, the bias circuit generates and outputs a differential current of a current that is proportionate to a drain current flowing into the first transistor and a current that is inversely proportionate to the load resistance value, and an output of the bias circuit is connected to an output node of the first circuit.

Abstract: Methods and corresponding systems for amplifying an input signal include inputting first and second differential input signals into first and second circuit legs, respectively, wherein the first circuit leg includes a first transistor coupled in series with a first variable current source, and wherein the second circuit leg includes a second transistor coupled in series with a second variable current source. The first and second variable current sources are dynamically set to provide first and second bias currents in response to the first and second differential input signals, wherein the first bias current is set inversely proportional to the second bias current. The first and second bias currents are sunk in the first and second circuit legs, respectively. First and second differential output signals are output from the first and second circuit legs, respectively.

Abstract: According to some embodiments, an amplifier may include a transconductance stage, a tail current source stage, and an adaptive biasing stage. The transconductance stage may be configured to receive an input voltage. The tail current source stage may be configured to provide current to the transconductance stage. The adaptive biasing stage may capacitively couple the transconductance stage to the tail current source stage.

Abstract: According to one exemplary embodiment, a power supply rejection bias circuit includes a first amplifier coupled to a second amplifier, where the first amplifier receives a reference voltage, and a feedback voltage of the bias circuit. The bias circuit further includes an output transistor driven by the output of the second amplifier, where the output transistor provides the output of the bias circuit and the feedback voltage. The bias circuit further includes a feedback resistor coupled between an input and an output of the second amplifier. According to this embodiment, the output of the second amplifier forms a non-dominant pole of the bias circuit and the output of the bias circuit forms a dominant pole of the bias circuit, thereby increasing power supply rejection of the bias circuit.