Abstract: The present invention relates to a system for boosting the power supply of an RF power amplifier in high peak to average power ratio applications, wherein said power amplifier is coupled to receive and amplify a digital data stream of a baseband signal, (e.g., which after modulation with a carrier wave are supplied as the RF input signal to said power amplifier to generate an RF output signal).

Abstract: A piece of audio equipment is provided that includes a first signal path including a first dynamic range expander and a lowpass filter. The piece of audio equipment also includes a second signal path parallel to the first signal path, wherein the second signal path includes a second dynamic range expander and a highpass filter. The piece of audio equipment further includes a summing amplifier configured to receive a first signal from the first signal path, a second signal from the second signal path, and a clear signal from an audio source and output a summed signal.

Abstract: A power amplification module includes a first input terminal arranged to receive a first transmission signal in a first frequency band, a second input terminal arranged to receive a second transmission signal in a second frequency band higher than the first frequency band, a first amplification circuit that amplifies the first transmission signal, a second amplification circuit that amplifies the second transmission signal, a first filter circuit located between the first input terminal and the first amplification circuit, and a second filter circuit located between the second input terminal and the second amplification circuit. The first filter circuit is a low-pass filter that allows the first frequency band to pass therethrough and that attenuates a harmonic of the first transmission signal and the second transmission signal. The second filter circuit is a high-pass filter that allows the second frequency band to pass therethrough and that attenuates the first transmission signal.

Abstract: An amplifier circuit includes: a first filter that receives input of amplitude information of an input signal, and performs filtering so that a gain of a frequency component higher than a first cutoff frequency becomes greater than a gain of a frequency component lower than the first cutoff frequency; a power supply circuit that has a low-pass filter characteristic, and receives input of amplitude information outputted from the first filter and generates a power supply voltage corresponding to the amplitude information outputted from the first filter; an amplifier that receives supply of the power supply voltage, and amplifies a signal based on the input signal; and a phase difference detector that detects a phase difference between the amplitude information of the input signal and the power supply voltage, wherein the first filter changes the first cutoff frequency in a direction in which the phase difference decreases.

Abstract: Programmable delay circuitry, which includes an input buffer circuit and variable delay circuitry, is disclosed. The variable delay circuitry includes an input stage, a correction start voltage circuit, and a variable delay capacitor. The input buffer circuit is coupled to the input stage, the correction start voltage circuit is coupled to the input stage, and the variable delay capacitor is coupled to the input stage. The programmable delay circuitry is configured to provide a fixed time delay and a variable time delay.

Abstract: A signal shaping circuit that shapes a drive signal and includes a main-signal amplifying circuit that amplifies the drive signal; a preemphasis generating circuit that symmetrically emphasizes a rising portion and a falling portion of the drive signal; a current source that is provided in the main-signal amplifying circuit; and a condenser that couples the main-signal amplifying circuit and the preemphasis generating circuit.

Abstract: An amplifier circuit of envelope tracking scheme has a timing adjusting unit having a finite number of adjustment values for adjusting time by which the output is delayed from the input, and capable of adjusting a time difference between an input signal and a power supply voltage which reach an amplifier, by making a selection from the adjustment values; a test signal output unit capable of repeatedly sending out a test signal serving as the input signal at predetermined cycles; and an adjustment value determining unit sequentially measuring output power for m (?k) periods from the amplifier while changing an adjustment value of the timing adjusting unit to a different value every k periods of the test signal, searching for an adjustment value at which a total sum of the output power form periods is maximum, and setting the adjustment value on the timing adjusting unit.

Abstract: A method for generating an amplified radio frequency (RF) signal is provided. In-phase (I) and quadrature (Q) signals are received and interleaved so as to generate a time-interleaved signal. Delayed time-interleaved signals are then generated from the time interleaved signal, and each of the delayed time-interleaved signals is amplified so as to generate a plurality of amplified signals. The amplified signals are then combined with a transformer, where the delayed time-interleaved signals are arranged to generate a filter response with the transformer.

Abstract: Provided is a power consumption control circuit, an amplifier circuit and a power consumption control method which control the power consumption associated with an amplification action in real time. A power consumption control circuit of the present invention comprises: a detection means which detects the presence or absence of an input of a digital input signal, spending a first period of time; a signal delay means which delays the digital input signal by a second period of time equivalent to the first period of time, and outputs the delayed signal; a digital-to-analog conversion means which converts the delayed signal into an analog signal, and outputs the analog signal; an amplification means which generates an amplification action when a bias is applied to it; and a bias control means which applies a bias to an amplification device, on the basis of a detection result obtained by the detection means.

Abstract: A transmitter has a power amplifier (40) to amplify an input signal having amplitude modulation, a supply voltage controller (10) to control a supply voltage of the power amplifier (40) according to the envelope, a sensor (R1) for sensing a modulation of a current drawn by the power amplifier (40), a delay detector (20) for detecting a delay of the controlled supply voltage relative to the sensed current, and a delay adjuster (30) for compensating the relative delay according to the detected delay. By sensing a current drawn, the delay detected can include any delay contributed by the power amplifier (40) up to that point, and yet avoid the more complex circuitry needed to derive the delay from an output of the power amplifier. Thus the distortion and out of band emissions caused by differential delays can be reduced more effectively.

Abstract: System and method for creating a time alignment analog notch. An embodiment includes a digital power amplifier coupled to an enable signal line and to a digital control bits bus, and a matching network coupled to the digital power amplifier. The matching network to provide impedance matching and the digital power amplifier to produce a current based on a value on the digital control bits bus. The digital power amplifier comprises a selection circuit and a plurality of transistors. The transistors, controlled by outputs of the selection circuit, provide a current based on the value on the digital control bits bus. The adjustment of a delay between a signal on the enable signal line and the values on the digital control bits bus creates an analog notch at about Fs/2, where Fs is a sampling frequency of a sigma-delta modulator used to modulate data provided to the digital power amplifier.

Abstract: A first gain stage and a second gain stage having different gains are linked in cascade to construct a wide range and high resolution programmable gain amplifier. The second gain stage can be used only for low gain and low power consumption. Furthermore, two pairs of chopper circuits are used to shift flicker noise when the programmable gain amplifier is operated.

Abstract: A receiver for processing a signal comprises a first amplifier circuit and a second amplifier circuit. The first amplifier circuit is operated in association with a first gain profile. The second amplifier circuit is operated in association with a second gain profile. The receiver further comprises a gain control circuit that determines a quality indicator associated with a modulated signal. The gain control circuit adjusts the first gain profile and the second gain profile based at least in part upon the determined quality indicator.

Abstract: Systems and methods for performance improvements in digital switching amplifiers using a low delay corrector. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low delay corrector configured to receive signals output by the plant. The output of the low delay corrector is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

Abstract: In a digital broadcast receiving apparatus for amplifying a received modulated digital signal wave with automatically adjusted gain and demodulating the modulated signal wave to a digital signal, a tuner frequency-converts the modulated digital signal wave to generate a first modulated signal. A first automatic gain control amplification unit controls gain of the tuner to make a level of the first modulated signal at a first predetermined level. An A/D converter converts the first modulated signal into a second modulated signal. A demodulator demodulates the second modulated signal to generate a first demodulated digital signal. A second automatic gain control amplifier generates a second demodulated digital signal where frequency fluctuations included in the digital modulated wave are eliminated.

Abstract: An amplifier system is provided for amplifying an input signal to provide an amplified output signal, amplifying an amplified input signal to provide a further amplified output signal, and phase delay compensating variations of the amplifications of the amplified output signal and the further amplified output signal for providing the further amplified output signal with substantially linear amplification under a variable load.

Abstract: A converter includes an input circuit to receive a single-ended input signal to generate a number of control signals. The control signals have a delay different from one another relative to the single-ended input signal. The converter also includes a first output circuit and a second output circuit. The first output circuit responds to the control signals to generate a first output signal. The second output circuit responds to the control signals to generate a second output signal. The first and second output signals are non-overlapping and form a complimentary signal pair.

Abstract: An amplitude frequency characteristic adjustment circuit 106 is provided downstream of and connected to a distortion generation circuit 105. An amplitude difference between low-frequency-side and high-frequency-side distortion voltages is adjusted by the amplitude frequency characteristic adjustment circuit 106, and then their amplitudes and phases are adjusted by a vector adjustment circuit 107. This configuration makes it possible to suppress simultaneously both of low-frequency-side and high-frequency-side distortion voltages of a distortion generated by a wide-band class-AB power amplifier even if they are different in amplitude and phase.

Abstract: An amplitude frequency characteristic adjustment circuit 106 is provided downstream of and connected to a distortion generation circuit 105. An amplitude difference between low-frequency-side and high-frequency-side distortion voltages is adjusted by the amplitude frequency characteristic adjustment circuit 106, and then their amplitudes and phases are adjusted by a vector adjustment circuit 107. This configuration makes it possible to suppress simultaneously both of low-frequency-side and high-frequency-side distortion voltages of a distortion generated by a wide-band class-AB power amplifier even if they are different in amplitude and phase.

Abstract: The insertion phase or delay of an amplifier can be controlled by comparing signals from the amplifier path with signals from a corresponding reference path without requiring the overall signal delay through the reference path to nominally match the overall signal delay through the amplifier path. Amplifier and reference path signals can be combined to form a combined signal whose power is detected using a narrow-band, frequency-selective power detector. For given phase and delay offsets between the amplifier and reference paths, cancellation (i.e., perfectly destructive interference) will occur at a series of different frequencies. By operating the power detector at one of these cancellation frequencies, a variable phase or delay adjuster in the amplifier path can be controlled to minimize the detected power level in order to achieve a desired level of insertion phase for the amplifier, without having to implement an expensive delay element in the reference path.

Abstract: A differential amplifier (10, 60) is formed to have a propagation delay that varied responsively to a control signal received on a differential control signal input. The propagation delay is varied by changing the bias current of a pair of differential input transistor (11, 13).

Abstract: An input signal is modified to compensate for amplifier memory effects by combining at least two versions of the input signal, each version of the input signal being offset in time with respect to one another. More specifically, an RF input signal is split into at least two split signals, a different delay is applied to each split signal, and the delayed, split signals are combined to obtain a modified input signal.

Abstract: A differential amplifier (10, 60) is formed to have a propagation delay that varied responsively to a control signal received on a differential control signal input. The propagation delay is varied by changing the bias current of a pair of differential input transistor (11, 13).

Abstract: The present invention is directed to a signal processing and amplifying system that uses advance knowledge of a digital signal, before it is converted to analog form and applied to the input stage of the amplifier stage, to “intelligently” amplify the signal with the maximum power efficiency and minimal distortion. This advance knowledge of the digital signal allows a switch control logic (SCL) unit to open and close solid state switches and seamlessly turn off and on the low and high power stages correctly to minimize the amplifier distortion while conserving power. In one embodiment, the system comprises a shift register, which receives the supplied digital signal to be amplified and delays the digital signal by a known amount, a digital to analog converter, an amplifying circuit, which is made up of at least two amplifiers, and an SCL unit. The SCL unit comprises control logic, and multiple solid state switches.

Abstract: A method for reducing delay variability in a differential receiver includes receiving a plurality of differential input signals, determining a first transition delay time of an output in response to the plurality of differential input signals, determining a second transition delay time of the output in response to the plurality of differential input signals, and modifying capacitance coupled to the output in response to the first transition delay time and to the second transition delay time.

Abstract: A high-frequency power amplifying apparatus includes a plurality of series-connected amplifiers, a power controller for selectively supplying an output terminal with an output from a desired one amplifier in accordance with a demanded output power and for causing one or more amplifiers downstream of the desired one amplifier to be in a cutoff state, and an output delay line connected between the output terminal and the final-stage amplifier and having a line length thereof providing the final-stage amplifier with a high impedance as viewed from the output terminal when the final-stage amplifier is in a cutoff state.

Abstract: An amplitude frequency characteristic adjustment circuit 106 is provided downstream of and connected to a distortion generation circuit 105. An amplitude difference between low-frequency-side and high-frequency-side distortion voltages is adjusted by the amplitude frequency characteristic adjustment circuit 106, and then their amplitudes and phases are adjusted by a vector adjustment circuit 107. This configuration makes it possible to suppress simultaneously both of low-frequency-side and high-frequency-side distortion voltages of a distortion generated by a wide-band class-AB power amplifier even if they are different in amplitude and phase.

Abstract: An electronic device comprises an audio amplifier, a main microprocessor and a user interface microprocessor. The UI microprocessor has a control pin for muting the audio amplifier. A muting circuit is provided for muting the audio amplifier when a signal representative of a switch to an OFF mode of the device is generated by a mode pin of the main microprocessor. A delay part is also provided in order to switch the audio amplifier to standby during a given period of time when a signal representative of a switch to an ON mode of the device is generated by the mode pin. Methods for controlling the electronic device are also proposed.

Abstract: An operational amplifier includes a differential amplification circuit, a voltage amplification circuit, a capacitor, and a bias setting circuit. The differential amplification circuit includes load transistors arranged in a cascode connection. The voltage amplification circuit forms a stage following the differential amplification circuit. The capacitor couples the differential amplification circuit and the voltage amplification circuit with each other. The bias setting circuit charges the capacitor to a prescribed bias voltage before amplification is started. Preferably, the charged capacitor sets the differential amplification circuit in a prescribed biased state.

Abstract: Disclosed an up converter of base station transmitter of an wireless communication and method of controlling outputs of the up converter to control output signals of the up converter in accordance with the conditions of the strength of input signal and/or output signal of by detecting the input signal level and/or output signal level of the up converter. The up converter of the present invention comprises an input level detection section for detecting an input signal of the up converter; a variable attenuator for attenuating converted frequency in the up converter; an output level detection section for detecting an output signal of the up converter; a processor for outputting a control signal to adjust the variable attenuator in accordance with the detected results of the input level detection section and the output level detection section.

Abstract: The stages of a multistage amplifier are quickly switched between operational modes, e.g., from a standby mode to an active mode. The delivery of a control signal to each individual stage is delayed so that the modes of the stages are switched, in a desired sequence. The final amplifier stage is isolated from the operational mode switching of the preceding stages by a buffer. For switching the multistage amplifier from the standby mode to the active mode, the stages and the buffer are turned on, in a desired sequence, beginning with the first stage. For switching the multistage amplifier from the active mode to the standby mode, the stages and the buffer are turned off, in a desired sequence, beginning with the buffer. A delay unit includes a plurality of delay units, one connected to each amplifier stage, except the final amplifier stage, and to the buffer.

Abstract: A method of linearizing an amplifier having an input and an output involves the steps of amplifying the amplifier input signal with a vector modulator having a gain adjustment signal input for receiving a gain adjustment signal and adjusting the gain of the vector modulator in response to a gain adjustment signal to produce an amplifier output signal at the amplifier output. This is followed by producing a gain error signal dependent upon the amplifier input signal and the amplifier output signal, the gain error signal having real and imaginary components lying within pre-defined regions in a complex plane. Finally, the gain adjustment signal is generated in response to a region in the complex plane in which an error signal vector defined by the real an imaginary components of the error signal vector lies.

Abstract: A variable time delay network (210) includes segments (270, 260) which are connected in parallel to form variable time delay network (210). Segment (270) includes a varactor diode (222) and an inductive element (223) connected in series at an anode electrode (290) of varactor (222). A cathode electrode (291) of varactor diode (222) connected to a node (220). Segment (260) includes a varactor (221) and a bypass capacitor (224) connected in series at a cathode electrode (292) of varactor (221). Cathode electrode (292) is connected at a node (225). An anode electrode (293) of varactor (221) connected to node (220). The impedance at node (220) presented to a signal that is to be time delayed remains constant at the center frequency of the signal via a bias voltage applied at node (225) while controlling and changing the time delay of the signal via a bias voltage applied at node (220).

Abstract: An automatic dynamic range control circuit is provided with a fixed-gain first circuit means and a variable-gain second circuit means having substantially the same propagation delay as the first circuit means. The automatic dynamic range control circuit holds the peak value of an input signal, selects the first circuit means when this peak value is smaller than a reference signal level, and selects the second circuit means when the peak value exceeds this reference signal level. When the held peak value is smaller than the reference signal level, the second circuit means is operated at the same gain relative to an input signal as the first circuit means by having its gain set by the reference signal. When the held peak value exceeds the reference signal, the gain of the second circuit means is limited by this held peak value and its output level is kept at or below a prescribed level.

Abstract: A comparator (5) compares a detected voltage obtained by detecting an output power of a nonlinear amplifier (2) with a reference voltage to generate a control voltage for the nonlinear amplifier (2). The control voltage is converted into such a control voltage as to cancel the nonlinearity of the nonlinear amplifier (2) by a nonlinearity compensating circuit (7) and is supplied to the nonlinear amplifier (2). The nonlinear compensating circuit (7) is comprised of a diode (71) and a resistor (72).

Abstract: A circuit having a double half-wave rectifier connected to the outputs of a differential amplifier in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier. Two comparators each having an input are connected to an output of the rectifier and a reference input in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs. The circuit also has processing means for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified is not symmetrical.

Abstract: The invention relates to a directional coupler arrangement and measurement of radio frequency electric power with a directional coupler arrangement, which arrangement comprises a directional coupler, in which a terminal impedance, a detector element and a control circuit are connected between the end of the second conductor element and the earth potential. The impedance value of the terminal impedance can be altered by means of an electric control signal and said control circuit produces said control signal on the basis of the signal provided by the detector element. When the detected power level is low, the control circuit increases the impedance value of the terminal impedance, whereby the peak voltage of the signal applied to one end of the directional coupler increases and the arrangement yields a measurement result that is larger than ordinary, which improves the accuracy and reliability of the arrangement at low power levels.

Abstract: An automatic gain control circuit is provided, which has minimum variations in the output signal level even with the presence of variations in component parts thereof and the temperature dependency of component parts thereof and can therefore dispense with the use of an additional amplifier circuit for adjusting the output level. An input signal-attenuating circuit attenuates the level of an input signal to a voltage amplifier circuit. An output level-detecting circuit detects the voltage level of an output signal from the voltage amplifier circuit to thereby carry out feedback control by controlling the attenuating characteristic of the input signal-attenuating circuit in response to the detected voltage of the output signal such that the voltage level of the output signal from the voltage amplifier circuit is maintained at a constant level.

Abstract: An amplifier comprises a variable gain analog amplifier for amplifying an input analog signal to generate an intermediate analog signal, the gain of the analog amplifier being switchable between two or more discrete gain values. An analog to digital converter converts the intermediate analog signal into a corresponding intermediate digital signal and a variable gain digital amplifier amplifies the intermediate digital signal. A gain control circuit, responsive to a required gain, selects one of the discrete gain values of the analog amplifier and a gain value of the digital amplifier so that the sum of the selected gain values is substantially equal to the required gain; and whether the required gain is increasing or decreasing is detected.

Abstract: An audio amplifier clipping avoidance apparatus (140) identifies signal segments of an audio signal that can have an amplitude peak greater than a particular amplifier clip avoidance threshold (530). A scaling factor is determined for each signal segment based on the particular threshold (540). Signal segments are scaled with corresponding scaling factors to produce a modified audio signal having no signal segments with an amplitude peak greater than the particular threshold (560).

Abstract: A power control circuit having a saturation preventing control loop including a variable gain amplifier, an RF power amplifier, a directional coupler, a detecting circuit, a comparator, a switch, and an adder. When the signal level of an output signal of the comparator is low, the switch is turned on. When the signal level of the output signal of the comparator is high, the switch is turned off. A system power control loop includes a system power control terminal, the adder, and the variable gain amplifier. Since the saturation preventing control loop is provided with the switch, the saturation preventing control loop operates only when the signal level of the amplified signal is larger than a reference value. The system power control loop can properly operate according to a system power control signal supplied from the system power control terminal.

Abstract: A data independent AGC control circuit for telecommunication applications is provided and includes an AGC amplifier, a fixed gain amplifier, a capacitor, and first, second, and third control circuits. The AGC amplifier has a data input, a control input, and a data output. The capacitor is coupled to the control input, and the charge on the capacitor effectively controls the gain of the AGC amplifier. The first control circuit is coupled to the data output of the fixed gain amplifier and to the capacitor and increases the stored charge on the capacitor when the data output exceeds a desired peak voltage level. The second control circuit is similarly coupled between the data output of the fixed gain amplifier and the capacitor, and decreases the stored charge on the capacitor when the data output exceeds a threshold voltage (typically 1/2 the desired peak voltage level).

Abstract: An output level automatic control apparatus suitable for use to keep a transmitted output level of a radio system constant has an objective to prevent an output level above a specified value from being transmitted if an input level abruptly becomes a normal level from a break state, and to stabilize the output level with a simple configuration. The output level automatic control apparatus includes a main amplifier output level feed-back control loop extending from an output side of a main amplifier to a variable attenuator, which main amplifier output level feed-back control loop includes an output level detecting means, a reference value setting means, and a control means controlling the variable attenuator on the basis of a result obtained by comparing a detected output of the main amplifier with a reference value.

Abstract: A method and apparatus for controlling an amplifier power output, in particular, a transmitter RF Amplifier includes a control circuit connected to the RF Amplifier. The control circuit derives a control signal from a shaper circuit and this control signal is applied, together with a feedback signal representative of the flow of dc current through one of the stages of the amplifier, to a comparator to generate an error signal. The error signal is applied to a common amplifier base bias line. Preferably, all of the stages of the error amplifier are in a saturated state so that the effect of the error signal on the bias line causes the amplification envelope of the transistors in the amplifier to follow the error signal, thus generating a pulsed output signal having an envelope shape corresponding to the control signal.

Abstract: An amplifier having an automatic threshold control circuit (ATC) and a limiting amplifier. The ATC detects and holds a top value (peak value) and bottom value of an input signal, and outputs the middle value between the top and bottom values as a reference voltage. The limiting amplifier amplifies the input signal in a linear operating region whose center is set at the reference voltage, thereby maintaining the output amplitude at a constant value. Even if the amplitude and the level of the input signals instantaneously changes by a large amount, the ATC can follow the change, so that the offset compensation and gain compensation of the amplifier can be achieved instantaneously. This makes it possible to continue producing the output of a constant amplitude with little phase deviations.

Abstract: A power controller for a class C radio frequency power amplifier that exhibits an output power threshold, including a detector circuit (299) that detects a output power level to provide a level signal when the radio frequency power amplifier has achieved the output power threshold, and a comparator apparatus (245) that combines a reference signal and the level signal to provide a control signal that is arranged to establish the output power level, and a generator function (247) that provides the comparator apparatus a substitute level signal until the amplifier has achieved the output power threshold.

Abstract: A control device for a power amplifier controls the power amplifier upon a rise in output power based on a power variation pattern stored in storage means to suppress a power overshoot which occurs upon a rise in output power.

Abstract: An amplifier for a radio transceiver overcomes the problem of gain being dependent on ambient temperature. Transmission power is matched to strength of a received signal by providing matched dual gate FET amplifier stages in both the transmitter and receiver portions of the transceiver. Changes in gain due to temperature are compensated for by detecting changes in the FET drain current by measuring the source voltage of the amplifier. The FET source voltage is compared to a reference voltage, and the output signal resulting from the comparison is provided as a control signal to one of the FET gates.

Abstract: An automatic level control circuit for radio frequency power amplifiers which is immune to temperature and power supply induced variations. The level control circuit (42) employs a detector/comparator comprising a matched transistor pair (55) operating as a detecting differential amplifier to compare a reference signal (63) to the output power signal (83). A second amplifier (60) receives the differential output signals from the detecting amplifier and provides a power level control signal (97) to the power amplifier, thereby causing the power amplifier to produce the desired output power level.

Abstract: An output level control circuit for radio-frequency transmitter which intermittently transmits radio-frequency carrier waves such as seen in the TDMA radio communication system and the digital cellular mobile telephone system. The variable gain amplifier unit of this transmitter amplifies the transmitting signal to a predetermined output power level in response to a control signal, the output power level is detected by a detecting diode which receives the application of a temperature-compensated bias voltage, and the sum of the detected output and the bias voltage becomes the detection output to the control loop.