Having Negative Feedback Patents (Class 330/293)
  • Patent number: 11025204
    Abstract: The present invention provides a circuit having a filter with an amplifier circuit for filtering and amplifying an input signal to generate an output signal, wherein a corner frequency of the filter is adjustable to control a settling time of the output signal.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: June 1, 2021
    Assignee: MEDIATEK INC.
    Inventors: Ying-Wei Chou, Sung-Han Wen, Chen-Chien Lin, Jou Lee
  • Patent number: 10972058
    Abstract: In accordance with aspects of the present invention, embodiments of a photodiode circuit. A photodiode circuit according to some embodiments includes a transimpedance amplifier; a resistor coupled across the transimpedance amplifier; and an amplifier stage coupled to receive an output from the transimpedance amplifier, wherein the photodiode circuit provides dynamic range across a current range of the photodiode circuit. In some embodiments, the transimpedance amplifier includes a receive signal strength indicator that provides a DC current signal to a tail of a first amplifier stage, the tail providing a current that is adaptively related to the DC current. In some embodiments, the resistor is a shielded resistor. In some embodiments, the adaptive current sink includes a plurality of switchable parallel current sinks.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: April 6, 2021
    Assignee: Integrated Device Technology, Inc.
    Inventors: Ulrich Duemler, Bortecene Terlemez
  • Patent number: 10892721
    Abstract: Apparatus and methods for oscillation suppression of cascode power amplifiers are provided herein. In certain implementations, a power amplifier system includes a cascode power amplifier including a plurality of transconductance devices that operate in combination with a plurality of cascode devices to amplify a radio frequency input signal. The power amplifier system further includes a bias circuit that biases the plurality of cascode devices with two or more bias voltages that are decoupled from one another at radio frequency to thereby inhibit the cascode power amplifier from oscillating.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: January 12, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventor: John William Mitchell Rogers
  • Patent number: 10229939
    Abstract: A semiconductor device with reduced power consumption and a display device including the semiconductor are provided. The semiconductor device generates a bias voltage that is to be supplied to a buffer amplifier. When the display device displays a still image, a data signal for updating the image need not be supplied from the buffer amplifier to a pixel array in the next frame; therefore, the circuit is configured so that the buffer amplifier is brought into a standby state (temporarily stopped). Specifically, input of a reference current from a BGR circuit to the semiconductor is stopped and a bias voltage is applied from the semiconductor device to the buffer amplifier to temporarily stop the operation of the buffer amplifier.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kei Takahashi
  • Patent number: 10187020
    Abstract: A variable current trans-impedance amplifier (TIA) for an ultrasound device is described. The TIA may be coupled to an ultrasonic transducer to amplify an output signal of the ultrasonic transducer representing an ultrasound signal received by the ultrasonic transducer. During acquisition of the ultrasound signal by the ultrasonic transducer, one or more current sources in the TIA may be varied.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: January 22, 2019
    Assignee: Butterfly Network, Inc.
    Inventors: Kailiang Chen, Keith G. Fife, Nevada J. Sanchez, Andrew J. Casper, Tyler S. Ralston
  • Patent number: 9780737
    Abstract: A digitally-controlled transimpedance amplifier (TIA) circuit is provided in which a plurality of feedback loops are digitally controlled, including, but not limited to, the DC offset cancellation loop, the variable gain control loop, and the TIA feedback impedance adjustment loop. The digitally-controlled TIA circuit includes digital loop-control circuitry that consumes less area on the TIA IC chip than the analog circuitry traditionally used to perform the feedback loop control in the analog domain. In addition, because digital logic continues to shrink as IC processes continue to evolve, the size of the IC chip packages will further decrease over time, leading to a smaller footprint in systems in which they are employed. The digital loop control circuitry is also capable of independently varying the gains of multiple gain stages of the variable gain control circuit to provide better control over the gain stages and better overall performance of the TIA circuit.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 3, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Georgios Asmanis, Faouzi Chaahoub
  • Patent number: 9143004
    Abstract: A method for charging an intermediate circuit capacitor in a precharging unit includes charging the intermediate circuit capacitor via a current source and adjusting the supplied current in such a manner that a constant power loss is produced in the current source during the entire charging operation. A circuit arrangement includes a battery which is connected to a current source which is connected to an intermediate circuit capacitor via a switch. An adjusting circuit is arranged in parallel with the current source and can be used to adjust the current for charging the intermediate circuit capacitor. The current is adjusted in such a manner that a constant power loss is produced in the current source during the entire charging operation.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: September 22, 2015
    Assignee: Rober Bosch GmbH
    Inventor: Stefan Butzmann
  • Patent number: 9071201
    Abstract: A low dissipation, low distortion amplifier includes a driver amplifier stage and a main output stage, with a plurality of impedance networks providing, among other things, feedback paths from outputs of the driver and main output stages to the input of the driver stage. The impedance networks also provide coupling paths from the outputs of the driver and main output stages to the load. The impedance networks can all be formed of resistors, capacitors, or network combinations thereof. An additional feedback path can be added from the load to the driver stage to flatten out the frequency response at low frequencies. The driver and main output stages may be operated in Class AB and B modes respectively, and/or in Class G or H modes. An intermediate amplifier driver stage may be added between the driver and main output stages.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: June 30, 2015
    Assignee: THX Ltd
    Inventors: Owen Jones, Lawrence R. Fincham
  • Patent number: 9007128
    Abstract: In an embodiment, a circuit includes a variable group delay configured to delay a wideband input signal to obtain a delayed input signal; a wideband operational amplifier configured to determine an error signal based on a difference between the delayed input signal and a linearized power amplifier output; a feedback amplifier configured to amplify the error signal to obtain an amplified error signal; and a directional combiner configured to combine the amplified error signal with the power amplifier output to obtain the linearized power amplifier output.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: April 14, 2015
    Assignee: Newlans, Inc.
    Inventor: Dev V. Gupta
  • Patent number: 8989307
    Abstract: A power amplifier system including a composite digital predistorter (DPD) ensuring optimized linearity for the power amplifier is described. In this system, a digital-to-analog converter (DAC), an analog filter, a first mixer, and the power amplifier are serially coupled to the composite DPD. A second mixer, a receive gain block, and an analog-to-digital converter (ADC) are serially coupled to the output of the power amplifier. A DPD training component is coupled between the inputs of the composite DPD and the ADC. The composite DPD includes a memory-based DPD, e.g., a memory polynomial (MP) DPD, a memoryless-linearizing DPD, e.g., a look-up table (LUT) DPD, and two multiplexers.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: March 24, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Hao Zhou, Ning Zhang
  • Publication number: 20150002225
    Abstract: A common source or common emitter LNA circuit for amplifying signals at an operating frequency f in a receiver circuit is disclosed. The LNA circuit comprises an input transistor arranged to, in operation, be biased to have a transconductance gm at the operating frequency f, and having a first terminal, which is a gate or base terminal, operatively connected to an input terminal of the LNA circuit. The LNA circuit further comprises a shunt-feedback capacitor operatively connected between the first terminal of the input transistor and a second terminal, which is a drain or collector terminal, of the input transistor. Furthermore, the LNA circuit comprises an output capacitor operatively connected between the second terminal of the input transistor and an output terminal of the LNA circuit. The output capacitor has a capacitance value CL<gm/f.
    Type: Application
    Filed: January 25, 2013
    Publication date: January 1, 2015
    Inventors: Sven Mattisson, Stefan Andersson
  • Publication number: 20140292413
    Abstract: A transimpedance pre-amplifier (TIA) with an improved bandwidth. In the TIA, a feedback circuit is added to a regulated cascode structure to be connected in parallel, so that an input resistance value is reduced and a bandwidth is easily broadened. Alternatively, an inductor is added to the regulated cascode structure, so that an input capacitance is reduced and bandwidth is easily broadened.
    Type: Application
    Filed: March 18, 2014
    Publication date: October 2, 2014
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young-Ho KIM, Sang-Soo LEE
  • Publication number: 20140232468
    Abstract: Aspects of the disclosure relate to a frequency suppression circuit arrangement, which allows at least one selected frequency band to be suppressed by coupling the frequency suppression circuit between the input and output of an RF power amplifier. The frequency circuit in the embodiments of the disclosure down-converts a feedback signal derived from the amplified output signal into baseband signals. Each of the baseband signals is fed into an inverting amplifier to generate a negative baseband signal. The negative baseband signal is subsequently filtered to selectively pass the negative baseband signal. The filtered signal is subsequently up-converted into an RF signal. The up-converted RF signal is combined and provided to a coupler connected at the input of the power amplifier such that when the input signal is amplified by the RF power amplifier any signals at the selected frequency can be suppressed.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 21, 2014
    Applicant: ROKE MANOR RESEARCH LIMITED
    Inventor: Anthony Peter HULBERT
  • Publication number: 20140197892
    Abstract: A power amplifier architecture for connecting a radio frequency (RF) transceiver to an antenna. An input matching circuit is connected to its input port, and an output matching circuit is connected to its output port. An amplifier circuit includes at least one amplifier active device with a first terminal connected to the input matching segment and a second terminal connected to the output matching segment. A first harmonic feedback circuit is connected across the amplifier active device. Voltage components of emissions of one or more harmonic frequencies of a carrier fundamental frequency generated by the amplifier active device is fed back with opposite phase to the first terminal of the amplifier active device. A negative feedback is defined at a level correlated with a gain level of the amplifier active device at the harmonic frequencies of the carrier fundamental frequency. Negative feedback is minimized at the carrier fundamental frequency.
    Type: Application
    Filed: January 10, 2014
    Publication date: July 17, 2014
    Applicant: RFAXIS, INC.
    Inventor: OLEKSANDR GORBACHOV
  • Publication number: 20140111281
    Abstract: A low dissipation, low distortion amplifier includes a driver amplifier stage and a main output stage, with a plurality of impedance networks providing, among other things, feedback paths from outputs of the driver and main output stages to the input of the driver stage. The impedance networks also provide coupling paths from the outputs of the driver and main output stages to the load. The impedance networks can all be formed of resistors, capacitors, or network combinations thereof. An additional feedback path can be added from the load to the driver stage to flatten out the frequency response at low frequencies. The driver and main output stages may be operated in Class AB and B modes respectively, and/or in Class G or H modes. An intermediate amplifier driver stage may be added between the driver and main output stages.
    Type: Application
    Filed: March 20, 2013
    Publication date: April 24, 2014
    Inventors: Owen Jones, Lawrence R. Fincham
  • Publication number: 20130293308
    Abstract: In an embodiment, a circuit includes a variable group delay configured to delay a wideband input signal to obtain a delayed input signal; a wideband operational amplifier configured to determine an error signal based on a difference between the delayed input signal and a linearized power amplifier output; a feedback amplifier configured to amplify the error signal to obtain an amplified error signal; and a directional combiner configured to combine the amplified error signal with the power amplifier output to obtain the linearized power amplifier output.
    Type: Application
    Filed: November 1, 2011
    Publication date: November 7, 2013
    Inventor: Dev V. Gupta
  • Patent number: 8564369
    Abstract: There is provided a linear amplifier capable of suppressing a reduction in bandwidth and reducing a ripple voltage by using a source follower and a local feedback loop. The linear amplifier includes an amplifier amplifying an input signal according to a difference in signal level between the input signal and a feedback signal, and a buffer buffering a signal amplified in the amplifier by a source follow method, suppressing a reduction in bandwidth of the signal, outputting the signal, and providing the bufferred signal to the amplifier as the feedback signal.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: October 22, 2013
    Assignees: Samsung Electro-Mechanics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Yu Sin Kim, Youn Suk Kim, Gyu Hyeong Cho, Chang Seok Chae, Young Sub Yuk
  • Publication number: 20130271220
    Abstract: Power consumption of a signal processing circuit is reduced. Further, power consumption of a semiconductor device including the signal processing circuit is reduced. The signal processing circuit includes a reference voltage generation circuit, a voltage divider circuit, an operational amplifier, a bias circuit for supplying bias current to the operational amplifier, and first and second holding circuits. The first holding circuit is connected between the reference voltage generation circuit and the bias circuit. The second holding circuit is connected between the voltage divider circuit and a non-inverting input terminal of the operational amplifier. Reference voltage from the reference voltage generation circuit and reference voltage from the voltage divider circuit can be held in the first and second holding circuits, respectively, so that the reference voltage generation circuit can stop operating. Thus, power consumption of the reference voltage generation circuit can be reduced.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 17, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kei Takahashi, Yoshifumi Tanada
  • Patent number: 8509629
    Abstract: The invention relates to amplifiers and in particular, to a transimpedance amplifier for high rate applications. Disclosed is a two stage transimpedance amplifier having a first stage comprising an amplifier and a load and a second stage comprising an amplifier and a resistor. Negative feedback is provided through a feedback resistor. Only two voltage conversions occur which reduces phase distortion, as compared to three stage transimpedance amplifiers which perform 3 voltage conversions.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: August 13, 2013
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Hehong Zou, Krishna Shivaram, Daniel Draper
  • Patent number: 8451061
    Abstract: In one embodiment, a method includes receiving a radio frequency (RF) at an antenna; generating negative feedback to linearize an amplifier by resistively or transformer coupling an output signal of a transistor of the amplifier to the input of the transistor; generating a rectified voltage by rectification of the output signal of the transistor; generating a constant reference voltage; and outputting a control voltage or a control current to the transistor based on the sum of the reference voltage and a first voltage derived from the rectified voltage. The output of the control voltage or control current facilitates control of an operating point of the transistor.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: May 28, 2013
    Assignee: Atmel Corporation
    Inventors: Michael Sagebiel, Stephan Gerlach
  • Publication number: 20120326790
    Abstract: A very low distortion amplifier using one or more error correction loops based on a balanced error negative feedback scheme intrinsically and easily reiterable. Such loops are applied to a generic amplifier block A1 in order to reduce its error in a wide frequency band, without substantially interfering, in the correction process, with the main path of the useful signal Vi to amplify, whereby the corrected amplifier preserves the same response, in time and frequency, the same dynamic behavior and the same stability margins in amplitude and phase, of the not corrected amplifier A1. This result is obtained by means of a balance and reference block A2, capable to decouple the error correction loop from the main path of the useful signal Vi in a very wide frequency band.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 27, 2012
    Inventors: GIOVANNI STOCHINO, Adrio PANTALEONI
  • Publication number: 20120274404
    Abstract: A mixed signal correlator utilizes coherent detection within a capacitance measurement application. In some applications, the mixed signal correlator is used to measure capacitance of a touch screen display. An external capacitor whose capacitance is measured is kept small for improved sensitivity and can be used for a variety of applications having varied integration periods for measurement. The external capacitor is kept small and can be used for varied applications by adjusting the output voltage within a range that is less than the supply voltage, and maintaining a count of the adjustments to later reconstruct an actual output voltage for the integration period. An output is a weighted sum of an analog integrator output and a digital counter output.
    Type: Application
    Filed: February 24, 2012
    Publication date: November 1, 2012
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Ozan E. Erdogan, Guozhong Shen, Rajesh Anantharaman, Ajay Taparia, Behrooz Javid, Syed T. Mahmud
  • Publication number: 20120218043
    Abstract: An amplifier comprises a main amplification stage and an auxiliary amplification stage. An input of the main amplification stage and an input of the auxiliary amplification stage are coupled to a common node, and an output of the main amplification stage is coupled to an output node. During activation, before power is supplied to the main amplification stage, the output node is coupled to a reference voltage (VREF). A quiescent voltage is then established at the common node by coupling power to the auxiliary amplification stage. Only then is power coupled to the main amplification stage and the reference voltage (VREF) de-coupled from the output node.
    Type: Application
    Filed: October 29, 2010
    Publication date: August 30, 2012
    Applicant: ST-Ericsson SA
    Inventor: Robert Hwat Hian Teng
  • Patent number: 8237505
    Abstract: This invention provides a low-current consumption type signal amplification circuit, which limits the output voltage to fix a lower-limit (upper-limit) saturation voltage of the amplification circuit at a predetermined lower-limit (upper-limit) limiting voltage. The signal amplification circuit comprises a negative feedback amplification circuit, a lower-limit voltage limiting circuit and an upper-limit voltage limiting circuit. The lower-limit voltage limiting circuit increases a resistance between an output terminal of the negative feedback amplification circuit and a ground terminal when the output voltage of the negative feedback amplification circuit falls below the lower-limit limiting voltage. The upper-limit voltage limiting circuit increases a resistance between the output terminal of the negative feedback amplification circuit and a high-potential side of a power supply when the output voltage of the negative feedback amplification circuit rises above the upper-limit limiting voltage.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: August 7, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Mutsuo Nishikawa, Katsuyuki Uematsu, Kazuhiro Matsunami
  • Publication number: 20120194274
    Abstract: An integrated circuit is described for providing a power supply to a radio frequency (RF) power amplifier (PA). The integrated circuit includes a low-frequency power supply path including a switching regulator and a high-frequency power supply path arranged to regulate an output voltage of a combined power supply at an output port of the integrated circuit for coupling to a load. The combined power supply is provided by the low-frequency power supply path and high-frequency power supply path. The high-frequency power supply path includes: an amplifier including a voltage feedback and arranged to drive a power supply signal on the high-frequency power supply path; and a capacitor operably coupled to the output of the amplifier and arranged to perform dc level shifting of the power supply signal.
    Type: Application
    Filed: January 9, 2012
    Publication date: August 2, 2012
    Inventors: Paul Fowers, Patrick Stanley Riehl
  • Publication number: 20120139639
    Abstract: Achievement of robust stability of a power amplifier (PA) that allows the sharing of the ground between the driver stages and the output stage is shown. A controlled amount of negative feedback is used to neutralize the local positive feedback that results from the driver-to-output stage ground sharing in the signal path, for example, a radio frequency (RF) signal path. The solution keeps a strong drive and a good performance of the PA. Exemplary embodiments are shown for the PA positive feedback neutralization. A first embodiment uses a ground signal divider while another embodiment uses a ground signal divider weighting technique.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 7, 2012
    Applicant: AMALFI SEMICONDUCTOR, INC.
    Inventors: Baker Scott, George Maxim, Stephen Franck, Chu Hsiung Ho
  • Publication number: 20120139637
    Abstract: There is provided a linear amplifier capable of suppressing a reduction in bandwidth and reducing a ripple voltage by using a source follower and a local feedback loop. The linear amplifier includes an amplifier amplifying an input signal according to a difference in signal level between the input signal and a feedback signal, and a buffer buffering a signal amplified in the amplifier by a source follow method, suppressing a reduction in bandwidth of the signal, outputting the signal, and providing the buffered signal to the amplifier as the feedback signal.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 7, 2012
    Inventors: Yu Sin KIM, Youn Suk Kim, Gyu Hyeong Cho, Chang Seok Chae, Young Sub Yuk
  • Patent number: 8183923
    Abstract: Constant and accurate signal gain systems based on controlling signal amplifier gain level by applying the signal amplifier output signal to a signal level divider with a set ratio. The output signal of the signal level divider is applied to one input of the gain control amplifier, which is a differential amplifier, while the signal amplifier input signal is applied to the other input. The gain control amplifier output level is used to control the gain level of the signal amplifier. The gain control amplifier output level forces by negative feedback the gain control amplifier input levels to be substantially equal thus maintaining the signal amplifier gain level substantially constant.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: May 22, 2012
    Inventor: Fred A Mirow
  • Patent number: 8149051
    Abstract: A solid-state image sensor capable of suppressing color mixture while suppressing increase of load capacitances of transfer gates and a short circuit between two adjacent transfer gates is provided. This solid-state image sensor comprises a plurality of transfer gates and a shielding material line blocking light incident from above a prescribed pixel upon another pixel adjacent to the prescribed pixel. The shielding material line has a downward projecting portion on a region corresponding to at least one transfer gate entering an ON-state in photoreception.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: April 3, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yoshinari Ichihashi, Ryu Shimizu, Kazuhiro Sasada
  • Publication number: 20120056674
    Abstract: In one embodiment, a method includes receiving a radio frequency (RF) at an antenna; generating negative feedback to linearize an amplifier by resistively or transformer coupling an output signal of a transistor of the amplifier to the input of the transistor; generating a rectified voltage by rectification of the output signal of the transistor; generating a constant reference voltage; and outputting a control voltage or a control current to the transistor based on the sum of the reference voltage and a first voltage derived from the rectified voltage. The output of the control voltage or control current facilitates control of an operating point of the transistor.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 8, 2012
    Inventors: Michael Sagebiel, Stephan Gerlach
  • Publication number: 20120056675
    Abstract: The present invention includes operational amplifier for an active pixel sensor that detects optical energy and generates an analog output that is proportional to the optical energy. The active pixel sensor operates in a number of different modes including: signal integration mode, the reset integration mode, column reset mode, and column signal readout mode. Each mode causes the operational amplifier to see a different output load. Accordingly, the operational amplifier includes a variable feedback circuit to provide compensation that provides sufficient amplifier stability for each operating mode of the active pixel sensor. For instance, the operational amplifier includes a bank of feedback capacitors, one or more of which are selected based on the operating mode to provide sufficient phase margin for stability, but also considering gain and bandwidth requirements of the operating mode.
    Type: Application
    Filed: November 14, 2011
    Publication date: March 8, 2012
    Applicant: Broadcom Corporation
    Inventor: Esin TERZIOGLU
  • Publication number: 20120049895
    Abstract: An amplifying circuit comprises: a first transistor, a second transistor, a third transistor and a fourth transistor provided to an input stage; and a first bias circuit. The input signal is input into a control terminal of the first transistor and a control terminal of the second transistor, a first terminal of the first transistor is connected to a first terminal of the third transistor, a first terminal of the second transistor is connected to a first terminal of the fourth transistor, a second terminal of the first transistor is connected to a first potential, a second terminal of the second transistor is connected to a second potential that is equal to or different from the first potential, a second terminal of the third transistor is connected to a third potential, a second terminal of the fourth transistor is connected to a fourth potential, the first bias circuit is connected between a control terminal of the third transistor and a control terminal of the fourth transistor.
    Type: Application
    Filed: July 26, 2011
    Publication date: March 1, 2012
    Applicant: ONKYO CORPORATION
    Inventors: Tsuyoshi KAWAGUCHI, Norimasa KITAGAWA, Mamoru SEKIYA, Naofumi SHIMASAKI, Yu TAKEHARA
  • Patent number: 8120428
    Abstract: Apparatus and methods are disclosed, such as those involving a low noise amplifier. One such apparatus includes a low noise amplifier circuit configured to receive a signal at an input node and to output an amplified signal at an output node. The low noise amplifier circuit includes a first transistor of a first polarity; and a second transistor of a second polarity complementary to the first polarity. The first and second transistors are connected in series between first and second supply voltage nodes via the output node. The circuit further includes a third transistor cascoded with one of the first transistor or the second transistor, but does not include a transistor cascoded with the other transistor. This configuration allows the low noise amplifier circuit to provide an increased high-frequency gain and linearity while having improved high-frequency system noise figure in, for example, deep submicron CMOS technology.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: February 21, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Antonio Montalvo, David McLaurin, Carl Grace
  • Publication number: 20110293115
    Abstract: An amplifier including an input stage, an output stage, an adjustable bias current generator and a level detector. The input stage may receive and amplify or buffer an input signal. The input stage may be biased by a first bias current. The output stage may supply an output signal to an amplifier load. The output stage may be biased with a second bias current. The adjustable bias current generator may be operatively coupled to the input stage and the output stage to supply these with the first and second bias currents, respectively. The level detector may be operatively coupled to the input signal and the adjustable bias current generator to control the first and second bias currents depending upon the input signal. The adjustable bias current generator may adjust the respective levels of first and second bias currents in opposite directions. Disclosed is an electroacoustical transducer incorporating the amplifier.
    Type: Application
    Filed: November 24, 2009
    Publication date: December 1, 2011
    Applicant: AUDIOASICS A/S
    Inventor: Jens Jørgen Gaarde Henriksen
  • Publication number: 20110235455
    Abstract: Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The “one-way” isolation circuit may allow the feedback signal to be coupled from a “downstream” node, such as an output node, to an “upstream” node, such as a node at which an error signal is generated to provide negative feedback. However, the “one-way” isolation circuit may substantially prevent variations in the voltage at the upstream node from being coupled to the capacitance in the isolation circuit. As a result, the voltage at the upstream node may quickly change since charging and discharging of the capacitance responsive to voltage variations at the upstream node may be avoided.
    Type: Application
    Filed: March 29, 2010
    Publication date: September 29, 2011
    Applicant: Micron Technology, Inc.
    Inventor: DONG PAN
  • Patent number: 8004363
    Abstract: A wideband low-noise amplifier of the present invention is designed such that an input terminal is connected to a base of a first transistor, one terminal of a first passive element, and one terminal of a third passive element; an emitter of the first transistor is grounded; a collector of the first transistor is connected to an output terminal, a base of a second transistor, one terminal of a capacitor, and one terminal of a second passive element; the other terminal of the first passive element is connected to the other terminal of the capacitor; an emitter of the second transistor is connected to the other terminal of the third passive element; and a power terminal is connected to a collector of the second transistor and the other terminal of the second passive element, wherein impedance of the third passive element is determined based on impedance of the first transistor whose emitter size is determined to suite desired saturation level of amplification, thus establishing input impedance matching.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: August 23, 2011
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Munenari Kawashima, Yo Yamaguchi, Kazuhiro Uehara, Kenjiro Nishikawa
  • Patent number: 7969246
    Abstract: Systems and methods are provided for positive and negative feedback of cascode transistors for a power amplifier. The systems and methods may include a first cascode stage comprising a first common-source device and a first common-gate device; a second cascode stage comprising a second common-source device and a second common-gate device; a first degenerative element or block provided for the first common-source device; a second degenerative element or block provided for the second common-source device; a first positive feedback block or element that connects a first gate of the first common-source device with a second drain of the second common-source device; and a second positive feedback block or element that connects a second gate of the second common-source device with a first drain of the first common-source device.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: June 28, 2011
    Assignee: Samsung Electro-Mechanics Company
    Inventors: Kyu Hwan An, Yunseo Park, Chang-Ho Lee
  • Publication number: 20110148527
    Abstract: An amplifying circuit arranged for converting an input signal into an amplified output signal comprising: an input node (11) at an input side of said circuit for receiving said input signal (pi); an output node (9) at an output side of said circuit for outputting said amplified output signal (io); a first gain element (M1) connected between said input and output nodes and provided for converting an input voltage taken from said input signal into a current for forming said amplified output signal; a negative feedback loop (3) over said first gain element, said negative feedback loop having first elements (5, 6) arranged for providing input matching; and a positive feedback loop (2) over said first gain element, said positive feedback loop having second elements (7, 8) arranged for providing additional input matching and gain enhancement of said first gain element.
    Type: Application
    Filed: July 17, 2009
    Publication date: June 23, 2011
    Applicant: STICHTING IMEC NEDERLAND
    Inventor: Sumit Bagga
  • Publication number: 20110140785
    Abstract: A CMOS amplifier with integrated tunable band-pass function, a tunable active resistor structure, a method of amplifying an input signal and a method of fabricating an amplifier. The tunable active resistor structure comprises two symmetrically cross-coupled transistors.
    Type: Application
    Filed: June 11, 2009
    Publication date: June 16, 2011
    Inventors: Yong Lian, Libin Yao, Xiaoyuan Xu, Xiaodan Zou
  • Publication number: 20110109392
    Abstract: Provided is a Low Noise Amplifier (LNA). Embodiments of the present invention provide LNAs including: a common gate amplifier circuit configure to amplify a signal of an input node to which an Alternating Current (AC) component is provided and transfer the amplified signal to an amplifier node; and a negative-feedback amplifier circuit configured to amplify a signal of the amplifier node, transfer the amplified signal to an output node, wherein the negative-feedback amplifier circuit includes a feedback capacitor and a feedback inductor connected in series between the amplifier node and the output node to form a negative feedback. the LNA of the present invention forms a negative feedback exclusive of a feedback resistance, such that a broad frequency bandwidth is obtained and noise and heat are reduced.
    Type: Application
    Filed: October 19, 2010
    Publication date: May 12, 2011
    Applicants: Electronics and Telecommunications Research Institute, Industry-University Cooperation Foundation Hanyang University
    Inventors: Jang Hyun PARK, Chang Sun Kim, Yea Chul Roh, Tae-Yeoul Yun, Hyun-kyu Park, Ji-Young Lee
  • Patent number: 7940120
    Abstract: The power amplifier mainly includes a main amplifier, two splitters, one combiner, one subtracter, two phase shifters, one attenuator and one error amplifier. The splitters, subtracter and combiner are designed in the form of 90-degree or quadrature hybrid couplers. A quadrature hybrid can be implemented with any lumped or transmission-line elements and has an important advantage compared to the in-phase splitter that at equal values of reflection coefficients from loads connected to the in phase and 90° phase shift terminals, the reflection wave is lacking at the main input terminal and, consequently, the input voltage standing wave ratio of a quadrature hybrid does not depend on the equal load mismatch level.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: May 10, 2011
    Assignee: Alcatel Lucent
    Inventors: Andrei Grebennikov, Florian Pivit
  • Publication number: 20110080220
    Abstract: A representative integrator includes an amplifier having an input and an output; a feedback loop coupled between the input and the output of the amplifier, the feedback loop comprising a compensated resistor circuit having a resistance value selected for reducing a loss factor of the integrator; and a control circuit coupled to an input of the compensated resistor circuit, the control circuit producing a control signal for controlling the compensated resistor circuit to substantially maintain the resistance value selected for reducing the loss factor of the integrator across a range of integrator temperatures.
    Type: Application
    Filed: October 7, 2009
    Publication date: April 7, 2011
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsien Tsai, Min-Shueh Yuan, Chien-Hung Chen
  • Patent number: 7898337
    Abstract: An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one compensation capacitor is coupled to provide negative feedback through the capacitor from the second amplifier stage to the first amplifier stage. The slew rate of the amplifier is enhanced by substantially reducing the negative feedback coupled through the capacitor during a period following the transition of a signal applied to an input terminal of the amplifier. If the first stage of the amplifier has complementary signal nodes, the negative feedback coupled through the capacitor may be reduced, for example, by closing a switch coupled between first and second complementary nodes of the first amplifier stage.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: March 1, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Taehee Cho
  • Patent number: 7889010
    Abstract: An improved compensation circuit with loop compensation is disclosed. The compensation circuit can get an equivalent large capacitance by amplifying a small capacitor. Hence, the compensation circuit can get a good compensation effect with a minimum chip area, hence lower cost.
    Type: Grant
    Filed: May 31, 2009
    Date of Patent: February 15, 2011
    Assignees: Vimicro Corporation, Wuxi Vimicro Corporation
    Inventor: Zhao Wang
  • Patent number: 7852158
    Abstract: An operational amplifier includes, between an input and an output of an operational amplifier (an operational amplification stage) 10, a feedback capacitor 34 connected in negative feedback, a phase control circuit 100 having a resistor element (a resistor unit) 30 connected in series to the feedback capacitor 34. Load capacitors (load units) 32 are connected on the output side of the operational amplifier 10 and driven by an output signal from the operational amplifier 10. In a case that the capacitance values of the load capacitor 32 and 33 are increased and the phase margin of the operational amplifier becomes excessive in comparison with the optimum value, a resistance value RO of the resistor element 30 is increased to control the phase margin of the operational amplifier so as to fall within the optimum range, and thus accelerated settling properties are realized.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Satoshi Kobayashi, Junji Nakatsuka
  • Publication number: 20100259237
    Abstract: An improved compensation circuit with loop compensation is disclosed. The compensation circuit can get an equivalent large capacitance by amplifying a small capacitor. Hence, the compensation circuit can get a good compensation effect with a minimum chip area, hence lower cost.
    Type: Application
    Filed: May 31, 2009
    Publication date: October 14, 2010
    Inventor: Zhao Wang
  • Publication number: 20100148876
    Abstract: An amplifier arrangement has an amplifier (3) with a signal input (31), a feedback input (32) and a signal output (33). A first coupling path (FB1), which has a first impedance element (R1), connects the feedback input (32) to the signal output (33). A second coupling path (FB2) has a filter device (4), a buffer circuit (5) and a second impedance element (R2) connected in series, and connects the feedback input (32) to the signal output (33) or to the signal input (31).
    Type: Application
    Filed: February 21, 2008
    Publication date: June 17, 2010
    Inventors: Thomas Fröhlich, Nicole Heule
  • Patent number: 7714644
    Abstract: An amplifier circuit block and a compensation circuit block are provided. The amplifier circuit block includes an analog adder for subtracting an output signal of the compensation circuit block from an input signal and an amplifier circuit operating in a wide band. The compensation circuit block includes an amplifier circuit with a low offset voltage and a low noise in a low frequency region, an analog adder block for subtracting an output signal of the amplifier circuit from an output signal of the amplifier circuit and generating a differential signal thereof, and a feedback circuit block for negatively feeding back the differential signal to the analog adder. The amplifier circuit block can reduce the offset voltage and the low-band noise by the negative feedback of the differential signal, and at the same time, the operation band of the entire amplifier circuit can be decided by the characteristic of the amplifier circuit.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: May 11, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Takemoto, Hiroki Yamashita, Tatsuya Saito
  • Publication number: 20100097146
    Abstract: This invention provides a low-current consumption type signal amplification circuit, which limits the output voltage to fix a lower-limit (upper-limit) saturation voltage of the amplification circuit at a predetermined lower-limit (upper-limit) limiting voltage. The signal amplification circuit comprises a negative feedback amplification circuit, a lower-limit voltage limiting circuit and an upper-limit voltage limiting circuit. The lower-limit voltage limiting circuit increases a resistance between an output terminal of the negative feedback amplification circuit and a ground terminal when the output voltage of the negative feedback amplification circuit falls below the lower-limit limiting voltage. The upper-limit voltage limiting circuit increases a resistance between the output terminal of the negative feedback amplification circuit and a high-potential side of a power supply when the output voltage of the negative feedback amplification circuit rises above the upper-limit limiting voltage.
    Type: Application
    Filed: October 5, 2009
    Publication date: April 22, 2010
    Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.
    Inventors: Mutsuo Nishikawa, Katsuyuki Uematsu, Kazuhiro Watsunami
  • Patent number: 7692486
    Abstract: An amplifier is disclosed that includes configurable feedback based on the output of a received signal strength indicator. The feedback may be increased for high received signal levels, and decreased for low received signal levels. In an embodiment, the configurable impedance may comprise a plurality of discrete impedance settings. Amplitude and/or time hysteresis may be incorporated.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: April 6, 2010
    Assignee: QUALCOMM, Incorporated
    Inventors: Mahim Ranjan, Li Liu