Abstract: A solid state power amplifier (SSPA) system may include a radio frequency (RF) input, an RF waveguide split block, multiple monolithic microwave integrated circuit (MMIC) power amplifier modules, and/or a heat spreader. An MMIC power amplifier module may include a backing, a board, at least one MMIC, and/or a cover. A method for dissipating heat within an SSPA may include receiving an RF signal, splitting the RF signal, amplifying multiple RF signals, combining the multiple RF signals, generating heat, and/or dissipating heat.

Abstract: A Doherty-amplifier system has several amplifier stages, of which the inputs are controlled via a control unit with different phase angles and/or signal amplitudes of an input signal. According to the invention, every output of every amplifier stage is connected directly to an antenna element, without the output signals from the amplifier stages being combined with one another before being supplied to the antenna elements.

Abstract: A power amplifier includes a first transformer, a first transistor, a first resistor, a second transformer, a second transistor, a second resistor, and a bias circuit. The first transformer drives the first transistor. The second transformer drives the second transistor. The first transformer is connected in series with the second transformer. The first transistor is connected in series with the second transistor. Therefore, the power amplifier has input impedance and output power both greater than those of a conventional power amplifier.

Abstract: The present invention relates to improved linearity of an active circuit, and more particularly, to an active circuit having improved linearity using a main circuit unit and an assistant circuit unit. According to the present invention, the common gate circuit includes a main circuit unit consisting of a common gate circuit having a drain terminal through which an input signal is output as an output signal, an assistant circuit unit having a common gate circuit in order to assist the linearity of the main circuit unit, a biasing unit for biasing the main circuit unit and the assistant circuit unit, respectively, and load stages connected to output stages of the main circuit unit and the assistant circuit unit, wherein the output stages of the main circuit unit and the assistant circuit unit are coupled to each other.

Abstract: Apparatus, method and article of manufacture are shown for linear signal modification. An input signal is modified by providing one or more non-linear current sources and regulating at least one of the one or more current sources to output a signal based on one or more of the input signal characteristics. The modification of the output signal includes both amplification and attenuation.

Abstract: A traveling wave amplifier includes a synthetic gate line, a synthetic drain line and a plurality of common drain driven cascode transistor circuits each connected between the synthetic gate line and the synthetic drain line.

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.

Abstract: The present invention provides a digital (computational) branch calibrator which uses a feedback signal sensed from an RF transmit signal path following the combining stage of LINC circuitry of a transmitter to compensate for gain and phase imbalances occurring between branch fragment signals leading to the combiner. The calibrator feeds a quiet (zero) base band signal through the transmit path during the calibration sequence (i.e. a period when data is not transmitted) and adjusts the phase and gain of the phasor fragment signals input thereto by driving the sensed output power to zero. The calibration is performed by alternating phase and gain adjustments with predetermined (programmable) and multiple update parameters stages (speeds). A baseband modulation is preferably used to distinguish false leakage (e.g. due to local oscillator, LO, feed through and DC offset in the base band Tx) from imbalance leakage.

Abstract: An amplifier that amplifies an input signal and provides the amplified signal to a load at a summing junction that has a first impedance value. The amplifier includes a splitter network receiving the input signal and providing a phase delayed signal and an undelayed signal; a carrier amplifier path amplifying the phase delayed signal and including a carrier amplifier and a first output match network coupled between the carrier amplifier and the summing node; and a peaking amplifier path amplifying the undelayed signal and including a peaking amplifier, a second output match network coupled to the peaking amplifier, and a phase delay element coupled between the second output match network and the summing node, wherein the phase delay element provides a degree of phase delay and has a designed characteristic impedance value that is larger than the first impedance value for increasing the off-state impedance of the peaking amplifier.

Abstract: Methods to implement power control in a digital power amplifier are described.

Abstract: A power amplifier (power amplifier) having multiple solid state sub-amplifiers connected in parallel between the power amplifier input and the power amplifier output are described. The signal input to the power amplifier is provided to an RF splitter connected between the power amplifier input connector and the input of each of the sub-amplifiers. The RF splitter splits the input power from the signal input and provides the power to the sub-amplifier inputs through input electrical paths. The input electrical paths from the power amplifier input to the sub-amplifiers are substantially physically identical. Each of the sub-amplifiers drive an input of an RF combiner connected between the outputs of the sub-amplifiers and the output of the power amplifier. The RF combiner combines the output power from each of the sub-amplifiers through output electrical paths, and provides the combined power to the power amplifier output.

Abstract: Amplification transistors respectively amplify an input signal. The output terminals of the amplification transistors are connected in series through respective transmission lines. A harmonic processing circuit is connected to an end of the array of collectors (output terminals) of the amplification transistors. The harmonic processing circuit suppresses harmonics included in output voltages of the amplification transistors. A transmission line and an MIM capacitor form a shorting circuit which establishes a short-circuit for the harmonics between the collector of the amplification transistor nearest to the harmonic processing circuit and the collector of the amplification transistor farthest from the harmonic processing circuit.

Abstract: A power amplifier system including: M main power amplifiers and one standby power amplifier, where M is a positive integer; an input switching module, connected to the inputs of the M main power amplifiers and the standby power amplifier; an output switching module, connected to the outputs of the M main power amplifiers and the standby power amplifier. In the system, M groups of signals are inputted to the input switching module, processed by the power amplifiers, and then outputted from the output switching module. The standby power amplifier is independent and is capable of taking place of the faulted main power amplifier immediately without a shut down. In the system there is no correlation between the isolation of various signals and the consistency of the power amplifies, which leads to a substantial decrease of the requirement on consistency of the power amplifiers.

Abstract: Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.

Abstract: An amplifier that amplifies an input signal and provides the amplified signal to a load at a summing junction that has a first impedance value. The amplifier includes a splitter network receiving the input signal and providing a phase delayed signal and an undelayed signal; a carrier amplifier path amplifying the phase delayed signal and including a carrier amplifier and a first output match network coupled between the carrier amplifier and the summing node; and a peaking amplifier path amplifying the undelayed signal and including a peaking amplifier, a second output match network coupled to the peaking amplifier, and a phase delay element coupled between the second output match network and the summing node, wherein the phase delay element provides a degree of phase delay and has a designed characteristic impedance value that is larger than the first impedance value for increasing the off-state impedance of the peaking amplifier.

Abstract: A circuit arrangement having a signal input configured to be supplied with a voltage signal; a first operational transconductance amplifier (OTA) having a voltage input that may be coupled to the signal input; at least one second OTA having a voltage input that may be coupled to the signal input; and at least one output capacitor which may be coupled to an output of the first OTA and to an output of the at least one second OTA, wherein an identical potential is set at the outputs of the first OTA and of the at least one second OTA.

Abstract: Two or more low noise amplifiers are configured to amplify received radio frequency input signals and one or more shared load or source degeneration inductors are configured to be used for each of the two or more low noise amplifiers. Further, the one or more shared inductors can be configured to be used for processing two or more signal bands in a multi-band communication system.

Abstract: A high-frequency power amplifier has an FET element having a unit FETs in multifinger form, and having a gate pad through which a signal is input, a source pad that is grounded, and a drain pad through which a signal is output. A high-frequency processing circuit includes series resonance circuits shunt-connected between the gate pads of the unit FETs and grounding ends. Two of the series resonance circuits have respective different resonance frequencies which correspond to second and higher harmonics of a frequency included in the operating frequency band of the FET element.

Abstract: A power amplifier includes: a first multi-finger FET formed on a semiconductor substrate; a second multi-finger FET formed on the semiconductor substrate; a first temperature detector which detects a channel temperature of the first FET; a second temperature detector which detects a channel temperature of the second FET; a third temperature detector which detects a temperature of the semiconductor substrate; a first detection circuit detecting a difference between an output of the first temperature detector and an output of the third temperature detector and converting the difference to thermoelectromotive force; a second detection circuit detecting a difference between an output of the second temperature detector and the output of the third temperature detector and converting the difference to thermoelectromotive force; and a comparator comparing outputs of the first and second detection circuits with each other to turn on one of the first and second switches and turn off the other.

Abstract: A solid state power amplifier (SSPA) system may include a radio frequency (RF) input, an RF waveguide split block, multiple monolithic microwave integrated circuit (MMIC) power amplifier modules, and/or a heat spreader. An MMIC power amplifier module may include a backing, a board, at least one MMIC, and/or a cover. A method for dissipating heat within an SSPA may include receiving an RF signal, splitting the RF signal, amplifying multiple RF signals, combining the multiple RF signals, generating heat, and/or dissipating heat.

Abstract: A nitride semiconductor device includes a substrate, a stacked semiconductor structure formed over the substrate and including a electron channel layer of an undoped nitride semiconductor and an electron supplying layer of an n-type nitride semiconductor formed epitaxially over the electron channel layer, the n-type nitride semiconductor having an electron affinity smaller than an electron affinity of said undoped nitride semiconductor and a two-dimensional electron gas being formed in the electron channel layer along an interface to the electron supply layer, a gate electrode formed over the stacked semiconductor structure in correspondence to a channel region, and source and drain electrodes formed over the stacked semiconductor structure in ohmic contact therewith respectively at a first side and a second side of the gate electrode, the stacked semiconductor structure including, between the substrate and the electron channel layer, an n-type conductive layer and a barrier layer containing Al formed consecu

Abstract: Embodiments of the present invention may provide a Doherty amplifier that includes a first amplifying path and at least one second amplifying path. The first amplifying path may include a carrier amplifier to amplify an input signal in a Class 1 mode. The second amplifying path may include a supplementary input matching circuit to input-match the input signal, a phase shifter to phase-shift an output from the supplementary input matching circuit, and a peak amplifier to amplify an output from the phase shifter in a Class 2 mode. The second amplifying path may further include a supplementary output matching circuit to output-match an output from the peak amplifier. The second amplifying path may provide an equivalent amplified output equivalent to the first amplifying path by cooperation of the supplementary input matching circuit and the supplementary output matching circuit.

Abstract: A distributed amplifier uses non-uniform filtering structures to provide better control over pass-band and stop-band characteristics. The various sections can have different tap coefficients. A notch filter can be implemented for interference suppression or pulse shaping in an ultra-wideband transceiver.

Abstract: The performance of an amplifying system is improved by achieving adequate matching. The amplifying system for amplifying signals includes distributing means 1 that distribute a signal, a carrier amplifier 2 that amplifies the distributed first signal in Class AB, a peak amplifier 4 that amplifies the distributed second signal in Class B or Class C, a first transmission line having a given electric length and being connected to an output of the carrier amplifier, a second transmission line having a given electric length and being connected to an output of the peak amplifier, and a combining end 18 for combining an output of the first transmission line and an output of the second transmission line.

Abstract: A multi-frequency and multi-mode power amplifier is provided. The amplifier has a carrier power amplifier and a peaking power amplifier. The carrier power amplifier receives a first signal and outputs a first amplified signal, in which a first transistor size adjusting unit is included to adjust an equivalent transistor size based on a mode indication signal. The peaking power amplifier receives a second signal and outputs a second amplified signal, in which a second transistor size adjusting unit is included to adjust an equivalent transistor size based on the mode indication signal.

Abstract: An amplifier includes a carrier amplifier which performs signal amplification at all times, a peak amplifier which operates only at a time when the high electric power is outputted, a combiner which combines the output from the carrier amplifier and the peak amplifier, and a distributor which distributes an input signal to the carrier amplifier and the peak amplifier. The carrier amplifier and the peak amplifier are included in a single package transistor.

Abstract: Microwave coupling network comprising a passive resistive pi net and a coupling capacitor is coupled to a branching point. The branching point is coupling to respectively a plurality of common drain FET amplifier stages or respectively to common collector BJT amplifier stages, wherein respectively the source, or respectively the emitter, is coupled to at least one output port.

Abstract: There is provided a method that comprises identifying a parasitic signal transfer in a filter using a signal-directed graph; and adding compensation paths to the filter to reduce or eliminate the effect of the parasitic signal transfer A corresponding filter is provided which comprises a plurality of amplifier stages that generate one or more filter poles; at least one component coupled to at least one of the amplifier stages, the component causing a parasitic effect in the filter; and means for applying a compensation current to the at least one amplifier stage to reduce or eliminate the parasitic effect.

Abstract: A power amplifier has at least a first amplifier circuit with an output port and at least a second amplifier circuit with an output port. The power amplifier further has at least a coupler with a first and a second input port and a first and a second output port. The first input port of the coupler is coupled with the output port of the first amplifier circuit and the second input port of the coupler is coupled with the output port of the second amplifier circuits. The power amplifier further has a switch with at least an input terminal and at least two output terminals. The input terminal of the switch is coupled with the first output port of the coupler, wherein each of the output terminals of the switch is connected with a respective terminal impedance, the terminal impedances having different impedance values.

Abstract: In one embodiment of a transmitting output stage, a first controllable amplification device with a first amplification factor and a second amplification device with a second amplification factor are provided. The two amplification devices are connected on the input side to a signal input. The transmitting output stage comprises a first matching network, which is connected on the input side to an output of first amplification device. A second matching network is also provided, which is installed switchably between an output of the second amplifier stage and the input of the first matching network and which, in one operating mode of the transmitting output stage in which only the second amplifier stage is being used, is connected between the second amplifier stage and the first matching network. Other embodiments are also disclosed.

Abstract: A configurable LNA architecture for a multi-band RF receiver front end comprises a bank of LNAs, each optimized to a different frequency band, wherein each LNA has a configurable topology. Each LNA comprises a plurality of amplifier stages, each stage including an RF transistor having a different width. The transistor widths in adjacent amplifier stages may be binary weighted, or may be sized to achieve a constant gain step. By selectively enabling and disabling RF transistors, the effective transistor width of the LNA can be controlled with a fine granularity. A DAC generates a bias voltage with a small quantization step, additionally providing a fine granularity of gain control. The LNAs are protected by overvoltage protection circuits which shield transistors from a supply voltage in excess of their breakdown voltage. A source degeneration inductor presents a real resistance at inputs of the LNAs, without introducing thermal noise.

Abstract: A wide bandwidth, high power amplifier system for amplifying a signal in a radio frequency (RF) system in a specific bandwidth within the frequency range from 1 MHz to 100 GHz. The system includes a number of amplifier modules and an equal number of input transformers connected in series, with each input transformer providing an input signal to one amplifier module. It also includes an equal number of output transformers connected in series with each output transformer receiving an input signal from one amplifier module. The series of input transformers, the series of output transformers and the amplifier modules each provide an impedance matched approximately to the impedance of the RF system.

Abstract: A high power, high frequency, solid state power amplifier system includes a plurality of input multiple port splitters for receiving a high-frequency input and for dividing the input into a plurality of outputs and a plurality of solid state amplifier units. Each amplifier unit includes a plurality of amplifiers, and each amplifier is individually connected to one of the outputs of multiport splitters and produces a corresponding amplified output. A plurality of multiport combiners combine the amplified outputs of the amplifiers of each of the amplifier units to a combined output. Automatic level control protection circuitry protects the amplifiers and maintains a substantial constant amplifier power output.

Abstract: A power amplifier according to the present invention is operated by switching a main power amplifier and a subsidiary power amplifier. The idle current of the subsidiary power amplifier is smaller than the idle current of the main power amplifier. Each of the main power amplifier and the subsidiary power amplifier has a former amplification element for amplifying RF signals, a latter amplification element for amplifying output signals from the former amplification element, a former bias circuit for driving the former amplification elements, and a latter bias circuit for driving the latter amplification elements, respectively. The interval between the latter amplification element of the main power amplifier and the latter amplification element of the subsidiary power amplifier is not more than 100 ?m. The interval between the latter amplification element of the main power amplifier and the latter bias circuit of the subsidiary power amplifier is not less than 200 ?m.

Abstract: A radial power divider-combiner is disclosed. Such a radial divider-combiner may include a plurality of waveguides, each of which extends between a central monopole antenna and a respective peripheral monopole antenna. Such a waveguide may have a central portion with a height-to-width ratio of two, and a peripheral portion having an aspect ratio of one. To improve impedance-matching, a transformer portion may be disposed between the central portion and the peripheral portion. Such a transformer portion may have any number of sections, from one to infinity, with each section having a respective height between that of the central portion and that of the peripheral portion. In the extreme case, where the number of “sections” is infinite, the height of the transformer portion may vary linearly from that of the central portion and that of the peripheral portion.

Abstract: An integrated power amplifier (PA) module formed on a substrate includes a first cluster of transistor cells positioned in a first portion of the substrate; a second cluster of transistor cells positioned in a second portion of the substrate and spaced apart from the first portion; and a combiner coupled to the first and second clusters to combine the output of the first and second clusters.

Abstract: A power amplifier comprises a control signal generator providing a first and a second signal, a first amplifier comprising a first transistor and a first cascode transistor for the amplification of the first signal, a second amplifier comprising a second transistor and a second cascode transistor for the amplification of the second signal, and an output coupler which couples an output of the first amplifier and an output of the second amplifier to an output terminal of the amplifier arrangement.

Abstract: A power amplifier includes a front-stage amplifier including first and second transistors connected in parallel, and a rear-stage amplifier including a third transistor. The first transistor is biased into near-Class A without a distortion compensation circuit. The second and third transistors are biased into near-Class B with a distortion compensation circuit. The gain characteristics of the first to third transistors are adjusted so that the concave portion of the gain characteristics of the front-stage amplifier and the convex portion of the gain characteristics of the rear-stage amplifier match each other, to thereby flatten the gain characteristic of the entire power amplifier.

Abstract: An amplifier has an input port, an output port, N gain elements in parallel, an input power splitter coupled between the input port of the amplifier and the input ports of the N gain elements, an output resistor chain extending between the output ports of the first through Nth gain elements, and an output power combiner coupled between the output ports of the N gain elements and the output port of the amplifier. The output power combiner presents a corresponding input impedance to each of the N gain elements. At least two of the input impedances presented by the output power combiner to the N gain elements are substantially different from each other.

Abstract: To improve operation during cutback power mode by reducing gain expansion, sections of a multi-section amplifier are selectively biased. During cutback power condition, fewer than all sections of the multi-section amplifier are biased. Selective biasing reduces power consumption and obtains desired output power. To reduce gain expansion, a bias resistor is provided between one or more sections to establish a small or leakage bias current into non-enabled or non-biased sections. This leakage bias current weakly biases the non-enabled sections allowing small signal amplification by the non-enabled sections. The combined amplification of the enabled section and the weakly biased section provide greater initial gain at lower power input signal levels thereby reducing gain expansion.

Abstract: An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.

Abstract: A new Class L amplifier which dynamically switches between multiple pairs of power rails, and has the ability to select the most advantageous combination of rails for the minimization of power dissipation in the amplifier. In one embodiment, a bridged amplifier system includes two Class L amplifiers to drive a load.

Abstract: Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.

Abstract: A power amplifier (power amplifier) having multiple solid state sub-amplifiers connected in parallel between the power amplifier input and the power amplifier output are described. The signal input to the power amplifier is provided to an RF splitter connected between the power amplifier input connector and the input of each of the sub-amplifiers. The RF splitter splits the input power from the signal input and provides the power to the sub-amplifier inputs through input electrical paths. The input electrical paths from the power amplifier input to the sub-amplifiers are substantially physically identical. Each of the sub-amplifiers drive an input of an RF combiner connected between the outputs of the sub-amplifiers and the output of the power amplifier. The RF combiner combines the output power from each of the sub-amplifiers through output electrical paths, and provides the combined power to the power amplifier output.

Abstract: There are included a Wilkinson divider/combiner dividing an input signal, amplifying elements amplifying outputs of the Wilkinson divider/combiner, and a Wilkinson divider/combiner combining outputs of respective amplifying elements. A variable capacitor element is connected to a branch point of a signal transmission path in the Wilkinson divider/combiner. A capacitance value of the variable capacitor element is controlled in correspondence with a frequency of an input signal, whereby a matching frequency is corrected to increase an operating frequency band.

Abstract: A distortion cancellation amplifier is described having a main amplifier and an error amplifier. The main amplifier, in response to an input signal, generates an output signal having an amplified signal component and a distortion signal component. The error amplifier is sized and biased to generate, in response to the same input signal, a distortion signal component that has substantially the same magnitude as the distortion signal component of the main amplifier. The distortion signal component from the error amplifier is subtracted from the output signal of the main amplifier.

Abstract: An amplifier has an input port, an output port, N gain elements in parallel, an input power splitter coupled between the input port of the amplifier and the input ports of the N gain elements, an output resistor chain extending between the output ports of the first through Nth gain elements, and an output power combiner coupled between the output ports of the N gain elements and the output port of the amplifier. The output power combiner presents a corresponding input impedance to each of the N gain elements. At least two of the input impedances presented by the output power combiner to the N gain elements are substantially different from each other.

Abstract: Polar modulation transmission apparatus capable of suppressing power loss of a battery supply line to a high-frequency power amplifier regardless of whether transmission power is high or low is provided. Operation control section (120) performing control in such a manner that a battery voltage (S21) converted as a result of operation of a DC/DC converter (111) is applied to amplitude signal amplifying section (106) or halting operation of the DC/DC converter (111) in such a manner that battery voltage (S20) is applied directly from the battery (130) based on a transmission power control signal (S14). As a result, when transmission power is low, power loss at the amplitude signal amplifying section (106) is suppressed by DC/DC converter (111), unnecessary operation of DC/DC converter (111) is halted when transmission power is high, and power loss can be suppressed regardless of whether transmission power is high or low.

Abstract: The present invention provides an amplifier unit including a carrier amplifier biased for Class A or Class AB operation; a peak amplifier biased for Class B or Class C operation, wherein an input signal is input to the carrier amplifier and the peak amplifier, and wherein output signals from the carrier amplifier and the peak amplifier are synthesized to output therefrom; a comparator configured to compare a gate bias voltage of a transistor device in the peak amplifier with a predetermined threshold voltage and output a first output signal; and a failure detection circuit configured to output a second output signal indicating presence or absence of failure, based on the first output signal received from the comparator.