Abstract: An embodiment of the present invention provides a system comprising a summing device and first amplifier portion. The summing device is coupled to an output node. The first amplifier portion is coupled between an input node and the summing device. The first amplifier portion includes a first amplifier, a first filter, and first and second switches. The first amplifier is coupled between the input node and the summing device on a first path. The first filter is coupled between the input node and the first amplifier on a second path, the second path being in parallel to the first path. The first switch is coupled between the input node and the first amplifier along the first path. The second switch is coupled between the input node and the first filter along the second path.

Abstract: An amplifier capable of lowering an electrical current flowing in a peak amplifier before a carrier amplifier becomes saturated to thereby improve the efficiency of an entirety of the amplifier is provided. The amplifier includes a carrier amplifier circuit having an amplifying element operable in class-AB or class-B, and a plurality of peak amplifier circuits which have amplifying elements operating in class-B or class-C and which are arranged to start an operation in stages in response to an input level. An output of the carrier amplifier circuit and outputs of the peak amplifier circuits are combined together for signal output. One of the peak amplifier circuits which is rendered operative at the lowest input level is smaller in saturation output than the carrier amplifier circuit.

Abstract: A power divider includes first and second amplifiers (AMP1, AMP2), and an isolation circuit. AMP1 includes a first capacitor (C1) with one end connected to input, a first FET (FET1) having a gate connected to the other end of C1, a first feedback circuit connecting the FET1 drain and the one end of C1, a first source circuit connecting the FET1 source and ground, and a second capacitor connecting the FET1 drain and a first output. AMP2 includes a third capacitor with one end connected to input, a second FET (FET2) having a gate connected to the other end of the third capacitor, a second feedback circuit connecting the FET2 drain and the one end of the third capacitor, a second source circuit connecting the FET2 source and ground, and a fourth capacitor connecting the FET2 drain and a second output. The isolation circuit connects the FET1 and FET2 sources.

Abstract: A power amplifier comprises a series stack of power amplifier devices, connected in parallel to the amplifier input for receiving an RF input signal, and having output terminals being connected in series to the amplifier output. An intermediate coupling capacitor is connected between each adjacent pair of power amplifier devices in the series stack of power amplifier devices for DC isolation of said power amplifier devices. This reduces the required DC supply voltage, as well as allowing shorting of individual power amplifier devices in response to variation in the DC supply voltage.

Abstract: A multi-function MMIC operated by a switch using an amplifier is disclosed. A switch may be configured by connecting an input or an output of a plurality of amplifiers, and an insertion loss may be reduced by selecting a transmission mode or a reception mode of an MMIC using the switch. A noise characteristic, a power characteristic, and a gain characteristic may also be improved.

Abstract: An amplifier having a Doherty-type architecture and a method for operation thereof are provided. The amplifier comprises a main amplifier path comprising a main amplifier, an auxiliary amplifier path comprising an auxiliary amplifier, and an signal preparation unit configured to develop a main amplifier input signal for the main amplifier path and an auxiliary amplifier input signal for the auxiliary amplifier path based on an amplifier input that is to be amplified and a transition threshold associated with the amplifier input. By driving the main and auxiliary amplifiers as a function of the transition threshold, the gain of the Doherty-type amplifier may be increased.

Abstract: According to one embodiment, there is a semiconductor device including a first active element, a second active element connected in parallel with the first active element, and a first stabilization circuit connected between a gate of the first active element and a gate of the second active element and configured with a parallel circuit of a gate bypass resistor, a gate bypass capacitor, and a gate bypass inductor, the first stabilization circuit having a resonant frequency equal to an odd mode resonant frequency.

Abstract: A 3-way Doherty amplifier has an amplifier input and an amplifier output. The amplifier has a main stage, a first peak stage and a second peak stage. The amplifier has an input network connecting the amplifier input to the inputs of the stages, and an output network connecting the stages to the amplifier output. The output network implements a phase shift of 90° between the output of the main stage and the amplifier output; a phase shift of 180° between the output of the first peak stage and the amplifier output; and a phase shift of 90° between the third output and the amplifier output.

Abstract: A signal processing method and power amplifier device are disclosed. The method may include receiving a signal to be transmitted, decomposing an original signal into a plurality of smaller constant-amplitude signals, wherein a vector sum each of the smaller constant-amplitude signals equals the original signal, amplifying the smaller constant-amplitude signals by an amplification factor using a plurality of amplifiers, wherein one or more of the plurality of amplifiers are enabled based on the amplitude of the original signal, combining the amplified smaller constant-amplitude signals into the original signal, the original signal being amplified by the amplification factor, wherein the amplified original signal is transmitted.

Abstract: An amplifier includes first and second amplifier circuits. The first amplifier circuit amplifies positive-phase input signal to obtain a first positive-phase signal and amplifies negative-phase input signal to obtain a first negative-phase signal. The second amplifier circuit includes first and second amplifier units. The first amplifier unit amplifies positive-phase input signal to obtain a second positive-phase signal and amplifies negative-phase input signal to obtain a second negative-phase signal. The second amplifier unit amplifies positive-phase input signal to obtain a third positive-phase signal and amplifies negative-phase input signal to obtain a third negative-phase signal. The positive-phase output signal is sum of first and second positive-phase signals while the negative-phase output signal is sum of first and second negative-phase signals.

Abstract: Doherty and distributed amplifier (DA) designs are combined to achieve, wideband amplifiers with high efficiency dynamic range. A modified Doherty amplifier includes a wideband phase shifter providing first and second outputs, a main amplifier coupled to the first output, an auxiliary amplifier coupled to the second output, and a wideband combining network combining the outputs in phase. A multi-stage DA has a main output and a termination port, and a phase delay module and transforming network allowing power at the termination port to be combined in phase with power at the main output. In one combination, one or more stages of the DA may comprise a Doherty amplifier. In another combination, a modified series-type Doherty amplifying system is achieved by cascading main and auxiliary DAs. In any combination, Doherty topology may include a bias control module.

Abstract: The invention relates to an integrated Doherty amplifier with an input network connecting the input to the main stage and to the peak stage, and with an output network connecting the main stage and the peak stage to the output. The output network has a shunt capacitor to signal-ground in parallel to a parasitic capacitance of the main stage, and has a shunt inductor between the main stage and signal ground. The shunt configuration enables to use the MMIC Doherty amplifier in a wide frequency range. At least some of the inductors of the input network and/or output network are implemented using bond wires. Their orientations and locations provide minimal mutual electromagnetic coupling between the wires and the return RF current paths.

Abstract: A RF power amplifying device is constituted by a system of a balanced amplifier including first phase shifters, a first RF power amplifier, a second RF power amplifier, second phase shifters, and a power combiner. Transmitting power Pout is detected by a first power level detector connected to an output of the first RF power amplifier, a second power level detector connected to an output of the second RF power amplifier, and an adder. A level control signal from a level control circuit controls transmitting power in response to a transmitting signal with wanted power level and a detected signal of the adder.

Abstract: The invention relates to a circuit arrangement (30, 40, 70, 80, 90) of a low-noise linear input amplifier comprising a parallel circuit of a common-base circuit (20) and a common-emitter circuit (30), the emitters of two first transistors (Q3, Q4) are interlinked and the bases of two second transistors (Q1, Q2) are intercoupled, the collectors are interconnected in parallel with the output, and the source voltage (VG) is interlinked with the emitters of the second transistors (Q1, Q2) and with the bases of the first transistors (Q3, Q4), in which a linearization of the output current (OUTLNA1,2) as a function of the source voltage (VG) is achieved by a linearization of the transfer function, such as the tangential hyperbolic function, of the first and second transistors (Q1, Q2, Q3, Q4).

Abstract: A high power, high frequency, solid state power amplifier system includes a plurality of input multiple port splitters for receiving a high-frequency input and for dividing the input into a plurality of outputs and a plurality of solid state amplifier units. Each amplifier unit includes a plurality of amplifiers, and each amplifier is individually connected to one of the outputs of multiport splitters and produces a corresponding amplified output. A plurality of multiport combiners combine the amplified outputs of the amplifiers of each of the amplifier units to a combined output. Automatic level control protection circuitry protects the amplifiers and maintains a substantial constant amplifier power output.

Abstract: Distributed band reject filters are disclosed. A first radio frequency band reject filter is disclosed having a splitter having a first input port, a first output port and a second output port, the splitter being operable on an input signal applied to the first input port to provide a respective output signal proportional to the input signal at each of the first and second output ports, the output signals having a phase shift between 45 degrees and 135 degree with respect to the input signal, as well as first, second and third acoustic resonators coupled respectively to the first input port, the first output port and the second output port.

Abstract: In a power amplification circuit an output signal is generated by combining the power of a first and second signal that have been amplified separately. An input signal is received that indicates a desired amplitude and phase of the output signal. A controllable phase shift circuit adapts the phase of first and second signals dependent on the desired amplitude, so that, when the signals with the adapted phases are combined, the resulting output signal will have an envelope with the desired amplitude. A time dependent common mode phase shift is applied to both the first and second signal. A control circuit selects the time dependent common mode phase shift as a function of the desired amplitude of the output signal, to compensate for envelope amplitude dependence of a common phase shift introduced by the amplification.

Abstract: There is provided a power amplifier capable of improving harmonics characteristics of an output signal of an amplifier circuit by compensating a phase of the output signal. A power amplifier according to an aspect of the invention may include: an amplification section having a plurality of amplification units each amplifying a radio frequency (RF) signal according to a gain being controlled; a phase correction section performing phase correction by removing harmonic components of respective output signals from the plurality of amplification units of the amplification section; and a coupling section coupling the respective output signals phase-corrected by the phase correction section.

Abstract: A two-channel operational amplifier circuit includes a first operational amplifier and a second operational amplifier. In a first frame period, the two-channel operational amplifier circuit switches a first input stage, a first gain stage and a first output stage to work between a working voltage and a half working voltage, and switches a second input stage, a second gain stage and a second output stage to work between the half working voltage and a ground voltage. In a second frame period, the two-channel operational amplifier circuit switches the second input stage and the second gain stage to work between the working voltage and the half working voltage, and switches the first input stage and the first gain stage to work between the half working voltage and the ground voltage.

Abstract: The present invention relates to a power supply control network of an amplifying active elements system enabling at least one control signal to be transmitted to N different control systems of the power supply voltage of P different composed active amplifying elements. It comprises a set of distributor elements of power supply control signals connected in cascade.

Abstract: A semiconductor package device comprises a first amplifier block, at least one further amplifier block operably coupled in parallel with the first amplifier block between a common input and a common output, and at least one stabilisation network operably coupled between a node of the first amplifier block and a corresponding node of the at least one further amplifier block. The at least one stabilisation network comprises an inductance operably coupled between the corresponding nodes of the first and at least one further amplifier blocks, and a capacitance operably coupling a mid-point of the inductance to a ground plane.

Abstract: Embodiments of circuits, apparatuses, and systems for a switchable radio frequency (RF) power amplifier are disclosed. Some embodiments include a matching network configured to alternatively provide a first load impedance or second load impedance based at least in part on an amplification mode of a power amplification section. Other embodiments may be described and claimed.

Abstract: An amplifier circuit can include a first supply terminal to receive a first reference voltage; a second supply terminal to receive a second reference voltage; a first pair of circuit paths extending between the first and second supply terminals and including a respective output terminal, the first pair of circuit paths including a first pair of transistors, each having a gate connected to a respective one of the input terminals and a source connected to the first supply terminal, and a second pair of transistors, each having a gate connected via a first impedance to a gate of a respective first transistor, and a source coupled to the second supply terminal.

Abstract: A power amplifier filter for radio-frequency signals having an outphasing type architecture comprising a first stage (2) capable of generating, from an input signal s(t), two signals s1(t), s2(t) having an identical amplitude but phase shifted relative to each other, a second amplifier stage (3) for said signals s1(t), s2(t), and a third recombining stage (4) capable of summing the two signals s?1(t), s?2(t) obtained from second stage (3), characterized in that recombining stage (4) includes an assembly of acoustic wave resonators coupled to each other, some of these resonators referred to as “input resonators” being connected to the outputs of second stage (4) and others of these resonators referred to as “output resonators” being connected to the output terminals of the filter.

Abstract: The present invention relates to a power amplifier; and, more particularly, to a Doherty power amplifier. The power amplifier includes at least one carrier amplifier; at least one peaking amplifier arranged in parallel with the carrier amplifier in such a manner that the carrier amplifier and the peaking amplifier collectively operate as a Doherty amplifier; a plurality of input matching circuits, at least one of which is respectively connected to an input ends of the carrier amplifier and the peaking amplifier; at least one impedance control circuit, each of which is connected to an output end of each carrier amplifier for controlling a load line impedance of the said each carrier amplifier; at least one output matching circuit directly or indirectly connected to output ends of the impedance control circuit and the peaking amplifier; and at least one first delay circuit for matching delays between the carrier amplifier and the peaking amplifier.

Abstract: An amplification cell employing a linearization scheme and an active inductor using the same are provided. The active inductor includes: first and second amplification cells each including a main amplifying unit amplifying an input signal, an auxiliary amplifying unit connected in parallel to the main amplifying unit and eliminating nonlinear characteristics of the main amplifying unit while amplifying the input signal, and a negative load unit connected to an output terminal of the main amplifying unit and that of the auxiliary amplifying unit; a plurality of load resistors for tuning frequency; and a plurality of capacitors for tuning frequency, wherein an output from the first amplification cell is negatively fed back to the second amplification cell, an output from the second amplification cell is negatively fed back to the first amplification cell, and the plurality of load resistors and the plurality of capacitors are disposed on negative feedback paths of the first and second amplification cells.

Abstract: A combination amplifier (1,1a) is provided which comprises a carrier amplifier (7,7a) and a series connection of a first peak amplifier (9,9a) and a second peak amplifier (11,11a) which are provided with a phase-shifted input signal relative to the input signal supplied to the carrier amplifier, wherein a transfer characteristics of the combination amplifier may be optimized by independently adjusting transfer characteristics of the carrier amplifier, the first peak amplifier and the second peak amplifier. Thereby, a linearity and/or an efficiency of the combination amplifier may be improved compared to a conventional Doherty amplifier.

Abstract: A combination amplifier, in particular a Doherty amplifier allowing dynamic biasing, is provided, the combination amplifier comprising a first amplifier (3,3a,3b) having a first input terminal (11,11a,11b) and a first output terminal (25,25a,25b); a second amplifier (5,5a,5b) having a second input terminal (27,27a,27b) and a second output terminal (29,29a,29b); a first impedance inverter (Li, 43b) connected between the first input terminal and the second input terminal; and an envelope detector (33,33a,33b) comprising a detector output terminal and a detector input terminal which is connected to the first output terminal.

Abstract: An integrated power amplifier can include a carrier amplifier, where the carrier amplifier is connected to a first quarter wave transformer at the input of the carrier amplifier.

Abstract: A method of optimizing performance of a multiple path amplifier includes: splitting an input signal to derive a respective sub-signal for each branch of the multiple path amplifier; independently pre-distorting each sub-signal using a known performance characteristic of its associated branch of the multiple path amplifier; and supplying each pre-distorted sub-signal to its associated branch of the multiple amplifier.

Abstract: Provided is a power amplifier device. The power amplifier device includes: a cutoff unit cutting off a direct current (DC) component of a signal delivered from a signal input terminal; a circuit protecting unit connected to the cutoff unit and stabilizing a signal delivered from the cutoff unit; and an amplification unit connected to the circuit protecting unit and amplifying a signal delivered from the circuit protecting unit, wherein the amplification unit comprises a plurality of transistors connected in parallel to the circuit protecting unit and the circuit protecting unit comprises resistors connected to between bases of the plurality of transistors.

Abstract: A buffer varies the size of its output stage in response to a varying capacitive load. The capacitive load may vary in a predictable or a random manner. The buffer includes an operational amplifier having an output stage of multiple transistors, selectively connected in parallel. During operation, data regarding the size of the capacitive load is obtained and used to determine the size of the output stage. In general, as the capacitive load increases, the number of transistors connected in parallel at the output stage also increases.

Abstract: A multi-band power amplifier in a wireless communication system includes: a plurality of matching circuits connected in parallel to an output stage of the power amplifier and corresponding to a plurality of different operation frequencies, respectively; and a plurality of high-frequency amplifiers connected to the plurality of matching circuits, respectively. The plurality of high-frequency amplifiers are selectively operated depending on the operation frequencies. Each of the high-frequency amplifiers may include a plurality of stages. Each of the matching circuits may include a high-frequency transformer.

Abstract: Systems and methods are provided for power amplifiers with discrete power control. The systems and methods may include a plurality of unit power amplifiers; a plurality of primary windings, wherein each primary winding is connected to at least one respective output port of a respective one the plurality of unit power amplifiers; a secondary winding inductively coupled to the plurality of primary windings, where the secondary winding provides an overall output; a bias controller, where the bias controller provides a respective bias voltage based at least in part on a level of output power to one or more of the plurality of unit power amplifiers; and a switch controller, where the switch controller operates to activate or deactivate at least one of the plurality of unit power amplifiers via a respective control signal.

Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.

Abstract: Disclosed herein is an asymmetric power divider. The asymmetric power divider includes a power dividing unit, a first matching network, and a second matching network. The power dividing unit supplies different amounts of power to a carrier amplifier and a peaking amplifier, which are connected in parallel. The first matching network is connected between the power dividing unit and the carrier amplifier so as to perform impedance matching between the power dividing unit and the carrier amplifier. The second matching network is connected between the power dividing unit and the peaking amplifier so as to perform impedance matching between the power dividing unit and the peaking amplifier.

Abstract: In one embodiment, a power amplifier may include an output stage with multiple transformers and corresponding matching capacitances. The capacitances may include a first matching capacitance coupled in parallel with a secondary coil of a first transformer and a second matching capacitance coupled in parallel with a secondary coil of a second transformer, where the secondary coils are coupled in series in an output stack configuration. By accounting for parasitics present in the power amplifier, the first matching capacitance can be designed to have a greater capacitance than the second matching capacitor, even where the first and second transformers are configured to output substantially equal power levels.

Abstract: Systems and apparatus for converting an input current signal into two or more output voltage signals on an integrated circuit. In one aspect, an integrated circuit includes a first trans-impedance amplifier that includes a first cascode amplifier; and a second trans-impedance amplifier that includes a second cascode amplifier, the second cascode amplifier and the first cascode amplifier sharing an input transistive element; where the first cascode amplifier is coupled to one or more first switches that disable the first trans-impedance amplifier, the second cascode amplifier is coupled to one or more second switches that disable the second trans-impedance amplifier, and control logic coupled to the one or more first switches and the one or more second switches disables at least one of the first trans-impedance amplifier or the second trans-impedance amplifier.

Abstract: A device for amplifying signals over a wide frequency range features stacked amplifying modules connected between a DC voltage source and an electrical ground. The stacking configuration reuses the DC current produced the voltage source, and thus reduces the amount of operational DC current permitting the use of lower voltage, higher frequency devices to be used. The amplifying modules are fed signals which are different versions of an input signal, and the output signals are AC coupled using capacitors to balance out gain imbalances and asymmetries between the amplifying modules.

Abstract: Systems and methods for providing an adaptive bias circuit that may include a differential amplifier, low-pass filter, and common source amplifier or common emitter amplifier. The adaptive bias circuit may generate an adaptive bias output signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit may increase the bias voltage or bias current of the adaptive bias output signal. A power amplifier (e.g., a differential amplifier) may be biased according to the adaptive bias output signal in order to reduce current consumption at low power operation levels.

Abstract: An amplifier circuit includes a first unit and a second unit. The first unit has a first amplifying unit, wherein the first amplifying unit provides a first main circuit unit and a first assistant circuit unit, and the first assistant circuit unit is configured for assisting the linearity of the first main circuit unit. The second unit includes a second amplifying unit, wherein the second amplifying unit has a second main circuit unit and a second assistant circuit unit, and the second assistant circuit unit is configured for assisting the linearity of the second main circuit unit. The first amplifying unit is configured for conducting in one half cycle of an input signal, and the second amplifying unit is configured for conducting in the other half cycle of the input signal.

Abstract: A stacked pre-driver stage and a power amplifier including the stacked pre-driver stage are described. The stacked pre-driver stage comprises stacked pre-drivers arranged in series between a supply voltage and a reference voltage. Each pre-driver includes a pre-driving amplifier, together with MOS transistors. Each pre-driver is subject, in operation, to a voltage difference which is inferior to a maximum allowed use voltage of the MOS transistors with a largely reduced voltage drop across the regulator included in the power amplifier.

Abstract: There is disclosed an amplifier module which may include a plurality of N circuit devices, each of which may have at least two stages of amplification. Each circuit device may additionally have a DC input power terminal, a DC power return terminal, and at least one bias voltage terminal. The DC power terminals of the N circuit devices may be connected in series. A bias voltage network may have at least N taps, and each of the N taps may be connected to a bias voltage terminal of a corresponding one of the N circuit devices.

Abstract: A power amplifier circuit includes an unequal power splitter that splits an input signal using an unequal power split and provides a first power level signal and a second power level signal. A first amplifier path includes a first transistor amplifier that amplifies the first power level signal, and a second amplifier path includes a second transistor amplifier that amplifies the second power level signal. The second transistor amplifier is configured to turn on at a different power level of the input signal than the first transistor amplifier. An unequal combiner combines the amplified first power level signal and the amplified second power level signal.

Abstract: A Doherty amplifier is provided. The Doherty amplifier includes a first path circuit including a carrier amplifier and a first impedance adjusting circuit connected with the carrier amplifier; and a second path circuit including a peaking amplifier, a second impedance adjusting circuit connected with the peaking amplifier, and a peaking amplifier bias circuit connected with the peaking amplifier. At least one among an impedance of the first impedance adjusting circuit, an impedance of the second impedance adjusting circuit, and a bias of the peaking amplifier bias circuit is adjusted in response to a control signal.

Abstract: Shared-current electronic systems (120, 130, 140, 150, 160, 170, 180, 190, 200, 210, and 220) include two or more electronic devices, such as an electronic device (Q1), a baseband processor (110), and a multiplier/up-converter (112), that are connected in dc series or dc series-parallel, that may be connected in rf series, and that either fixedly or variably share portions of a dc source voltage. Various embodiments produce separate rf outputs, variably shift the phase of a single rf output, variably shift rf power between/among rf outputs, or produce a frequency-compressed modulation. The apparatus includes means (122, 162, 162A, and/or 162B) for precisely proportioning the regulated dc source voltage to one or more of the dc series-connected electronic devices irrespective of production variations in operating parameters of the electronic devices and/or drift of the electronic devices.

Abstract: A power amplifier includes a plurality of amplification paths in which at least one amplification path is selectively enabled and disabled, wherein each amplification path includes an output impedance modification element and an output phase shift element that is operable independently from the output impedance modification element, and wherein the output impedance modification element in each amplification path provides selective impedance for each amplification path.

Abstract: A solid state power amplifier (SSPA) system may include a radio frequency (RF) input, an RF waveguide split block, multiple monolithic microwave integrated circuit (MMIC) power amplifier modules, and/or a heat spreader. The power amplifier modules and RF waveguide may be distributed about the heat spreader in different planes. Furthermore, the power amplifier modules may be located on opposite sides of the heat spreader and nonplanar to the waveguide split block. A method for dissipating heat within an SSPA may include receiving an RF signal in a first plane, amplifying the RF signal in another plane, and combining the RF signal in yet another plane.

Abstract: In one embodiment, an apparatus includes a driver and a receiver. The driver has an output, wherein the output of the driver has an associated output termination. In addition, the receiver has an input, wherein the input of the receiver has an associated input termination. An interface between the output of the driver and the input of the receiver operates according to a set of one or more timing parameters, wherein the input termination, the output termination, and the set of timing parameters correspond to a bandwidth for data transfer or frequency for data transfer across the interface between the output of the driver and the input of the receiver.

Abstract: An amplifying circuit includes amplifying unit comprising a first transistor unit having a gate width that is controllable and is controlled based on a first control signal.