Abstract: A high-frequency amplifier with high linearity is provided that is easy to integrate and is resistant to variations in transistor characteristics due to process variation. The high-frequency amplifier includes a bias circuit to bias an amplifying element that amplifies high frequencies. The bias circuit has a feedback circuit including a feedback loop in which a circuit with low pass characteristics and having a capacitor one end of which is grounded is inserted. A stable bias voltage is thus provided, which makes it possible to improve the linearity of the high-frequency amplifier.

Abstract: A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.

Abstract: A common-base amplifier for a bipolar junction transistor or a heterojunction bipolar transistor employs an active current source output biasing to provide for improved power output in a power saturation region providing increased power for a given transistor area such as may be advantageous in mobile radio transmitters or the like.

Abstract: There is disclosed an amplifier module which may include a plurality of N circuit devices, each of which may have at least two stages of amplification. Each circuit device may additionally have a DC input power terminal, a DC power return terminal, and at least one bias voltage terminal. The DC power terminals of the N circuit devices may be connected in series. A bias voltage network may have at least N taps, and each of the N taps may be connected to a bias voltage terminal of a corresponding one of the N circuit devices.

Abstract: The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a sense amplifier includes a sense amplifying circuit sensing and amplifying data loaded on a bit line with a first power. A power supplying unit provides the first power to the sense amplifying circuit. A decoupling unit generates a decoupling noise with a second power and provides the decoupling noise to the first power voltage. The decoupling noise is maintained for a period including a time point of an operation of the sense amplifying circuit and a predetermined time thereafter.

Abstract: Bias circuitry that may be used within a communications or other device includes a first current mirror having first and second transistors with sources coupled to ground and operable to receive a reference current at a drain of first transistor. A second current mirror has first and second transistors with drains coupled to a battery voltage supply. A third current mirror has first and second transistors with drains coupled to sources of the first and second transistors of the second current mirror, respectively. A biasing transistor couples between the second transistor of the first current mirror and the first transistor of the third current mirror and operable to receive a tuning input voltage at its gate. A resistive element coupled between the second transistor of the third current mirror and ground produces a bias voltage produced at a connection of the resistive element and the second transistor of the third current mirror.

Abstract: A voltage converter includes a plurality of capacitors and corresponding first switch elements, the capacitors coupled in series and arranged to each charge to a voltage level during a first clock period, the voltage level determined by a supply voltage level, the number of capacitors and a value of each capacitor; and a plurality of second switch elements configured to cause the plurality of capacitors to be connected in parallel and to discharge into an output capacitor during a second clock period, the output capacitor charged to a discrete voltage output level so that the output capacitor provides the discrete voltage output level, wherein the discrete voltage output level is less than the supply voltage level and wherein the discrete voltage output level is used to develop a bias signal that is supplied to a power amplifier element.

Abstract: A charge pump power supply for an audio power amplifier integrated circuit has an operating mode selected according to an indication of operating environment and/or a process position of the integrated circuit. The operating mode selects the output voltage provided by the charge pump and may also select efficiency by selecting a frequency of operation of the charge pump and/or the effective size of a switching transistor bank. The selection is made in conformity with an indication of a process position of the integrated circuit and/or an indication of an environment of the integrated circuit, such as temperature, power supply voltage and/or load impedance values, and generally also in conformity with a volume (gain) setting, or a detected signal level, so that internal power consumption of the amplifier and charge pump is reduced when a high signal level is not being reproduced at the audio power stage.

Abstract: High-efficiency envelope tracking (ET) methods and apparatus for dynamically controlling power supplied to radio frequency power amplifiers (RFPAs). An exemplary ET circuit includes a switch-mode converter coupled in parallel with a split-path linear regulator. The switch-mode converter is configured to generally track an input envelope signal Venv and supply the current needs of a load (e.g., an RFPA). The split-path linear regulator compensates for inaccurate envelope tracking by sourcing or sinking current to the load via a main current path. A current sense path connected in parallel with the main current path includes a current sense resistor used by a hysteresis comparator to control the switching of the switch-mode converter. The split-path linear regulator is configured so that current flowing in the current sense path is a lower, scaled version of the current flowing in the main current path.

Abstract: A transimpedance amplifier having open-loop DC control is provided. The open-loop feedback control may provide a DC bias that is configurable based on the characteristics of an input device, such as, a photodiode or a magnetoresistor. The open-loop feedback control may provide quick recovery from voltage level variations and may provide stability for the amplifier.

Abstract: Methods, circuits and apparatus for biasing an amplifier to maintain consistent operational characteristics over variations in fabrication processes and operational temperature conditions are disclosed. A bias is determined by first comparing output voltages of replica circuits of the amplifier during an offset canceling phase. The output voltages are differently driven by an offset induced by a first reference current and the offset is canceled in response to the first comparing step. The output voltages are secondly compared during a calibration phase and a calibration bias current is adjusted in response to the second comparing step. The amplifier bias is determined based on the calibration bias current. The process is periodically repeated in response to operational variations.

Abstract: Aspects of a system for a power amplifier with an on-package matching transformer may include a DC/DC converter that enables generation of a bias voltage level within an IC die based on an amplitude of an input signal to a PA circuit within the IC die. The bias voltage level may be applied to a transformer, which is external to the IC die but internal to an IC package containing the IC die and/or a circuit board containing the IC package. One or more amplifier bias voltage levels, derived from the bias voltage level applied to the transformer, may be applied to the PA circuit.

Abstract: A power amplifier for use in a radio frequency (RF) transmitter or other device exhibits improved protection from voltage standing wave ratio (VSWR) issues emanating from avalanche currents. The amplifier circuit includes a power transistor having a base terminal, and a mirror transistor having a collector terminal and a base terminal. The base terminal is coupled to the collector terminal of the mirror transistor to thereby provide a bias current to the base terminal of the mirror transistor. The base terminal is also coupled to the base terminal of the power transistor to thereby form a base bias feed node for a current mirror arrangement. A static or variable impedance is coupled to the base bias feed node to sink current and to thereby maintain the proper bias current at the base terminal of the mirror transistor to thereby continue operation of the mirror transistor while avalanche conditions exist.

Abstract: A power amplifier module comprises a power amplifier circuit having an output power level controlled by a power supply voltage. A power supply transistor controls the power supply to the power amplifier circuit from a drive signal which is received from a drive circuit. The drive circuit generates the drive signal in response to a power level input signal, which specifically may correspond to a power ramping for a GSM cellular communication system. The power amplifier module furthermore comprises a detection circuit which determines an operating characteristic of the power supply transistor. The operating characteristic is preferably a saturation characteristic. A control circuit controls the drive signal in response to the operating characteristic. The control circuit preferably controls the drive signal such that the power supply transistor does not enter the linear region for a Field Effect Transistor and the saturated region for a bipolar transistor.

Abstract: A Bi-Directional and Adjustable Current Source (“BACS”) for providing an amplifier input with a voltage signal that is linear, where an output of the BACS and the amplifier input are shunted with a capacitor, is described. The BACS may include a first switch in signal communication with a high voltage reference and a first current source in signal communication with the first switch. The BACS may also include a second switch in signal communication with a low voltage reference and a second current source in signal communication with the second switch. The BACS may further include a directional current element in signal communication with both the first current source, the second current source, the output of the BACS, the amplifier input, and the capacitor, where the directional current element is configured to prevent current flow from the output BACS to the first current source.

Abstract: Embodiments relate to a current cell circuit in a digital-analog converter. According to embodiments, a current cell circuit in a digital-analog converter may include a current source connected to a power voltage terminal to generate current having a predetermined magnitude, a first current switch transferring current provided from the current source to a first output terminal, a first current generator detecting output voltage from the first output terminal and generating the amount of reduced current from the detected voltage, and a first current supplier supplying the amount of current generated from the first current generator to the first current switch. According to embodiments, current variations at a constant output voltage may be minimized. This may make it possible to obtain more stable frequency characteristics.

Abstract: A broadband signal amplifier includes one of more broadband amplifier circuits, each dynamically controlled in response to a total power level of signals applied thereto to reduce linearity in response to a reduction of input signal strength. A filter may couple the output of the broadband amplifier circuits to each other to form a tandem arrangement. Power detectors are connected to detect and provide outputs indicative of the total power levels of the signals applied to respective broadband amplifiers. A control unit is connected to and receives the output from the power detectors and, in response, provides a control signals to the broadband amplifier circuit so as to operate each over portions of their operating characteristic curves that provide only that degree of linearity necessary to limit distortion to a predetermined or dynamically adjustable maximum acceptable level.

Abstract: Power amplifying systems and modules and components therein are designed based on CRLH structures, providing high efficiency and linearity.

Abstract: A bias circuit for applying a bias voltage to a nonlinear amplification circuit, including a constant-current source; and a first, second, third, and fourth transistors, wherein a current mirror circuit is configured by the first transistor and the second transistor, and the bias voltage is outputted from the drain of the second transistor, gate lengths and gate widths of the first and second transistor are the same, gate lengths of the first to fourth transistor are the same, and gate lengths and gate widths of the first, second, third, and fourth transistor are configured so that k4?0.5?k3?0.5 is approximately 1, where k3 stands for a ratio of a gate width of the third transistor to the gate width of the first transistor and k4 stands for a ratio of a gate width of the fourth transistor to the gate width of the first transistor.

Abstract: To reduce pop or click during turn-on, a method and apparatus are provided. Initially, a plurality of current sources in the amplifier is actuated. The amplifier is transitioned from an off-state to an on-state in a class B amplifier mode by de-coupling each input node of an output stage of the amplifier from a voltage rail, and the amplifier is transitioned from the on-state in the class B amplifier mode to an on-state in a class AB amplifier mode by actuating at least a portion of an intermediate circuit in the amplifier.

Abstract: An operational amplifier includes an amplifying circuit and a bais current generating circuit. The bias current generating circuit generates a bias current to the amplifying circuit. The amplifying circuit comprises a current adjusting unit and a current mirror. The current adjusting circuit has a storage element, receives a reference current and generating a passing current. The passing current is gradually adjusted utilizing the storage element according to a control signal. The current mirror receives the passing current to generate the bias current.

Abstract: An amplifier including a first transistor including a gate coupled to an input terminal and a grounded source; a load resistor provided between a drain of the first transistor and a power supply; an output terminal coupled to a node between the drain of the first transistor and the load resistor; a feedback path coupled to the input terminal and the output terminal and including a resistor and a capacitor; a bias voltage generator applying a gate bias voltage to the gate of the first transistor in response to an enable signal; a supply resistor provided between an output node for the gate bias voltage of the bias voltage generator and the gate of the first transistor; and an enable switch lowering a resistance value between the output node for the gate bias voltage and a node in the feedback path.

Abstract: In an output stage of an operational amplifier, first and second transistors each provide a collector current under quiescent conditions to first and second current sources. A resistor receives a portion of one the collector currents and produces a resistor voltage in response. An output transistor provides a quiescent current having a value calculated as a function of the resistor voltage and a base-emitter voltage of the second transistor.

Abstract: A method and apparatus for testing a data signal amplifier having an output signal power dependent upon multiple signal power control parameters, e.g., signal gain control and amplifier bias current control.

Abstract: The present invention provides compensation for distortions in a multi-stage amplifier having a gain expansion characteristic. The present invention also provides an approach for using an amplification stage biased in a state close to B-class, which exhibits high power with added efficiency at low output, in order to have a gain expansion characteristic in all stages of a multi-stage amplifier. The amplifier of the present invention has a gain expansion characteristic which presents an increase in gain in response to an increase in input power or output power in a certain range of the input power or the output power.

Abstract: To reduce pop or click during turn-on, a method and apparatus are provided. Initially, a plurality of current sources in the amplifier is actuated. The amplifier is transitioned from an off-state to an on-state in a class B amplifier mode by de-coupling each input node of an output stage of the amplifier from a voltage rail, and the amplifier is transitioned from the on-state in the class B amplifier mode to an on-state in a class AB amplifier mode by actuating at least a portion of an intermediate circuit in the amplifier.

Abstract: A voltage converter includes a plurality of capacitors and corresponding first switch elements, the capacitors coupled in series and arranged to each charge to a voltage level during a first clock period, the voltage level determined by a supply voltage level, the number of capacitors and a value of each capacitor; and a plurality of second switch elements configured to cause the plurality of capacitors to be connected in parallel and to discharge into an output capacitor during a second clock period, the output capacitor charged to a discrete voltage output level so that the output capacitor provides the discrete voltage output level, wherein the discrete voltage output level is less than the supply voltage level and wherein the discrete voltage output level is used to develop a bias signal that is supplied to a power amplifier element.

Abstract: The RF power amplifier includes first and second amplifiers Q1 and Q2 as final-stage amplification power devices connected in parallel between an input terminal RF_In and an output terminal RF_Out. The amplifiers Q1 and Q2 are formed on one semiconductor chip. The first bias voltage Vg1 of the amplifier Q1 is set to be higher than the second bias voltage Vg2 of the amplifier Q2 so that the amplifier Q1 is operational between Class B and AB, and Q2 is operational in Class C. The first effective device size Wgq1 of the amplifier Q1 is intentionally set to be smaller than the second effective device size Wgq2 of the amplifier Q2 beyond a range of a manufacturing error of the semiconductor chip. An RF power amplifier that exhibits a high power-added efficiency characteristic regardless of whether the output power is High or Low can be materialized.

Abstract: An operational amplifier capable of enhancing slew rate is disclosed. The operational amplifier includes a first current generator for generating a first bias current, a second current generator for generating a second bias current, an amplification stage, coupled to the first current generator, for generating a amplification signal according to an input signal, an output stage, coupled to the second current generator and the amplification stage, for generating an output signal according to the amplification signal, and a bias current allocation unit, coupled to the first current generator, the second current generator, the amplification stage and the output stage, for reallocating current intensities of the first bias current and the second bias current according to a control signal.

Abstract: Aspects of a method and system for a highly efficient power amplifier (PA) utilizing dynamic biasing and predistortion are presented. Aspects of the system may include a processor that enables computation of a value of a variable bias component of a bias current based on a bias slope value and an amplitude of an envelope input signal. The processor may enable computation of a value of the bias current based on the selected constant bias current component value and the variable bias current component value. A PA may enable generation of an output signal in response to a generated baseband signal by utilizing the bias current to amplify an amplifier input signal. The bias current may be generated based on the envelope input signal. A feedback signal may be generated based on the output signal, which may be used to predistort a subsequent baseband signal.

Abstract: Systems and methods for providing a self-mixing adaptive bias circuit that may include a mixer, low-pass filter or a phase shifter, and a bias feeding block. The self-mixing adaptive bias circuit may generate an adaptive bias signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit increases the bias voltage or bias current such that the amplifier will save current consumption at low power operation levels and obtain better linearity at high power operation levels compared to conventional biasing techniques. Moreover, the adaptive bias output signal can be used to cancel the third-order intermodulation terms (IM3) to further enhance the linearity as a secondary effect.

Abstract: An amplifier system may include an output stage configured to provide an amplified output signal at an output thereof based on an input signal, the output stage being connected between first and second supply voltages. A dynamic power supply control system provides the first and second supply voltages, the dynamic power supply being configured to adjust the first and second supply voltages as a function of the input signal such that a difference between the first and second supply voltages remains substantially constant.

Abstract: An analog amplifier includes at least one signal path. Each of the at least one signal path extends between an input and an output and includes a load device coupled to the output and a transistor coupled to the input. The analog amplifier further includes a dither current source selectively coupled to one of the at least one signal path. The dither current source is capable of supplying dither current to the load device of the selected signal path directly by bypassing the transistor of the selected signal path.

Abstract: An amplifier arrangement has an amplifier (3) with a signal input (31), a feedback input (32) and a signal output (33). A first coupling path (FB1), which has a first impedance element (R1), connects the feedback input (32) to the signal output (33). A second coupling path (FB2) has a filter device (4), a buffer circuit (5) and a second impedance element (R2) connected in series, and connects the feedback input (32) to the signal output (33) or to the signal input (31).

Abstract: A cascode amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor and a bias circuit. Each of the transistors has a gate electrode, a first electrode and a second electrode, a first electrode of the first transistor is coupled to a second electrode of the second transistor, a first electrode of the third transistor is coupled to a second electrode of the fourth transistor, and gate electrodes of the third and the fourth transistors are coupled to gate electrodes of the first and the second transistors, respectively. The bias circuit is coupled to the first electrode of the fourth transistor, and is used for biasing a voltage level at the first electrode of the fourth transistor to make the second and the fourth transistors operate in a same region.

Abstract: A bias circuit including: a first current source which generates a first current; a second current source which generates a second current having a temperature-to-output current characteristic that an output current characteristic increases or decreases with a change in temperature to intersect with that of the first current; a first current-voltage conversion circuit which converts the first current to a first voltage; a second current-voltage conversion circuit which has an input terminal and converts a current inputted into the input terminal to a second voltage; a comparison circuit which compares the first voltage and the second voltage and generates a third current according to a result of the comparison; an addition unit which adds the third current to the second current and inputs a resulting current to the input terminal; and a voltage-current conversion circuit which converts the second voltage to a fourth current for bias.

Abstract: A bias circuit 12 includes: a transistor Q5 operable to supply, to an amplifier 11, a bias current in accordance with a base current supplied thereto; a transistor Q3 operable to pass a current in accordance with a reference voltage Vref; a transistor Q2 operable to correct, in accordance with the current passed by the transistor Q3, the base current to be supplied to the transistor Q5, so as to compensate a temperature characteristic represented by the transistor Q5; and a bias changing section (of a transistor Q4, and resistances R5, R6, and R7), connected to a base of the transistor Q5, operable to change, in accordance with a control voltage VSW, an amount of the base current to be supplied to the transistor Q5. The amplifier 11 amplifies, by using the bias current supplied by the bias circuit 12, a radio frequency signal having been inputted thereto.

Abstract: A buffer amplifier has high input impedance and is less affected by temperature by supplying independent bias power to each of amplification units. The buffer amplifier includes a bias supply unit supplying bias power having a preset voltage level, an amplification unit receiving preset driving power and the bias power from the bias supply unit to amplify an input signal, and a compensation unit compensating for current unbalance of the driving power supplied to the amplification unit.

Abstract: Provided is a radio frequency (RF) amplifier. The RF amplifier includes an amplification circuit amplifying an RF signal, a bias voltage generation circuit supplying a bias voltage of the amplification circuit, and a first bias resistor connected between the amplification circuit ad the bias voltage generation circuit, and having a predetermined resistance allowing the bias voltage to be affected by the RF signal.

Abstract: A linearizer for reducing intermodulation distortion in a non-linear device. The novel linearizer includes an input port for receiving a signal from the device and a circuit for effecting gain expansion on the signal that counteracts a gain compression of the device. In an illustrative embodiment, the circuit includes a starved limiter in shunt with the device, implemented using a pair of biased diodes D1 and D2. The first diode D1 is connected to ground and the second diode D2 is coupled to the signal. In an alternate embodiment, the linearizer also includes a second pair of biased diodes D3 and D4, D3 connected to ground and D4 coupled to the signal, and a plurality of reactive elements for increasing the operational bandwidth of the linearizer.

Abstract: A power amplifier circuit includes two amplifier subsections and delay elements coupled in parallel. An input received by the second amplifier subsection is a delayed version of the input received by the first amplifier subsection. The output of the first amplifier subsection is delayed such that the delayed output of the first amplifier subsection is in phase with the output of the second amplifier subsection. For low output power operation, only the first amplifier subsection is enabled. For high output power operation, both the first and the second amplifier subsections are enabled. The first and the second amplifier subsections operate as saturated amplifiers. A first variable output power control signal controls the output power of the first amplifier subsection, and a second variable output power control signal controls the output power of the second amplifier subsection.

Abstract: A radio frequency signal is input to the bases of transistors via respective capacitors, is amplified, and is output from the collectors of the transistors. The emitter of each transistor is grounded. A bias current input from a bias circuit is supplied to the bases of the transistors via respective resistors both during low-output operation and during high-output operation. The collectors of the transistors are connected via an impedance circuit to a bias voltage input terminal. Therefore, during high-output operation, a direct current offset voltage is generated by the impedance circuit based on a portion of a radio frequency signal output from the collectors, thereby further increasing the bias current.

Abstract: In one embodiment, the present invention includes an amplifier having an input to receive a radio frequency (RF) signal from an output node of a source. An input stage coupled to the amplifier input may include one or more components to aid in processing of incoming signals. One such component coupled between the source and the input of the amplifier is a coupling capacitor used to maintain a bias voltage of the amplifier at a different potential than a DC voltage of the output node. In certain applications, the amplifier and the coupling capacitor may be integrated on a single substrate.

Abstract: Embodiments of the invention show a bias circuit for providing a biasing signal at a bias connection. The bias circuit includes a bias transistor and a feedback node, wherein the feedback node is coupled to a control terminal of the bias transistor via a first impedance element. The feedback node is furthermore coupled to the bias connection via a second impedance element. The control terminal of the bias transistor is coupled to the bias connection via a bypass-coupling path, which bypasses the first impedance element and the second impedance element, such that there is a feedback path via the bypass-coupling path and via the bias transistor from the bias connection to the feedback node.

Abstract: A driver amplifier operative from a single DC voltage supply, coupled directly to the output load without the need for DC coupling capacitors used for preventing DC reaching the output load. An onboard power supply generates a negative voltage rail that powers the output amplifiers, allowing driver amplifier operation from both positive and negative rails. Since the amplifiers can be biased at ground potential (0 volts), no significant DC voltage exists across the load and the need for DC coupling capacitors is eliminated.

Abstract: A cascode circuit for a high-gain or high-output millimeter-wave device that operates with stability. The cascode circuit including two cascode-connected transistors includes: a first high electron mobility transistor (HEMT) including a source that is grounded; a second HEMT including a source connected to a drain of the first HEMT; a reflection gain restricting resistance connected to the gate of the second HEMT, for restricting reflection gain; and an open stub connected to a side of the reflection gain restricting resistance which is opposite the side connected to the second HEMT, for short-circuiting high-frequency signals at a predetermined frequency and nearby frequencies.

Abstract: Various embodiments of a hybrid class AB super follower circuit are provided.

Abstract: A method and an NE for controlling power amplification are provided. The method for controlling power amplification includes: outputting a voltage signal according to the state of an NE; applying the voltage signal to a grid electrode or a base electrode of at least one power amplifier transistor in a power amplifier. Thus, static power dissipation of the power amplifier can be eliminated when no RF power is output, and the efficiency of the power amplifier can be improved by using the above method and NE.

Abstract: A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.

Abstract: A semiconductor integrated circuit device includes: an amplifier circuit which respectively has one or more input terminals and one or more output terminals; a replica circuit which has the same DC characteristics as those of the amplifier circuit; a reference voltage generation circuit which is connected to a bias terminal of the replica circuit, and which generates a predetermined reference voltage at the bias terminal; and a feedback circuit which takes a difference between the reference voltage generated at the bias terminal of the replica circuit and the voltage generated at a bias terminal of the amplifier circuit, and which performs feedback control by providing negative feedback of the difference to the bias terminal of the amplifier circuit so that the voltage generated at the bias terminal of the amplifier circuit is made equal to the reference voltage generated at the bias terminal of the replica circuit.