Including Combined Diverse-type Semiconductor Device Patents (Class 330/299)
  • Patent number: 9854632
    Abstract: An optoelectronic circuit for receiving a variable voltage having alternating increasing and decreasing phases. The optoelectronic circuit includes an alternating arrangement of resistive elements and light-emitting diode sets mounted in series. Each set contains two terminals. Each resistive element is inserted between two consecutive sets. The optoelectronic circuit includes, for each set among a plurality of said sets, a depletion mode metal oxide semiconductor field effect transistor, the drain and the source of which are coupled with the terminals of said set and the gate of which is coupled with one of the terminals of the next set. An additional resistive element is, for at least some of the transistors, coupled between the drain or the source of the transistor and one of the terminals of the set.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: December 26, 2017
    Assignee: Aledia
    Inventors: Frédéric Mercier, Erwan Dornel, Xavier Hugon
  • Patent number: 9692365
    Abstract: A graphene microphone preamplifier is a minimalist design working in class A with large quiescent current in a push-pull configuration, with automatic balancing of voltage imbalance.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: June 27, 2017
    Inventor: Piotr Nawrocki
  • Publication number: 20140049326
    Abstract: A low noise amplifier (LNA) includes a bank of selectable first transistors and a bank of selectable second transistors complementary to the first transistors. The LNA also includes a plurality of switches to select one or more of the first transistors and to select one or more of the second transistors, the selected first transistors positioned in series with respect to the selected second transistors. The LNA also includes switching logic to control the plurality of switches, to simultaneously vary selection of the first transistors and the second transistors during calibration to substantially match output second-order distortion of the selected first transistors with that of the selected second transistors, to create high second-order intercept points.
    Type: Application
    Filed: August 14, 2012
    Publication date: February 20, 2014
    Applicant: Broadcom Corporation
    Inventor: Eric Bernard Rodal
  • Publication number: 20130336066
    Abstract: A sense amplifier (100) includes first and second inverters (112 and 113). The first inverter has an input terminal (116) and an OUT_B output node and a first transistor (124). The second inverter (113) has an input terminal (115) and an OUT output node and a second transistor (125). The OUT_B output node of the first inverter is coupled to an input terminal of the second inverter, and the OUT node of the second inverter is coupled to an input terminal of the first inverter. The sense amplifier does not use a reference current; therefore, the sense amplifier does not need a reference current generator. The sense amplifier needs only one enable signal to reset a latch (110) of the sense amplifier. When coupled to a non-volatile memory element, voltages at the output nodes are indicative of a logic level of a bit stored in the non-volatile memory element.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Walter Luis TERCARIOL, Andre Luis VILAS BOAS, Fernando Zampronho NETO
  • Publication number: 20130214868
    Abstract: A sense amplifier circuit includes a first transistor and a second transistor of a first type, a first transistor and a second transistor of a second type, a first resistive device, and a second resistive device. A first end of the first resistive device is coupled to a first data line. A second end of the first resistive device is coupled to a drain of the first transistor of the second type and a gate of the second transistor of the first type. A first end of the second resistive device is coupled to a second data line. A second end of the second resistive device is coupled to a drain of the second transistor of the second type and a gate of the first transistor of the first type.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 22, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hyun-Sung HONG
  • Publication number: 20120194276
    Abstract: A low noise amplifier includes a first Group III-nitride based transistor and a second Group III-nitride based transistor coupled to the first Group III-nitride based transistor. The first Group III-nitride based transistor is configured to provide a first stage of amplification to an input signal, and the second Group III-nitride based transistor is configured to provide a second stage of amplification to the input signal.
    Type: Application
    Filed: May 18, 2011
    Publication date: August 2, 2012
    Inventor: Jeremy Fisher
  • Publication number: 20120188021
    Abstract: A N-Channel HJ-FET cascode amplifier, with a High Frequency NPN Transistor differential error amplifier, having low 1/f noise, a DC to 12 GHz bandwidth, flat frequency response, excellent transient response, high linearity, and low input and output VSWR over a wide frequency range.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 26, 2012
    Inventor: Mark Scott Logue
  • Publication number: 20120154055
    Abstract: A power amplifier includes a first amplifier unit, a second amplifier unit, and an attenuator. The second amplifier receives a signal from the first amplifier unit and amplifies the signal. The attenuator is provided between the first and second amplifier units. The attenuator has arms, including at least one parallel arm and at least one series arm, and has switches connected to the arms to switch the electrical connection states of the arms with respect to the first and second amplifier units. The at least one parallel arm and the at least one series arm are alternately arranged, in the order named, as viewed in the direction from the first amplifier unit to the second amplifier unit.
    Type: Application
    Filed: August 1, 2011
    Publication date: June 21, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazuya Yamamoto, Miyo Miyashita, Takayuki Matsuzuka, Kenji Mukai
  • Publication number: 20110304395
    Abstract: Disclosed is a power amplifier. A power amplifier according to an aspect of the invention may include: a first amplification section having a first N metal oxide semiconductor (MOS) amplifier and a second N MOS amplifier connected in a cascode configuration and amplifying an input signal; a second amplification section having a first P MOS amplifier and a second P MOS amplifier connected in a cascode configuration and amplifying the input signal; and a power combining section combining respective output signals of the first amplification section and the second amplification section.
    Type: Application
    Filed: January 14, 2011
    Publication date: December 15, 2011
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Bon Hoon KOO, Ki Yong SON, Song Cheol HONG, Gyu Suck KIM, Yoo Sam NA
  • Patent number: 8045807
    Abstract: A pattern edge detecting method includes: detecting edge points in an image of an inspection pattern acquired from an imaging device; generating a plurality of edge lines from the edge points using a grouping process; generating a plurality of edge line group pairs, each composed of a combination of first and second edge line groups to be a candidate of any of one and the other of an outside edge and an inside edge of the inspection pattern, the generated edge lines being divided into two parts in different manners; performing shape matching between the first and second edge line groups for each edge line group pair; and specifying, as an edge of the inspection pattern, one of the first and second edge line groups constituting the edge line group pair whose matching score is best of matching scores of the edge line group pairs obtained during the shape matching.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadashi Mitsui
  • Publication number: 20110227653
    Abstract: An electronic circuit including: a first branch, placed between two terminals of application of a D.C. voltage, including a series connection of a first constant current source, of a first diode-connected N-channel MOS transistor, of a first diode-connected P-channel MOS transistor, and of a second constant current source; a second branch, parallel to the first branch, comprising a series connection of a second N-channel MOS transistor connected as a current mirror on the first N-channel MOS transistor and of a second P-channel MOS transistor connected as a current mirror on the first P-channel transistor; and an input terminal connected between the first N-channel and P-channel transistors and an output terminal connected between the second N-channel and P-channel transistors.
    Type: Application
    Filed: March 15, 2011
    Publication date: September 22, 2011
    Applicant: STMicroelectronics (Crolles2) SAS
    Inventor: Hubert Degoirat
  • Patent number: 7768354
    Abstract: A bias circuit operable to supply a bias current to a first transistor includes: a second transistor having a collector terminal connected to a first power supply; a first resistance element having one end connected to an emitter terminal of the second transistor and having the other end connected to a base terminal of the first transistor; a second resistance element having one end connected to the emitter terminal of the second transistor and having the other end connected to ground potential; at least one third resistance element provided between a base terminal of the second transistor and a second power supply; and a plurality of temperature compensation circuits connected to the base terminal of the second transistor which are operable to control a base potential of the second transistor so that the potential falls as a temperature rises.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: August 3, 2010
    Assignee: Panasonic Corporation
    Inventors: Shingo Matsuda, Hirokazu Makihara, Kazuki Tateoka, Masahiko Inamori
  • Patent number: 7609076
    Abstract: A method of quickly measuring a characteristic impedance of an ESD protecting circuit by applying a discharge voltage to the ESD protecting circuit, includes the steps of measuring a variation in discharge voltage applied to and a variation in discharge current caused to flow through the ESD protecting circuit with time; simultaneously detecting a state when both the discharge voltage and discharge current corresponding to each other are attenuated, after both the discharge voltage and discharge current sequentially rise to arrive individually to respective peak values based on an input to or an output from a computer; and taking a ratio of the variation of discharge voltage to the variation of discharge current during the attenuation as an impedance value when the ratio is nearly constant as well as an apparatus for realizing the same.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: October 27, 2009
    Assignee: Hanwa Electronic Ind. Co., Ltd.
    Inventors: Toshiyuki Nakaie, Masanori Sawada, Taizo Shintani, Natarajan Mahadeva Iyer, David Eric Tremouilles
  • Patent number: 7486138
    Abstract: An audio signal switch has a plurality of inputs and an output. Each input is arranged to be selectively connected to the output via a respective transmission chain, each transmission chain includes: a first bipolar transistor, of a first type, connected to the input; a second bipolar transistor, of a second type, complementary to said first configuration, connected to the output; and an intermediate bipolar transistor, of the second type, connected between said first and second transistors. The first and second transistors are arranged in an emitter-follower circuit configuration, and the intermediate transistor is arranged to act as a diode to protect the first transistor from a large reverse voltage applied to its base-emitter junction.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: February 3, 2009
    Assignee: STMicroelectronics Asia Pacific Pte Ltd.
    Inventors: Yann Desprez-Le Goarant, Kok-Yong Tan
  • Patent number: 7391829
    Abstract: In some embodiments, a frequency dependent gain circuit is coupled to an output of an amplifier. The gain circuit provides at least two ranges of frequency dependent gain characteristics in response to the output of the amplifier. A control circuit provides one of the at feast two gain values as an output. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: June 24, 2008
    Assignee: Intel Corporation
    Inventors: Alok Tripathi, Ken Drottar, Dave Dunning
  • Patent number: 7391269
    Abstract: The invention provides an amplifying circuit for reducing electric power consumption at a standby mode time. Therefore, in DMOS and NMOS transistors constituting a cascode amplifier, the gate of the DMOS transistor of an initial stage is biased to a grounding voltage through a resistor, and the source of the DMOS transistor is connected to the output side of an inverter through an inductor. When a control signal is set to a level “H”, the output of the inverter becomes a level “L”, and the DMOS transistor attains a turning-on state and a sufficient operating electric current is flowed to the cascode amplifier. Thus, an input signal is amplified and is outputted as an output signal. In contrast to this, when the control signal is set to the level “L”, the output of the inverter becomes the level “H”, and the DMOS transistor attains a turning-off state and the operating electric current of the cascode amplifier is stopped.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: June 24, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tadashi Chiba
  • Patent number: 7386075
    Abstract: An apparatus for and method of extending the dynamic range of a RF communications receiver. The invention provides a mechanism for controlling the gain of both the LNA and down conversion mixer in the front end portion of an RF receiver. Both the LNA and the mixer are adapted to have both low and high gain modes of operation. The control mechanism typically comprises a two bit gain control that places both the LNA and mixer in one of four operating gain mode states. The selection of the most appropriate operating gain mode state, is preferably determined in accordance with various metrics such as the received levels of the desired signal, levels of interference signals, bit error rate and receiver RSSI.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: June 10, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Alexander Mostov, Oren Eliezer
  • Patent number: 7016664
    Abstract: A mixer circuit arrangement 30 comprises a complementary transconductor circuit 31 and a mixer stage 32. The complementary transconductor circuit 31 includes two paths in parallel between a positive supply voltage VDD and ground G and is connected directly between the voltage supply terminals VDD and G. The first path includes a P-type MOS transistor TP1 and an N-type MOS transistor TN1 connected in series. Similarly, the second path includes a P-type MOS transistor TP2 and an N-type MOS transistor TN2 connected in series. The gate electrodes of the P-type transistors TP1 and TP2 are connected to a voltage bias Vbp via high value bias resistors Rb, and the gate electrodes of the N-type transistors TN1 and TN2 are connected to a second voltage bias Vbn via high value bias resistors Rb. The mixer stage 32 is connected between the output of the complementary transconductor circuit 31 and a load, the load also being connected to one of the supply terminals.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: March 21, 2006
    Assignee: Zarlink Semiconductor Limited
    Inventor: Viatcheslav Igorevich Souetinov
  • Patent number: 7012464
    Abstract: A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain amplifier. The first stage is a transconductance amplifier and the second stage is an operational amplifier. The first stage converts an input signal from a voltage into a current. The second stage converts the current signal to an output voltage signal.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: March 14, 2006
    Assignee: Broadcom Corporation
    Inventors: Frank W. Singor, Arya R. Behzad
  • Patent number: 6828854
    Abstract: A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain amplifier. The first stage is a transconductance amplifier and the second stage is an operational amplifier. The first stage converts an input signal from a voltage into a current. The second stage converts the current signal to an output voltage signal.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: December 7, 2004
    Assignee: Broadcom Corporation
    Inventors: Frank W. Singor, Arya R. Behzad
  • Publication number: 20040140855
    Abstract: A chemical formulation and the method of using said formulation for testing the ability of certain coolant treatment and additive formulations to actually perform certain aspects of the work for which they were intended. These certain aspects of work, for which the coolants ability to perform are tested, include the treated coolant's ability to remove scale from the treated system by inactivating, or otherwise rendering harmless, certain scale causing contaminants via chelation and sequestration. The invention further includes the method by which the testing is carried out.
    Type: Application
    Filed: August 11, 2003
    Publication date: July 22, 2004
    Applicant: TeknowSmartz Innovations/Technology Inc.
    Inventor: Buddy Don Gray
  • Patent number: 6737915
    Abstract: A hybrid preamplifier with a vacuum tube input stage driving a JFET output stage dubbed TIJO (for Tube Input JFET Output) that uses zero feedback circuitry and a common low voltage B+ power supply. A single output low voltage transformer provides all necessary voltages including the filament voltage. No attempt is made to minimize distortion or maximize bandwidth by adding feedback. The vacuum tube is mounted externally to allow easy tube swapping for varying the gain and tonal palette, with no dangerous high voltages present.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: May 18, 2004
    Inventor: Stephen Arthur Harner
  • Patent number: 6300669
    Abstract: A semiconductor integrated circuit device comprises a multiple-stage amplifier including a plurality of transistors. The multiple-stage amplifier has a first stage comprising a plurality of bipolar transistors each having a single emitter structure. The bipolar transistors are connected parallel to each other. The semiconductor integrated circuit device can easily be designed, is of a self-aligned structure, and has a single transistor size. The semiconductor integrated circuit device may be used as a low-noise, high-power-gain high-frequency amplifier.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: October 9, 2001
    Assignee: NEC Corporation
    Inventor: Yasushi Kinoshita
  • Patent number: 6043714
    Abstract: A power amplifier including an amplifier stage including a heterojunction bipolar transistor for signal amplification having a base electrode connected to an RF signal input terminal, and a grounded emitter electrode; and a bias circuit including a silicon bipolar transistor having a base electrode connected to a power supply terminal, and a terminal from which a current amplified in response to a base current is output, which terminal is connected to the base electrode of the heterojunction bipolar transistor stage. In this power amplifier, since the voltage required for operating the bias circuit is reduced, a power amplifier capable of operating at a low voltage is realized.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: March 28, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuya Yamamoto, Yukio Miyazaki
  • Patent number: 5977571
    Abstract: Each of a plurality of photodiodes forming a photodetector is mounted on a respective metal pad on the surface of a semiconductor integrated circuit chip including a corresponding number of amplifier circuits for detecting the photocurrent from respective photodiodes. Each circuit comprises a high gain, high input impedance amplifier and a feedback element, typically a resistor of high value, connected across the amplifier between input and output nodes thereof. Each photodiode mounting metal pad and each feedback resistor is connected to a common input node of a respective amplifier by metal paths within a connecting structure forming part of the integrated circuit. Adverse effects on the output current from the photodiodes are reduced by forming a junction of the path from each feedback resistor with the path from the corresponding photodiode at the metal pad on which the photodiode is mounted, and interconnecting such junction along a common path to the corresponding amplifier input node.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: November 2, 1999
    Assignee: Lucent Technologies, Inc.
    Inventor: Keith Wayne Goossen
  • Patent number: 5854718
    Abstract: A DC feed-back circuit for causing a DC voltage of an external transistor in which an output bias current of a record amplifier flows to be equal to a DC voltage of an output terminal is provided so as to decrease power consumption. Thus, a plurality of record amplifying circuits can be incorporated into one IC chip. In particular, in home-use Hi-Fi VCRs, a Hi-Fi record amplifying circuit and video record amplifying circuits can be incorporated into one chip.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: December 29, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshikazu Fujii
  • Patent number: 5701103
    Abstract: A DC feed-back circuit for causing a DC voltage of an external transistor in which an output bias current of a record amplifier flows to be equal to a DC voltage of an output terminal is provided so as to decrease power consumption. Thus, a plurality of record amplifying circuits can be incorporated into one IC chip. In particular, in home-use Hi-Fi VCRs, a Hi-Fi record amplifying circuit and video record amplifying circuits can be incorporated into one chip.
    Type: Grant
    Filed: July 10, 1996
    Date of Patent: December 23, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshikazu Fujii
  • Patent number: 5623230
    Abstract: A unity gain or buffer amplifier having a low offset voltage. The amplifier uses two emitter followers of different conductivity types (PNP and NPN) in an up-down emitter or voltage follower configuration to provide high input impedance and low output impedance. By using both PNP and NPN transistors in a current mirror, the base-emitter voltages of the input and output transistors are forced to be substantially the same, reducing the offset voltage. N- and P-channel MOSFETs can be substituted for the NPN and PNP transistors. Single ended and push-pull arrangements are shown.
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: April 22, 1997
    Assignee: Lucent Technologies Inc.
    Inventor: David C. Goldthorp
  • Patent number: 5574403
    Abstract: A simple high speed precision transconductance amplifier circuit having a low offset. The circuit uses as an input stage two substantially identical transistors of a first conductivity type connected in series so as to have the same current there through, neglecting base currents. A second stage uses two substantially identical transistors of a second conductivity type connected in series, with the output of the amplifier being a current mirrored from the second stage. The offset is maintained low by maintaining the V.sub.BE of the transistors in the two stages substantially identical by connecting together the base and collector of one of the transistors in one stage and coupling the resulting V.sub.BE of the transistor so coupled to one of the transistors of opposite conductivity type in the other stage. Various embodiments and variations are disclosed.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: November 12, 1996
    Assignee: Maxim Integrated Products
    Inventor: Madhav V. Kolluri
  • Patent number: 5498885
    Abstract: An integrated circuit is provided with particular application for high frequency modulation circuits, such as a mixer circuit, with reduced noise and gain. The circuit provides a novel application of a single device comprising a 4 or 5 terminal, gate controlled lateral bipolar junction transistor device, in the form of a merged MOS and lateral bipolar transistor. In a grounded base configuration, RF and LO signals are applied to the gate and emitter terminals respectively and provide for modulated output at the collector, and provides signal modulation with reduced noise compared with multi-device implementations of known mixer circuits using a summation circuit, diodes and FETs. Advantageously, operation of the device in the grounded base or grounded emitter configuration provides for strong modulation of the DC current gain, i.e. over 4 decades, as a function of gate voltage.
    Type: Grant
    Filed: September 26, 1994
    Date of Patent: March 12, 1996
    Assignee: Northern Telecom Limited
    Inventors: M. Jamal Deen, Duljit S. Malhi, Zhixin Yan, Robert A. Hadaway
  • Patent number: 5469093
    Abstract: A drive circuit comprises a plurality of current mirrors connected in series at their output-current end with a load resistor between two power rails. The input halves of the mirrors are driven by respective groups of series-connected input transistors, the lowest transistor in each group serving to set up the required currents in the mirrors in response to an input voltage on its base. Two potential dividers set up potentials on the control terminals of the groups of input transistors, on the one hand, and potentials on the main-terminal junctions of the mirror output transistors, on the other, such that at no time does any transistor in the circuit experience a voltage greater than its rated voltage.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: November 21, 1995
    Assignee: Plessey Semiconductors Limited
    Inventor: Iain R. MacDonald
  • Patent number: 5463350
    Abstract: A biasing voltage is supplied from the emitter of an emitter follower npn transistor. The base current of the npn transistor is supplied from the emitter of an emitter follower pnp transistor. Thus, a constant biasing voltage which is not influenced by an average value of an input signal, is supplied to an amplifier.
    Type: Grant
    Filed: December 15, 1994
    Date of Patent: October 31, 1995
    Assignee: NEC Corporation
    Inventor: Hirotaka Yamaji
  • Patent number: 5446414
    Abstract: A simple high speed precision transconductance amplifier circuit having a low offset. The circuit uses as an input stage two substantially identical transistors of a first conductivity type connected in series so as to have the same current there through, neglecting base currents. A second stage uses two substantially identical transistors of a second conductivity type connected in series, with the output of the amplifier being a current mirrored from the second stage. The offset is maintained low by maintaining the V.sub.BE of the transistors in the two stages substantially identical by connecting together the base and collector of one of the transistors in one stage and coupling the resulting V.sub.BE of the transistor so coupled to one of the transistors of opposite conductivity type in the other stage. Various embodiments and variations are disclosed.
    Type: Grant
    Filed: September 27, 1994
    Date of Patent: August 29, 1995
    Assignee: Maxim Integrated Products
    Inventor: Madhav V. Kolluri
  • Patent number: 5278516
    Abstract: A buffer circuit provided with a transistor each on the input and output terminal sides, in which the transistor has been provided in order to keep constant a difference between a collector-emitter voltage of the input terminal side transistor and that of the output terminal side transistor.
    Type: Grant
    Filed: March 31, 1993
    Date of Patent: January 11, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventor: Katsuhito Sakurai
  • Patent number: 5023570
    Abstract: An emitter-follower circuit includes a bipolar transistor of a first conductivity type operating as an emitter-follower transistor and a bipolar transistor of a second conductivity type operable as a clamping transistor. The voltage developed between the base and the emitter of the second conductivity type clamping transistor is adapted to clamp the voltage developed between the base and the collector of the first conductivity type transistor, so that such a high voltage as exceeding the breakdown voltage is not developed between the collector and the emitter of the first conductivity type transistor. The emitter-follower circuit is capable of operating with safety even when an input signal applied thereto has a wide range of direct current components.
    Type: Grant
    Filed: February 12, 1990
    Date of Patent: June 11, 1991
    Assignee: NEC Corporation
    Inventor: Kouichi Matsumoto
  • Patent number: 4939254
    Abstract: A method is provided for a high yield template synthesis of macrocyclic catecholamide ligands.
    Type: Grant
    Filed: October 30, 1989
    Date of Patent: July 3, 1990
    Assignee: The Regents of the University of California
    Inventors: Thomas J. McMurry, Kenneth N. Raymond
  • Patent number: 4628281
    Abstract: The base of a transistor constitutes the input of an amplifier arrangement, to which an input signal may be applied. The emitter of this transistor is coupled to the negative power-supply terminal by means of a first resistor. The collector of this transistor is coupled to the input terminal of a first current multiplier circuit, whose output terminal is connected to the output of the amplifier arrangement and to the emitter of the transistor by means of a second resistor. The first current multiplier circuit further has a sum terminal which is connected to the positive power-supply terminal. In order to reduce the distortion in the arrangement it further comprises a second current multiplier circuit whose input terminal is connected to the collector of the transistor and whose sum terminal is connected to the input terminal of the first current multiplier circuit. The output of the second current multiplier circuit is connected to the negative supply terminal of the transistor.
    Type: Grant
    Filed: November 14, 1985
    Date of Patent: December 9, 1986
    Assignee: U.S. Philips Corporation
    Inventor: Adrianus Sempel
  • Patent number: 4590005
    Abstract: The present invention relates to novel macrocyclic carbonyl compounds of the macrocyclic carbamate and lactone type, to chiral macrocyclic structures, to macrocyclic urea compounds and to macrocyclic thiolactones and to a process for the preparation of same. The process of the invention comprises reacting a stannoxane, silazane or silathiane compound with an activated carbonyl compound in an organic solvent at moderate temperature.
    Type: Grant
    Filed: April 26, 1985
    Date of Patent: May 20, 1986
    Inventors: Abraham Shanzer, Eduard Schwartz
  • Patent number: 4540950
    Abstract: A linear amplifier circuit includes input and output signal ports and a pair of signal amplifying circuits. Each signal amplifying circuit couples an input signal from the input signal port to the output signal port. A bias supply can be connected to the signal amplifying circuits for supplying bias currents thereto. The input and output signal ports are isolated from the bias supply without using capacitors or inductors.
    Type: Grant
    Filed: June 7, 1982
    Date of Patent: September 10, 1985
    Assignee: AT&T Bell Laboratories
    Inventor: David G. Ross
  • Patent number: 4420725
    Abstract: A low-noise wide-band bipolar transistor amplifier in which distortion caused by non-linear transistor operating characteristics is substantially eliminated. An input signal is coupled to the base of a first transistor connected in an emitter follower configuration with the signal formed at the emitter of the first transistor coupled to the base of a second transistor. Currents are supplied to the first and second transistors by a current mirror circuit in such a manner that a ratio of the current supplied to the first transistor to the current supplied to the second transistor is made constant. An output signal is produced in response to current variations in a transistor of the current mirror circuit which supplies current to the second transistor.
    Type: Grant
    Filed: September 22, 1980
    Date of Patent: December 13, 1983
    Assignee: Pioneer Electronic Corporation
    Inventors: Susumu Sueyoshi, Kikuo Ishikawa
  • Patent number: 4105943
    Abstract: The dynamic input impedance of a feedback current amplifier is varied such that a matching to the characteristic impedance of a line feeding the amplifier is achieved. An integrated negative feedback current amplifier has at least two amplifier stages and one inverse coupling branch from the amplifier input to the amplifier output. The active element of the last amplifier stage has a divided output circuit such that the output current is divided between the inverse coupling branch and the amplifier output. The input DC current is selected such that the dynamic amplifier input impedance is adjusted to the characteristic impedance of a line feeding the amplifier.
    Type: Grant
    Filed: August 10, 1977
    Date of Patent: August 8, 1978
    Assignee: Siemens Aktiengesellschaft
    Inventor: Gerhard Krause
  • Patent number: 4093925
    Abstract: A method and a system of obtaining a large power with the use of a junction field effect transistor by extending the working range to improve the utilization rate of the power source voltage. The range for the gate voltage is set up to some predetermined forward voltage at which the gate and the source will be subjected to a forward biasing. The source-to-drain internal resistance is reduced by this forward gate voltage, but no gate current is allowed to flow probably due to the existence of a non-linear element between the gate and the source.
    Type: Grant
    Filed: November 18, 1975
    Date of Patent: June 6, 1978
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Kenji Yokoyama
  • Patent number: 4058776
    Abstract: A bias circuit for a large pulse-width, broad-bandwidth radio-frequency avalanche device comprising a power supply coupled to the device through a bias line. The bias circuit includes a resistive network shunted across the bias line and ground to dampen spurious submicrowave oscillations.
    Type: Grant
    Filed: July 29, 1976
    Date of Patent: November 15, 1977
    Assignee: RCA Corporation
    Inventors: Elmer Lawrence Allen, Jr., Hirohisa Kawamoto
  • Patent number: 4057763
    Abstract: Current mirror amplifiers, which exhibit greater current attenuation (or gain) than prior art current mirror amplifiers taking up the same area on a monolithic integrated circuit die, are described in which the base-emitter junctions of the mirroring transistors are dissimilar in profile.
    Type: Grant
    Filed: May 17, 1976
    Date of Patent: November 8, 1977
    Assignee: RCA Corporation
    Inventor: Carl Franklin Wheatley, Jr.