Bipolar Or Unipolar (fet) Patents (Class 330/300)
  • Patent number: 10771018
    Abstract: Provided is a harmonic suppression method, a corresponding low-noise amplifier (20, 30, 40), and a communication terminal. In the harmonic suppression method, an isolation unit (23, 33, 43) is arranged between a harmonic suppression unit (24, 34, 44) of the low-noise amplifier (20, 30, 40) and an output match network (25, 35, 45)/input match network (21, 31, 41). The harmonic suppression unit (24, 34, 44) is isolated from the output match network (25, 35, 45)/input match network (21, 31, 41) by means of the isolation unit (23, 33, 43), so that the two are not affected or compromised by each other, and can be designed separately. In this way, the design flexibility of a signal amplification circuit is greatly improved, and the design difficulty is reduced.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 8, 2020
    Assignee: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.
    Inventor: Wenhua Wan
  • Patent number: 10498299
    Abstract: A baseband amplifier circuit comprising a single-ended to differential converter followed by at least one boosted follower amplifier. The boosted follower amplifier comprises a first transconductance device arranged to control a first current between a first supply node and a first output node in response to a voltage at a first input node, a second transconductance device arranged to control a second current between the first output node and a second supply node in response to a voltage at a second input node, a third transconductance device arranged to control a third current between the first supply node and a second output node in response to a voltage at a third input node, and a fourth transconductance device arranged to control a fourth current between the second output node of the boosted follower amplifier and the second supply node in response to a voltage at a fourth input node.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Charaf Eddine Souria, Cristian Pavao Moreira
  • Patent number: 10374552
    Abstract: A mixer device is disclosed, which is fabricated as a bipolar-complementary metal oxide semiconductor (BiCMOS) integrated circuit device, to provide improved linearity and dynamic range, at higher operating frequencies. A mixer device configured according to an embodiment includes a driver circuit comprising bipolar junction transistors (BJTs) to convert a local oscillator signal to a high slew-rate gate drive signal. The driver circuit is configured as a quasi-complementary driver employing NPN BJTs. The mixer device further includes a mixer circuit comprising CMOS field-effect transistors (FETs) configured to mix an input signal with the gate drive signal to generate an output signal through the application of the gate drive signal to the gate port of the CMOS FETs. The mixer device further includes a voltage biasing circuit to provide a biased body voltage to the FETs to allow overdriving to a negative voltage relative to the body voltage.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: August 6, 2019
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Douglas S. Jansen
  • Patent number: 10326420
    Abstract: We disclose a receiver circuit which may be used in mm-wave devices. The receiver circuit comprises a transimpedance amplifier comprising PMOS and NMOS transistors, wherein the back gate voltages provided to the transistors may be adjusted. By adjusting the back gate voltages during device operation, structural variations and temperature variations in the threshold voltages of the transistors may be minimized and the gain compression tolerance of the receiver circuit may be increased.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Mehmet Ipek, Frank Zhang
  • Patent number: 10256781
    Abstract: A complementary metal oxide silicon transceiver having an integrated power amplifier is provided. The complementary metal oxide silicon transceiver having the integrated power amplifier is capable of controlling an output power according to a communication environment to solve the following problem that with the increment of an output level of a power amplifier, performance is decreased when noises flow into other blocks of a transceiver with power and thus are inputted to the power amplifier.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 9, 2019
    Assignee: FCI INC.
    Inventors: Dong Hyun Ko, Min Chul Kang, Myung Woon Hwang
  • Patent number: 10128804
    Abstract: An equalizer, in at least some embodiments, comprises an amplifier configured to produce an amplified voltage signal that is a function of an ambient temperature affecting the equalizer. The equalizer also includes a linear equalizer stage coupled to the amplifier and comprising a transistor having a resistance controlled by the amplified voltage signal. The linear equalizer stage is configured to produce a voltage output signal having a gain that is dependent on the transistor resistance and on a frequency of the amplified voltage signal.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: November 13, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amit Rane, Dongwei Chen
  • Patent number: 10116269
    Abstract: The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a differential amplifier in cascode configuration. An input transistor is coupled to an output transistor via a peaking inductor. The output transistor is also directly coupled to a degeneration resistor. There are other embodiments as well.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: October 30, 2018
    Assignee: INPHI CORPORATION
    Inventors: Leonardo Vera, Carl Pobanz, James Hoffman
  • Patent number: 9881881
    Abstract: A multi-block semiconductor device includes a first block and a second block operating in different power regimes from each other. A seal ring is around a periphery of the die, hermetically sealing the first and second blocks. The die has a substrate and an insulating layer, the seal ring being on the insulating layer. The seal ring serves as a power bus for the first block but not the second block. The seal ring and first block are electrically coupled to a first ground node, the first ground node being electrically isolated at a die-level from other ground nodes in the multi-block semiconductor device. In some embodiments, the second block is located in a central area of the die, and a plurality of metal lines electrically connect the seal ring to the first block, the metal lines being evenly spaced around a majority of the periphery of the semiconductor die.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: January 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher N. Brindle, Anton Arriagada
  • Patent number: 9853680
    Abstract: Circuits and methods related to adjustable compensation for parasitic effects in radio-frequency switch networks. In some embodiments, an adjustable compensation circuit for a radio-frequency (RF) circuit can include an inductive circuit that couples a selected node of the RF circuit with a reference node. The inductive circuit can be configured to provide a plurality of inductance values. In some embodiments, the RF circuit can be, for example, a switch network having a plurality of switchable RF signal paths, the reference node can be a ground node, and the selected node can be a common node such as an antenna port.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: December 26, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Junhyung Lee
  • Patent number: 9768744
    Abstract: A power amplifier comprising a bipolar transistor connected in cascode with a field effect transistor (FET) such as a pseudomorphic high electron mobility transistor (PHEMT) device. The bipolar transistor has a common emitter and the FET a common gate. Advantageously, the bipolar transistor is a heterojunction bipolar transistor (HBT); and the HBT and the FET may be integrated on a single die. Illustrative materials for the HBT and FET are Gallium Nitride, Indium Phosphide, or Gallium Arsenide/Indium Gallium Phosphide.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: September 19, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Thomas William Arell
  • Patent number: 9698734
    Abstract: Power amplification system with adjustable common base bias. A power amplification system can include a first transistor having a base coupled to a radio-frequency input. The power amplification can further include a second transistor having an emitter coupled to a collector of the first transistor and having a collector coupled to a radio-frequency output. The power amplification system can include a biasing component configured to apply a fixed biasing signal to the base of the first transistor and to apply an adjustable biasing signal to the base of the second transistor.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: July 4, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Philip John Lehtola, Scott W Coffin
  • Patent number: 9634718
    Abstract: Architectures and methods related to insertion loss reduction and improved isolation in switch designs. In some embodiments, a switching architecture can include a switch network having one or more switchable radio-frequency (RF) signal paths, where each path contributes to a parasitic effect associated with the switch network. The switching architecture can further include a parasitic compensation circuit coupled to a node of the switch network. The parasitic compensation circuit can be configured to compensate for the parasitic effect of the switch network.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: April 25, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Junhyung Lee
  • Patent number: 9439259
    Abstract: A current drive circuit capable of reducing the influence of temperature variation or individual deviation is provided. An output transistor is a PNP bipolar transistor, and has an emitter connected to a cathode of an LED string. A current control resistor is disposed between a collector of the output transistor and a ground terminal. An output terminal of an error amplifier is connected to a base of the output transistor, a first input terminal of the error amplifier is connected to a connection point of the output transistor and the current control resistor, and a reference voltage is applied to a second input terminal of the error amplifier. The error amplifier enables a sink current sunk from the output terminal to flow to the current control resistor.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: September 6, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Junichi Hagino, Shingo Haruta
  • Patent number: 9385625
    Abstract: A RF-to-DC converter charges a battery or powers a circuit from the energy of received radio waves. The RF energy received is very small for far-field applications, so the converter is highly sensitive. Four capacitor arrays are arranged in two banks. Buffered RF signals pump bottom plates of the capacitors. A series of L-switches in each bank connect between the two capacitor arrays in that bank. Each L switch has a pre-charge switch that charges that stage's input capacitor, and a stage-transfer switch that shares charge from the input capacitor to an output capacitor for that stage. Switches in the two banks alternately pre-charge and pump, with the left bank pumping while the right bank pre-charges. Switches are transistors with substrates tied to their sources or actively driven by substrate control signals. One bank may use n-channel transistors with the other bank uses p-channel transistors. Gate voltages may be boosted.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: July 5, 2016
    Assignee: Hong Kong Applied Science and Technology Research Institute Company, Limited
    Inventors: Kwok Kuen (David) Kwong, Yat Tung Lai, Ka Hung Kwok
  • Patent number: 9231537
    Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to an intermediate signal. The first circuit may be implemented using a first transistor type. The second circuit may be configured to generate the intermediate signal in response to (i) an input signal and (ii) a feedback of the output signal. The second circuit may be implemented using a second transistor type. The output signal is an amplified version of the input signal while maintaining linearity.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: January 5, 2016
    Assignee: M/A-COM Technology Solutions Holdings, Inc.
    Inventor: Brian J. McNamara
  • Patent number: 9130524
    Abstract: Disclosed is a linear amplifier which includes: a common source transistor with the gate connected with an input node; a first common gate transistor connected with the common source transistor in a cascode type, with the drain connected with an output node; and a second common gate transistor connected in parallel with the first common gate transistor, with the gate connected with the input node and the drain connected with the output node.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: September 8, 2015
    Assignee: SOONGSIL UNIVERSITY RESEARCH CONSORTIUM TECHNO-PARK
    Inventors: Jong Hoon Park, Chang Hyun Lee, Chang Kun Park
  • Patent number: 8928414
    Abstract: The object of the present invention is a low noise figure amplifier with a variable gain which comprises a cascode amplification stage comprising, serially mounted, a low-voltage MOSFET transistor installed as a common source followed by a bipolar transistor with high breakdown voltage installed as a common base. A resistor is placed between the bipolar transistor's collector and the grid of the cascode stage's MOSFET transistor, and the cascode stage is electrically powered through a choke.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: January 6, 2015
    Assignee: Alcatel Lucent
    Inventors: Pascal Roux, Yves Baeyens, Muriel Gohn
  • Patent number: 8797100
    Abstract: Circuit unit (CU) comprising a heterojunction bipolar transistor and a long-gate pseudomorphic high-electron-mobility transistor. Either a source (S) or a drain (D) of the long-gate pseudomorphic high-electron-mobility transistor is electrically coupled with either a collector (C) or an emitter (E) of the heterojunction bipolar transistor.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: August 5, 2014
    Assignee: Epcos AG
    Inventors: Bart Balm, Jeroen Bouwman, Léon C. M. van den Oever
  • Publication number: 20140184340
    Abstract: This invention generally relates to the technical field of integrated circuits. More specifically the invention relates to output stages for providing an output signal, into which an integrated circuit may be used. An aspect relates to an integrated circuit capable of driving an external class-B output stage in a manner that allows providing a continuous output signal over the full range of desired outputs. The integrated circuit may comprise a class-AB output stage working in conjunction with the class-B output stage so as to provide a hybrid output stage. The integrated circuit may prevent dead band problems commonly faced when employing a class-B output stage. The integrated circuit may also reduce the quiescent current of the hybrid output stage. This may have further advantages, such as for example, the output stage producing less heat/power than needs to be dissipated.
    Type: Application
    Filed: October 18, 2013
    Publication date: July 3, 2014
    Inventors: Martijn F. Snoeij, Mikhail V. Ivanov
  • Publication number: 20140159820
    Abstract: A sense amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first resistive device, and a second resistive device. The first resistive device is coupled to a first data line and to a drain of the third transistor. The second resistive device is coupled to a second data line and to a drain of the fourth transistor. A terminal of the fifth transistor is coupled to the gate of the first transistor. A terminal of the sixth transistor is coupled to the gate of the second transistor.
    Type: Application
    Filed: February 11, 2014
    Publication date: June 12, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hyun-Sung HONG
  • Patent number: 8704147
    Abstract: A photoelectric conversion device has a first photoelectric converter which converts light into a current, a second photoelectric converter which converts light into a current, a first bipolar transistor which amplifies the current input to a base thereof from the first photoelectric converter, and outputs the amplified current from each of a plurality of emitters thereof, a second bipolar transistor which amplifies the current input to a base thereof from the second photoelectric converter, and outputs the amplified current from each of a plurality of emitters thereof, and a current adder which adds the current from one emitter of the plurality of emitters of the first bipolar transistor, and the current from one emitter of the plurality of emitters of the second bipolar transistor, thereby obtaining a sum current.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: April 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yukihiro Kuroda
  • Patent number: 8665020
    Abstract: A differential amplifier circuit including: a differential input stage including a pair of differential MOS transistors, a pair of load elements, and a first constant-current source; an output stage including an output MOS transistor and a second constant-current source; a constant-current MOS transistor provided in parallel to one of the first and second constant-current sources; and a boost current controlling MOS transistor in which a potential of a connection node of the output MOS transistor and the second constant-current source is applied to a gate terminal thereof; wherein the boost current controlling MOS transistor is turned on when a voltage inputted to a gate terminal of one of the pair of differential MOS transistors changes, and a current of the constant-current MOS transistor is added to one of the first and second constant-current sources and is allowed to flow.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: March 4, 2014
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Kohei Sakurai, Akihiro Terada, Yoichi Takano
  • Patent number: 8610484
    Abstract: An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: December 17, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Sudarshan Udayashankar, Jerry L. Doorenbos
  • Patent number: 8588433
    Abstract: There is disclosed a microphone, a circuit, and a method. A microphone capsule may include an electret microphone and a field effect transistor (FET). A floating DC voltage source may have a first end connected to a drain terminal of the electret microphone capsule and a second end. A load resistor may be connected between the second end of the floating DC voltage source and a source terminal of the electret microphone capsule. A voltage follower may have an output connected to the source terminal of the electret microphone capsule and the first end of the floating DC voltage source. A coupling capacitor may couple an audio signal from the source terminal of the electret microphone capsule to an input of the voltage follower.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: November 19, 2013
    Assignee: Baltic Latvian Universal Electronics, LLC
    Inventors: Martins Saulespurens, Felikss Stanevics
  • Patent number: 8570101
    Abstract: Power reduction in transmitters is very important. One method to realize reduction is to make use of switching power amplifiers (PA) that have a better efficiency. Switching PA concepts are only possible in combination with suitable modulation methods like pulse width modulation (PWM) and out-phasing concepts. However, PWM and out-phasing concepts rely on accurate phase control and duty cycle of the signals. Digitally generation of signals of variable duty cycles and phase is proposed without sacrificing their accuracy. Accordingly, a out-phasing power amplifier arrangement is disclosed, where the generation of the out-phasing angle (?) and duty cycles (d1 and d2) are controlled by a set of n-bit digital input words (D1, D2, D3, D4). The baseband phase information (?(t)) is phase modulated back to radio frequency and used as the clock signal of digital circuitry for phase and duty cycle generation after being frequency multiplied by 2n-1.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: October 29, 2013
    Assignee: NXP B.V.
    Inventors: Melina Apostolidou, Mark Pieter Van Der Heijden, Mustafa Acar
  • Publication number: 20130120070
    Abstract: Embodiments of dual stage active pixel devices are described herein. Other examples, implementations, and related methods are also disclosed herein.
    Type: Application
    Filed: January 4, 2013
    Publication date: May 16, 2013
    Applicant: Arizona Board of Regents, a body Corporate of the State of A-Z, Acting for and on behalf of ASU
    Inventor: Arizona Board of Regents, a body Corporate of the State of AZ, Acting for and on behalf of ASU
  • Patent number: 8395451
    Abstract: A N-Channel HJ-FET cascode amplifier, with a High Frequency NPN Transistor differential error amplifier, having low 1/f noise, a DC to 12 GHz bandwidth, flat frequency response, excellent transient response, high linearity, and low input and output VSWR over a wide frequency range.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: March 12, 2013
    Inventor: Mark Scott Logue
  • Patent number: 8311785
    Abstract: Methods and apparatus to minimize saturation in a ground fault detection device are disclosed. An example method includes connecting a capacitor simulator to a node of the ground fault detector device to prevent saturation, and monitoring power-line conductors for ground fault conditions with the ground fault detector device. An example apparatus to simulate a saturation capacitance in a ground fault device includes a sense coil induced by power-line conductors, and at least one of an amplifier or a current detector including an input connected to the sense coil and an output connected to a ground fault detector. The example apparatus also includes a saturation capacitor simulator connected to a node of at least one of the amplifier or the current detector to prevent saturation.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: November 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Artur J. Lewinski, Ross Teggatz, Thomas Edward Cosby
  • Patent number: 8289302
    Abstract: An output buffer circuit with enhanced slew rate is disclosed. A first and a second slew-rate enhancing transistor are configured to enhance the slew rate of the source transistor and the sink transistor of an output stage. A first control circuit and a second control circuit turn off the first and the second slew-rate enhancing transistors during the static state, and turn on the first and the second slew-rate enhancing transistors during the transition.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: October 16, 2012
    Assignees: Himax Technologies Limited, National Taiwan University
    Inventors: Yi-Jan Emry Chen, Pang-Jung Liu, Jyun-Ping Jiang, Tsung-Yu Wu
  • Patent number: 8111105
    Abstract: An amplifier circuit comprising: a MOSFET amplifier circuit; a BJT amplifier circuit; a MOSFET switch circuit arranged for switching between the MOSFET amplifier circuit and the BJT amplifier circuit to implement different gain modes of the amplifier circuit.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: February 7, 2012
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventor: Jun Zhou
  • Patent number: 8014719
    Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: September 6, 2011
    Assignee: Broadcom Corporation
    Inventors: Shervin Moloudi, Maryam Rofougaran
  • Patent number: 7986189
    Abstract: A circuit includes a first resistive element coupled to a diode, a second resistive element, a first transistor having a first current electrode coupled the second resistive element, a second transistor having a first current electrode coupled to the first resistive element and a second current electrode coupled to the control electrode of the first transistor, a third resistive element coupled to a node, a third transistor having a first current electrode coupled to the node and having a control electrode and a second current electrode each coupled to the control electrode of the second transistor, a fourth transistor having a first current electrode coupled to the second resistive element and a control electrode coupled to the control electrode of the second transistor, and a fifth transistor having a first current electrode coupled to the node and a control electrode coupled to the second current electrode of the fourth transistor.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: July 26, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Thierry Sicard
  • Patent number: 7969429
    Abstract: The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: June 28, 2011
    Assignee: Panasonic Corporation
    Inventors: Masahiko Sasada, Hiroki Matsunaga, Masashi Inao, Hiroshi Ando, Jinsaku Kaneda, Eisaku Maeda, Akihiro Maejima
  • Patent number: 7928804
    Abstract: A power amplifier includes: a semiconductor substrate; a preceding-stage amplifying device on the semiconductor substrate, amplifying an input signal; a following-stage amplifying device on the semiconductor substrate, amplifying an output signal of the preceding-stage amplifying device; and an inter-stage matching circuit connecting the preceding-stage amplifying device to the following-stage amplifying device. The preceding-stage amplifying device has a first field effect transistor; the following-stage amplifying device has a heterojunction bipolar transistor; and the inter-stage matching circuit has a capacitance galvanically separating the output terminal of the preceding-stage amplifying device from the input terminal of the following-stage amplifying device.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: April 19, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuya Yamamoto, Satoshi Suzuki, Takao Haruna, Takao Moriwaki
  • Patent number: 7911276
    Abstract: A low noise, highly linear transconductor circuit, which may be applied, e.g., in communication systems, includes a first input node for receiving a first input signal of the transconductor circuit and a second input node for receiving a second input signal of the transconductor circuit, and at least a first amplifier, a second amplifier, and a first, second and third resistor. Each of the first and second amplifiers includes an input stage with a combination of at least a transistor of the MOS type and a transistor of the bipolar type, and an output stage for providing a respective output signal of the transconductor circuit and having at least a transistor of the bipolar type. The circuit achieves reduced noise due to output current reuse in the input stage of the amplifiers and cross coupling of bias resistors to result in a highly linear transconductor circuit having very low noise.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: March 22, 2011
    Assignee: STMicroelectronics Design and Application GmbH
    Inventor: Sebastian Zeller
  • Patent number: 7911280
    Abstract: An amplifier stage for generating an amplified output signal from an input signal, a mobile device comprising an audio amplifier, and an amplification method for generating an amplified output signal from an input signal using an amplifier stage are described.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: March 22, 2011
    Assignee: Sony Ericsson Mobile Communications AB
    Inventor: Hans Peter Koerner
  • Patent number: 7876154
    Abstract: A variable gain amplifier (VGA) with a linear-in-dB gain characteristic is provided. The VGA includes: a control signal converter which converts an input gain control signal VC, which is input so that the VGA obtains a linear-in-dB gain characteristic to the maximum gain, into an output gain control signal Vx=VTln((1/m)exp(?VC/VT)?1) (m is a constant, VT=kT/q); and a variable gain amplifier which receives and converts the output gain control signal VX output from the control signal converter so that the gain has a linear-in-dB characteristic. A shape of a gain curve is externally controlled.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: January 25, 2011
    Assignee: FCI Inc.
    Inventor: Sung Ho Beck
  • Patent number: 7860454
    Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: December 28, 2010
    Assignee: Broadcom Corporation
    Inventors: Shervin Moloudi, Maryam Rofougaran
  • Patent number: 7830210
    Abstract: Provided is an amplifier device including a J-FET, a bipolar transistor, a first resistor and a second resistor. The amplifier device has a configuration in which a gate of the J-FET is connected to one end of an ECM and one end of the first resistor, a drain of the J-FET is connected to an input terminal of the bipolar transistor, a high-potential side of the bipolar transistor is connected to one end of a load resistor, the other end of the first resistor is grounded, a source of the J-FET and a low-potential side of the bipolar transistor are connected to one end of the second resistor, the other end of the second resistor is grounded, and an output voltage is drawn from the high-potential side of the bipolar transistor.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: November 9, 2010
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventor: Eio Onodera
  • Patent number: 7626460
    Abstract: A differential amplifier topology includes circuitry to create a higher bandwidth output using less current than an existing Capacitive Trans-Impedance Amplifier (CTIA) using an all Field Effect Transistor (FET) circuit design. A bipolar npn emitter follower in the circuit topology provides low output impedance and some degree of output inductive peaking, and the CTIA differential output is buffered by the bipolar npn emitter follower in the CTIA feedback loop such as the open-loop high voltage gain is maintained without being affected by output loads.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: December 1, 2009
    Assignee: Raytheon Company
    Inventors: Kanon Liu, James F. Asbrock
  • Patent number: 7592869
    Abstract: An electronic amplifier circuit that provides improved gain control linearity characteristics resulting from having a controllable field effect transistor (FET) acting as a degeneration resistance (degeneration resistance FET) and a controllable load resistance FET. The overall gain function of the amplifier exhibits improved linearity in part due to the presence of the load FET, which tends to cancel the nonlinear behavior emanating from the degeneration FET. The circuit also includes a control circuit for generating non-linear control signals that are responsive to process characteristics of the FETs, such that the degeneration resistance FET and load resistance FETs may be controlled more consistently and independently from process variations.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: September 22, 2009
    Assignee: Finisar Corporation
    Inventors: Hyeon Min Bae, Naresh Ramnath Shanbhag, Jonathan B. Ashbrook
  • Patent number: 7555263
    Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: June 30, 2009
    Assignee: Broadcom Corporation
    Inventors: Ahmadreza Rofougaran, Maryam Rofougaran, Brima Ibrahim, Jacob Rael, Shahla Khorram, Shervin Moloudi, Stephen Wu, Hooman Darabi, William T. Colleran, Ed Chien, Meng-An Pan
  • Publication number: 20090108942
    Abstract: A differential amplifier topology includes circuitry to create a higher bandwidth output using less current than an existing Capacitive Trans-Impedance Amplifier (CTIA) using an all Field Effect Transistor (FET) circuit design. A bipolar npn emitter follower in the circuit topology provides low output impedance and some degree of output inductive peaking, and the CTIA differential output is buffered by the bipolar npn emitter follower in the CTIA feedback loop such as the open-loop high voltage gain is maintained without being affected by output loads.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Inventors: Kanon Liu, James F. Asbrock
  • Patent number: 7486138
    Abstract: An audio signal switch has a plurality of inputs and an output. Each input is arranged to be selectively connected to the output via a respective transmission chain, each transmission chain includes: a first bipolar transistor, of a first type, connected to the input; a second bipolar transistor, of a second type, complementary to said first configuration, connected to the output; and an intermediate bipolar transistor, of the second type, connected between said first and second transistors. The first and second transistors are arranged in an emitter-follower circuit configuration, and the intermediate transistor is arranged to act as a diode to protect the first transistor from a large reverse voltage applied to its base-emitter junction.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: February 3, 2009
    Assignee: STMicroelectronics Asia Pacific Pte Ltd.
    Inventors: Yann Desprez-Le Goarant, Kok-Yong Tan
  • Publication number: 20080204141
    Abstract: A device for measuring voltage levels includes a root mean square (RMS) detector. The RMS detector includes a linear multiplier, a log converter, a low-pass filter and a temperature compensator. The linear multiplier multiplies a voltage of an input signal by the voltage of the input signal. The low-pass filter couples to an output of the linear multiplier. The log converter generates a logarithmic signal having a voltage that is logarithmically related to a voltage of an output of the low-pass filter. The temperature compensator adjusts the logarithmic signal based on a temperature of the RMS detector. The RMS detector is capable of determine an RMS voltage level of the input signal.
    Type: Application
    Filed: April 15, 2008
    Publication date: August 28, 2008
    Applicant: Microtune (Texas), L.P.
    Inventors: Kim E. Beumer, Peter Kipfelsberger, Philip T. Hisayasu
  • Patent number: 7415245
    Abstract: An ultrawideband radio frequency pulse is generated by shaping a carrier signal having a selected frequency with a window function. The shaped carrier is gated to produce the ultrawideband pulse. In further embodiments, the window function comprises a sinusoidal function, and the ultrawideband pulse is formed via a mixer and a CMOS radio frequency switch.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Keith R Tinsley, Jeffery R Foerster, Minnie Ho, Evan R Green, Luiz M. Franca-Neto, Siva G. Narendra
  • Publication number: 20080191805
    Abstract: The invention relates to an electronic circuit comprising a first terminal (100) and a second terminal (200, 300) and at least three transistors (1) arranged in parallel, each transistor having a control terminal (2) connected to said first terminal (100) for receiving a control signal, and an output terminal (3, 4) connected to said second terminal (200, 300) for providing an output signal, said output signal depending on the control signal. The transistors (1) are arranged symmetrically with regard to a point of symmetry, in a manner such that the contribution to the heating of a transistor by heat received from the other transistors, is substantially the same for all of said transistors. The invention also relates to a method for manufacturing an electronic circuit.
    Type: Application
    Filed: May 9, 2005
    Publication date: August 14, 2008
    Applicant: Seiko Epson Corporation
    Inventor: Kazuaki Tanaka
  • Patent number: 7411451
    Abstract: An amplifier circuit includes an pair of input transistors, the drains of which are connected to emitters of first and second cascode transistors. First and second controlled current sources are connected to the emitters of the first and second cascode transistors, respectively, and third and fourth controlled current sources are connected to the collectors thereof. A bias circuit controls the 4 controlled current sources in response to the emitter voltage of a pair of input transistors of an output stage the inputs of which are connected to the drains of the first and second cascode transistors.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: August 12, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Sergey V. Alenin, Henry Surtihadi
  • Patent number: 7358968
    Abstract: The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: April 15, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiko Sasada, Hiroki Matsunaga, Masashi Inao, Hiroshi Ando, Jinsaku Kaneda, Eisaku Maeda, Akihiro Maejima
  • Patent number: 7348855
    Abstract: An integrated circuit includes a composite transistor including at least a first transistor of a first technology type having a first group of intrinsic properties and a second transistor of a second technology type having a second group of the intrinsic properties, at least one of the intrinsic properties of the second group being substantially different than a corresponding intrinsic property of the first group, the second transistor having a first electrode coupled to a supply voltage, a second electrode coupled to a first electrode of the first transistor, and a control electrode coupled to a bias voltage conductor and also coupled to a control electrode and a second electrode of the first transistor. A source of bias current is coupled to the bias voltage conductor and is also coupled to the second electrode of the second transistor. A bias voltage across the composite transistor is produced on the bias voltage conductor to bias a cascode transistor of the first technology type.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: March 25, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Dolly Y. Wu