Abstract: Some implementations provide a passive equalizer section configured to filter an input signal, the passive equalizer section including: a first passive filter that comprises: a first resistor characterized by a first resistance, and a first reactive component characterized by a first reactance, wherein the first resistor and the first reactive component are in series and connected at a first connection node; and a second passive filter that comprises: a second resistor characterized by a second resistance, and a second reactive component characterized by a second reactance, wherein the second resistor and the second reactive component are in series and connected at a second connection node; and a signal mixing section comprising a plurality of transistors to mix signals with different frequency response characteristics.

Abstract: A pre-driver for driving an LVDS (Low Voltage Differential Signaling) driving circuit is provided. The pre-driver includes a first inverter, a high-pass filter, and a second inverter. The first inverter has an input terminal coupled to an input node of the pre-driver, and an output terminal coupled to a first node. The high-pass filter is coupled between the first node and a second node. The second inverter has an input terminal coupled to the second node, and an output terminal coupled to an output node of the pre-driver. The high-pass filter is configured to improve a high-frequency response of the pre-driver.

Abstract: The present disclosure discloses an adjustable electric control equalization circuit used for cable television networks. The disclosed adjustable electric control equalization circuit includes one or more electric control equalization modules with adjustable slopes, a control module, and one or more compensation modules. The control module and the one or more electric control equalization modules are electrically connected to control slope change of the one or more electric control equalization modules. The control module and the one or more compensation modules are electrically connected to generate compensation signals based on the slope change of the one or more electric control equalization modules. An output of the one or more electric control equalization modules is electrically connected to an input of the one or more compensation modules to output a combined signal of a sum of signals outputted from the electric control equalization module and the compensation module.

Abstract: A photodetector integrated circuit (IC) having an electromagnetic interference (EMI) sensor integrated therein is provided for sensing EMI at the photodetector. Integrating the EMI sensor into the photodetector IC ensures that the EMI sensor is in proximity to the photodetector so that any EMI that is sensed is actually EMI to which the photodetector is exposed. The sensed EMI may then be used for a number of reasons, such as to determine the root cause of damage to circuitry of the system, to determine the point in time at which an EMI event occurred, or to trigger a warning when a determination is made that an EMI limit has been reached.

Abstract: An ultra-wideband low-noise amplifier circuit with low power consumption includes a cascode amplifier circuit module and an output combining circuit module. The cascode amplifier circuit module receives an input signal, and outputs a first output signal and a second output signal. The output combining circuit module receives the first output signal and the second output signal, and applies respective phase shifts to the first output signal and the second output signal for reducing a phase difference between the first output signal and the second output signal, so as to obtain a combined output signal.

Abstract: According to an embodiment, a variable gain amplifier includes a differential transistor pair including a first and second transistor. A variable resistor for setting a gain is connected between electrodes the transistor pair. A first variable capacitor is connected to an electrode of the first transistor, and a second variable capacitor is connected to an electrode of the second transistor. Corresponding to the gain setting set by adjusting the variable resistor, capacitance values of the variable capacitors can be adjusted to provide improved frequency characteristics of the variable gain amplifier.

Abstract: A power amplifier system including a composite digital predistorter (DPD) ensuring optimized linearity for the power amplifier is described. In this system, a digital-to-analog converter (DAC), an analog filter, a first mixer, and the power amplifier are serially coupled to the composite DPD. A second mixer, a receive gain block, and an analog-to-digital converter (ADC) are serially coupled to the output of the power amplifier. A DPD training component is coupled between the inputs of the composite DPD and the ADC. The composite DPD includes a memory-based DPD, e.g., a memory polynomial (MP) DPD, a memoryless-linearizing DPD, e.g., a look-up table (LUT) DPD, and two multiplexers.

Abstract: One embodiment relates an equalizer which includes a first amplifier stage and a second amplifier stage. The first amplifier stage is configured to apply a first gain at a characteristic frequency while attenuating frequencies in a low frequency range. The second amplifier stage is configured to apply a second gain at the frequencies in the low frequency range. The first amplifier stage may be configured before the second amplifier stage, or vice versa. Another embodiment relates to a method of linear equalization. Another embodiment relates to an amplifier which may be used for linear equalization. Other embodiments, aspects, and features are also disclosed.

Abstract: A receiver equalization circuit includes a first output transistor having a gate coupled to an input signal. The receiver equalization circuit may also include a second output transistor having a drain coupled to a drain of the first output transistor. The receiver equalization circuit may also include a resistor coupled between a gate and a drain of the second output transistor to provide a direct current (DC) bias to the gate of the second output transistor. The receiver equalization circuit may further include a feed-through capacitor coupled between the gate of the second output transistor and an input signal source. The feed-through capacitor feeds the input signal to the gate of the second output transistor when a frequency of the input signal is above a predetermined threshold. The feed-through capacitor and the resistor define a signal gain amplification point.

Abstract: Disclosed is a predistortion linearizer for power amplifiers using a bridge topology, which has the advantages that an equalizer stage is disposed in each of the linear and nonlinear branches. This equalizer stage is used to adjust the frequency response of the complex expansion of the bridge. The equalizers introduce variable transmission functions in the linear and nonlinear bridge branches, so that the linearizer compensates for the individual nonlinear frequency response of a power amplifier, which varies within a manufacturing lot.

Abstract: An offset calibration method is provided. Two input terminals of an equalizer are switched to a common voltage at a first time point, wherein the equalizer generates a first equalized signal and a second equalized signal according to the common voltage. It is determined whether a first offset voltage is present in the equalizer according to the first and second equalized signals generated from the common voltage. If the first offset voltage is determined to be present in the equalizer, a first compensation voltage is provided to the equalizer.

Abstract: An equalization circuit adjusts (e.g., equalizes) an input signal according to the value of one or more adjustment signals (e.g., equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.

Abstract: There is provided a programmable high-frequency high-gain equalizer for digital display interfaces comprising, two pairs of current sources; two pairs of transistors arranged as two differential pairs, each transistor connected to a different one of the current sources; and a pair of a negative impedance resistors connected to the two pairs of two differential pairs; and a pair of capacitive and programmable resistive degeneration connected to the two pairs of two differential pairs to optimize the equalizer gain.

Abstract: Methods and apparatus to provide an equalizer for analog adaptive control are disclosed. An example equalizer described herein includes a high frequency amplifier to receive an input signal and to amplify a high frequency portion of the input signal, a low frequency amplifier to receive the input signal and to amplify a low frequency portion of the input signal, and a weight factor controller to control a gain of the high frequency amplifier and a gain of the low frequency amplifier.

Abstract: An optical receiver includes a light receiving element for converting an optical signal to an electrical signal having a first bandwidth and an amplifier for amplifying the electrical signal. The amplifier has a first gain response that yields a second bandwidth that is less than the first bandwidth. The optical receiver also includes an equalizing circuit operationally coupled to the amplifier. The equalizing circuit has a second gain response that compensates for the first gain response of the amplifier so that a substantially constant net gain is imparted by the amplifier and the equalizing circuit to the electrical signal over the first bandwidth.

Abstract: An equalization system (18) that reduces inter-symbol interference in an input signal (220) includes a variable gain amplifier (430), and one or more peaking amplifiers (432) that are connected in series to the variable gain amplifier (430). The variable gain amplifier (430) receives the input signal (220) and scales the input signal (220) while each peaking amplifier (432) can be selectively controlled to selectively adjust a peaking gain (326) and a peaking corner frequency (328). Additionally, the equalization system (18) can include a PTAT bias generator (434) that provides a PTAT bias current to one or more of the peaking amplifiers (432) to maintain a transconductance of one or more of the peaking amplifiers (432) substantially constant as temperature changes. With this design, the equalization system (18) provides programmable and stabilized equalization gain, has a tunable peaking corner frequency, and superior common mode rejection.

Abstract: An equalization system (18) that reduces inter-symbol interference in an input signal (220) includes a variable gain amplifier (430), and one or more peaking amplifiers (432) that are connected in series to the variable gain amplifier (430). The variable gain amplifier (430) receives the input signal (220) and scales the input signal (220) while each peaking amplifier (432) can be selectively controlled to selectively adjust a peaking gain (326) and a peaking corner frequency (328). Additionally, the equalization system (18) can include a PTAT bias generator (434) that provides a PTAT bias current to one or more of the peaking amplifiers (432) to maintain a transconductance of one or more of the peaking amplifiers (432) substantially constant as temperature changes. With this design, the equalization system (18) provides programmable and stabilized equalization gain, has a tunable peaking corner frequency, and superior common mode rejection.

Abstract: An integrated circuit includes a differential amplifier. The differential amplifier includes at least one output end. A circuit is coupled with the at least one output end of the differential amplifier. The circuit does not include a resistor-capacitor (RC) network and is configured for providing a negative impedance to the differential amplifier for adjusting a direct current (DC) gain of the integrated circuit.

Abstract: Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading. A novel approach is presented by which adjustable amplification and equalizer may be achieved using a C3MOS wideband data stage. This may be referred to as a C3MOS wideband data amplifier/equalizer circuit. This employs a wideband differential transistor pair that is fed using two separate transistor current sources. A switchable RC network is communicatively coupled between the sources of the individual transistors of the wideband differential transistor pair. There are a variety of means by which the switchable RC network may be implemented, including using a plurality of components (e.g., capacitors and resistors connected in parallel).

Abstract: Techniques for sequencing switched single capacitor for automatic equalization of batteries connected in series are described herein. In one embodiment, a battery equalizer includes a single capacitor, at least two switching circuits to be coupled to each of at least two batteries coupled in series. The battery equalizer further includes at least two driver circuits corresponding the at least two switching circuits and a controller. The controller is programmed to control the driver circuits in order to drive the switching circuits to sequentially couple the single capacitor to one of the batteries coupled in series during charging and/or discharging of the batteries. Only one of the switching circuits is turned on at a given time such that only one of the batteries is coupled to the single capacitor at the given time. Other methods and apparatuses are also described.

Abstract: The present invention is directed to systems and methods for providing an AGC circuit for maintaining a constant output power level from an amplifier. More specifically, the AGC circuit includes a circuitry for determining whether an input signal is a QAM or a CW signal. A QAM/CW gain switch is then controlled depending upon the input signal. Depending upon the mode of the QAM/CW gain switch, the AGC circuit either attenuates the power level of the signal or bypasses the signal. The bypassed or attenuated signal is then compared to a reference signal so that the AGC circuit produces an adjusting voltage accordingly. The amplifier finally receives the adjusting voltage and attenuates the output power level of the signal.

Abstract: A signal waveform equalizer circuit capable of equalizing the waveform of an input signal with a center voltage of 0 V and yet small in circuit scale. An input signal (in FIG. 1, positive-phase input signal) whose waveform is to be equalized is input to the source of an nMOS, and this enables the equalizer circuit to handle an input signal with the center voltage 0 V without the need to add an extra circuit. The waveform of the input signal is shaped by a delay circuit including a resistor and a capacitor, and an output signal (in FIG. 1, positive-phase output signal) is output from a node.

Abstract: Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading. A novel approach is presented by which adjustable amplification and equalizer may be achieved using a C3MOS wideband data stage. This may be referred to as a C3MOS wideband data amplifier/equalizer circuit. This employs a wideband differential transistor pair that is fed using two separate transistor current sources. A switchable RC network is communicatively coupled between the sources of the individual transistors of the wideband differential transistor pair. There are a variety of means by which the switchable RC network may be implemented, including using a plurality of components (e.g., capacitors and resistors connected in parallel).

Abstract: An optical receiver includes a light receiving element for converting an optical signal to an electrical signal having a first bandwidth and an amplifier for amplifying the electrical signal. The amplifier has a first gain response that yields a second bandwidth that is less than the first bandwidth. The optical receiver also includes an equalizing circuit operationally coupled to the amplifier. The equalizing circuit has a second gain response that compensates for the first gain response of the amplifier so that a substantially constant net gain is imparted by the amplifier and the equalizing circuit to the electrical signal over the first bandwidth.

Abstract: Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading. A novel approach is presented by which adjustable amplification and equalizer may be achieved using a C3MOS wideband data stage. This may be referred to as a C3MOS wideband data amplifier/equalizer circuit. This employs a wideband differential transistor pair that is fed using two separate transistor current sources. A switchable RC network is communicatively coupled between the sources of the individual transistors of the wideband differential transistor pair. There are a variety of means by which the switchable RC network may be implemented, including using a plurality of components (e.g., capacitors and resistors connected in parallel).

Abstract: A signal waveform equalizer circuit capable of equalizing the waveform of an input signal with a center voltage of 0 V and yet small in circuit scale. An input signal (in FIG. 1, positive-phase input signal) whose waveform is to be equalized is input to the source of an NMOS, and this enables the equalizer circuit to handle an input signal with the center voltage 0 V without the need to add an extra circuit. The waveform of the input signal is shaped by a delay circuit including a resistor and a capacitor, and an output signal (in FIG. 1, positive-phase output signal) is output from a node.

Abstract: A thermal pad controlled equalizer that adjusts the slope and gain of an amplifier in response to changes in ambient temperature, effectively simulating automatic gain control. The equalizer has a slope pad and a gain pad. The slope pad increases the attenuation of the signal in response to increases in ambient temperature. The gain pad decreases the attenuation when ambient temperature increases. Thus, the slope and gain pads together compensate for temperature effects on the system.

Abstract: In some embodiments an apparatus includes an amplifier, a first inverter having an input coupled to an output of the amplifier, and a second inverter having an input coupled to an output of the first inverter and an output, where the output of the second inverter is fed back to an input of the amplifier. Other embodiments are described and claimed.

Abstract: A radio frequency (RF) generator for applying RF power to a plasma chamber includes a DC power supply (B+). A radio frequency switch generates the RF power at a center frequency f0. A low-pass dissipative terminated network connects between the DC power supply (B+) and the switch and includes operates at a first cutoff frequency. The switch outputs a signal to an output network which improves the fidelity of the system. The output network generates an output signal fed to a high-pass subharmonic load isolation filter that passes RF power above a predetermined frequency. A low-pass harmonic load isolation filter may be inserted between the output network and the high-pass subharmonic load isolation filter, and a high-pass terminated network may connect to the output of the output network. The high-pass terminated network dissipates RF power above a predetermined frequency.

Abstract: An analog signal gain controller and equalizer with an increased signal bandwidth for reducing intersymbol interference (ISI) within a digital data signal.

Abstract: A forward signal equalizer for a forward amplifier for two-way coaxial cable systems, of the type having a distribution center distributing forward signals, and having reception facilities for receiving return signals from said cable system, the system having forward amplifiers for receiving forward signals, and having return amplifiers, and the forward signal equalizers are settable to provide varying amplifier specifications, and having receptacles for receiving plug-in equalizer components for varying the specifications of the forward amplifier, the equalizer components having a range of varying performance characteristics so that a component can be selected and plugged in to the forward signal equalizer to produce the performance specifications desired at a predetermined location in the cable system.

Abstract: A method and an apparatus for analyzing performance of a multi-stage radio frequency amplifier are described. The method simplifies the multi-stage radio frequency amplifier into equivalent input parts, output parts and mid-stage parts. The mid-stage parts are temporarily unset. Therefore, the equivalent input parts and output parts will be adjusted to make best gain performance and the mid-stage parts will be the next targets for analysis. Repeating the above-mentioned methods for decomposing the circuit can systemize the method for analyzing circuits and problems in each part of the circuit may be found more quickly.

Abstract: The invention relates to a composite amplifier (500) based on a main amplifier (510) and an auxiliary amplifier (520), and compensation for non-linear amplifier behavior by means of respective non-linear models (570, 575) of parasitic. In order to provide proper excitation of the non-linear models, a filter network (560) based on a linear model of the output network of the composite amplifier is provided. The linear filter network (550) basically determines ideal output node voltages, which are used as input to the respective non-linear models for generating appropriate compensation signals. The compensation signals are finally merged into the input signals of the respective sub-amplifiers (510, 520), thus effectively compensating for the effects of the non-linear parasitics.

Abstract: An equalizer circuit for equalizing first and second differential input signals comprises a differential pair, a reactive load, and first and second input followers. The differential pair defines first and second input nodes and first and second output nodes, and the reactive load is coupled to the differential pair. The first input follower circuit is connected to the first input node of the differential pair and is operable to receive the first differential input signal and to receive a first feedback signal from the differential pair and in response to generate a first input signal at the first input node of the differential pair. The second input follower circuit is connected to the second input node of the differential pair and is operable to receive the second differential input signal and to receive a second feedback signal from the differential pair and in response to generate a second input signal at the second input node of the differential pair.

Abstract: A network amplifier is provided. The network amplifier includes a variable equalizer having at least one control input and a variable attenuator having at least one control input. The network amplifier also includes at least one amplifier circuit that is coupled in series with the variable equalizer and the variable attenuator in a signal path of the network amplifier. The network amplifier also includes an automatic gain control circuit with a processor that monitors signals in the signal path and generates control signals for the control input of the variable equalizer and the control input of the variable attenuator to control at least one characteristic of the network amplifier.

Abstract: A predistortion system compensates or equalizes the phase and/or amplitude response over frequency of at least a portion of a signal path prior to the distortion generating circuitry, such as an amplifier, and/or of at least a portion of a feedback path after the distortion generating circuitry. For example, in a power amplification system using predistortion, an equalizer on the signal path adjusts the phase and amplitude of a predistorted signal across frequency to compensate for the amplitude and phase response of circuitry on the signal path, such as the amplitude and phase response of analog filters in the up-conversion process. After amplification, an equalizer on a feedback path adjusts the phase and amplitude across frequency of the signal representing the output of the amplifier to compensate for the amplitude and phase response of circuitry, such as analog filters in the down-conversion process, on the feedback path.

Abstract: A current amplifier has a variable resistor or capacitor to provide a high frequency boost. Additionally, additional transistors may be switched in and out of the circuit to provide different gains at lower frequency. The combination of variable resistors or capacitors and the switchable transistors provides control over the low frequency gain of the amplifier and the transition region from low gain to higher gain.

Abstract: A feed signal equalizer for a feed amplifier for two-way coaxial cable systems, of the type having a distribution centre distributing feed signals, and having reception facilities for receiving return signals from said cable system, the system having feed amplifiers for receiving feed signals, and having return amplifiers, and the feed signal equalizers are settable to provide varying amplifier specifications, and having receptacles for receiving plug-in equalizer components for varying the specifications of the feed amplifier, the equalizer components having a range of varying performance characteristics so that a component can be selected and plugged in to the feed signal equalizer to produce the performance specifications desired at a predetermined location in the cable system.

Abstract: A current amplifier has a variable resistor or capacitor to provide a high frequency boost. Additionally, additional transistors may be switched in and out of the circuit to provide different gains at lower frequency. The combination of variable resistors or capacitors and the switchable transistors provides control over the low frequency gain of the amplifier and the transition region from low gain to higher gain.

Abstract: A receiving circuit having a termination impedance and an equalization capacitor. The receiving circuit is connectable to a signal source having a source impedance through a DC (direct current) blocking capacitor. The value of the equalization capacitor is chosen such that voltage spikes otherwise caused by the blocking capacitor are eliminated. The receiving circuit is especially useful in distributed electronic amplifiers and electro-optic modulators.

Abstract: A D-class power amplifier of two channels in which an increase in power voltage due to a regenerative current is prevented and a high efficiency in utilization of electric power is attained. Two D-class power amplifying circuits included in the D-class power amplifier of the two channels are constructed by opposite phases. A preprocess is performed only to low frequency components of input signals so that they have a substantially equal amplitude in the two channels, and the resultant low frequency components are supplied to the D-class power amplifying circuits, respectively. The other ends of loads connected to the D-class power amplifying circuits are connected to a neutral potential point of the power voltage.

Abstract: A digitally controllable nonlinear pre-equalizer system receiving an input signal and generating an output signal, the system including a splitter for dividing the input signal into a first signal path and a second signal path, an attenuator and a time delay element in the first signal path, the attenuator and the time delay element operable to generate a linear signal, a mixer and a vector modulator in the second signal path, the mixer being responsive to a signal from a digital to analog converter coupled to a processor chip providing a digital signal to the digital to analog converter, the mixer and vector modulator operable to generate a nonlinear signal, and a summer for summing the linear signal and the nonlinear signal to generate the output signal.

Abstract: An equalizer circuit for equalizing first and second differential input signals comprises a differential pair, a reactive load, and first and second input followers. The differential pair defines first and second input nodes and first and second output nodes, and the reactive load is coupled to the differential pair. The first input follower circuit is connected to the first input node of the differential pair and is operable to receive the first differential input signal and to receive a first feedback signal from the differential pair and in response to generate a first input signal at the first input node of the differential pair. The second input follower circuit is connected to the second input node of the differential pair and is operable to receive the second differential input signal and to receive a second feedback signal from the differential pair and in response to generate a second input signal at the second input node of the differential pair.

Abstract: In a state where a PLL circuit is not locked, a gain control signal according to the difference between a peak value of a reproduced signal and the upper or lower limit value of the dynamic range of an A/D converter is given to a variable gain amplifier. In a state where the PLL circuit is locked, a gain control signal according to the difference between the reproduced signal and a reference value that corresponds to a level to which the reproduced signal belongs is given to the variable gain amplifier for each sampling point of the A/D converter. The variable gain amplifier amplifies the reproduced signal with a gain according to the gain control signal.

Abstract: The present invention provides a slope equalizer for use in a voice frequency channel card, which is preferably electronically and remotely controllable, and retrocompatible with existing telecommunication systems. The slope equalizer of the invention includes a high-pass filter followed by a variable gain stage amplifier, where the variable gain stage amplifier is an operational amplifier with a plurality of parallel input signal paths, each of the signal paths being a series-connected resistor and switch. The switch is preferably a FET transistor that is electronically and, optionally, remotely controllable. The circuit topology allows the use of FET transistors having relatively high on-resistances. A further advantage of the topology is that the FET switches are connected to a virtual ground by way of an operational amplifier, thereby reducing on-resistance modulation caused by signal variations across the FET.

Abstract: A circuit and method for equalization of a communication signal received over a communication system transmission line using switched filter characteristics. Equalization for frequency-independent and frequency-dependent attenuation of the communication signal is accomplished with a linear equalization channel which includes an input biasing circuit which provides a common input signal to two parallel amplifier paths. One path includes a wideband, fixed-gain, frequency-independent amplifier stage. The other path is a wideband multiplier amplifier stage in series with a wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic. The outputs of the fixed-gain wideband frequency-independent amplifier stage and wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic are both tied in common to the input of a wideband gain buffer amplifier stage, which has a switchable high-frequency boost frequency response characteristic.

Abstract: A serial digital data communications receiver with an improved automatic cable equalizer that is less susceptible to jitter and has greater multi-standards capability, and an improved automatic gain control system with a DC restorer that provides optimal edge jitter performance while avoiding the possibility of a latch-up condition at the start of data transmission. The automatic cable equalizer for equalizing signals received over cables of different lengths has multiple stages each having a transfer function of 1+Ki[fi(j&ohgr;)] wherein each of the Ki vary in accordance with a sequential gain control methodology. The AGC system uses the difference between band-pass filtered versions of the amplitudes of the input and output of a DC restorer based on quantized feedback, to regulate the AGC circuit.

Abstract: A low power analog equalizer is disclosed that provides up to twenty decibels (20 dB) of alternating current gain in a single stage of analog signal equalization. The analog equalizer comprises an operational amplifier coupled to two half circuits. Each half circuit comprises an impedance network capable of receiving an analog input voltage and generating a current signal that is inversely proportional to frequency, a variable resistor capable of adjusting the gain of the operational amplifier, and a transistor and an amplifier coupled in a cascode configuration to create a low impedance node at the output of the impedance network. The analog equalizer is fabricated with 0.18 micron CMOS technology and operates at 1.8 volts.

Abstract: A network line equalizer includes a transconductance-controlled, tunable single zero high-pass, filter that includes a single zero impedance circuit, and first and second MOS transistors that output differential currents based on differential input signals and the impedance of the single zero impedance circuit. The MOS transistors act as source followers to convert the differential input voltage signals to respective differential current signals. The single zero impedance circuit connects the first and second MOS transistors, and causes the first and second MOS transistors to output a corrected pair of differential signals based on the impedance. The impedance of the single zero IMPEDANCE circuit is implemented using CMOS transistors, enabling the impedance to be dynamically controlled by an external impedance controller.

Abstract: There is disclosed an adaptive equalizer filter with a current splitting system for variable gain control. The system comprises a current splitting circuit that splits an input current into a first current portion that is proportional to a first scale factor that has a value between zero and one. The remainder of the current is a second current portion that is proportional to a second scale factor that has a value that is equal to one minus the first scale factor. The current splitting circuit comprises a differential current mirror circuit that rejects common mode input current signals.