Plural A.f.s. For A Single Oscillator Patents (Class 331/10)
  • Patent number: 9654113
    Abstract: A control device for a clock generation circuit that generates a clock signal based on a reference signal from an outside, the control device includes: a storage device that stores frequency correction information for the clock signal according to a temperature condition of the clock generation circuit; and a processor that controls a frequency of the clock signal generated by the clock generation circuit under a second temperature condition, based on first and second frequency correction information according to a first temperature condition at first and second time points in the storage device.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: May 16, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Masumi Kobayashi, Shigeaki Kawamata, Kenji Kazehaya, Yuichiro Katagiri
  • Patent number: 9526137
    Abstract: Apparatuses and methods concerning regulation of load currents are disclosed. As an example, one apparatus includes a first clock generation circuit configured to generate a first clock signal with a frequency spectrum having a first frequency range. A second clock generation circuit is configured to produce a second clock signal by spreading the frequency spectrum of the first clock signal to have a second frequency range that is wider than the first frequency range. The second clock signal has a frequency spectrum extending outside of the frequency range. The apparatus includes a third circuit configured to regulate a voltage at a supply node as a function of the second clock signal. A current regulation circuit is configured to regulate current in a circuit path, from the supply node and passing through a load circuit coupled to the current regulator, as a function of the first clock signal.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: December 20, 2016
    Assignee: NXP B.V.
    Inventors: Ge Wang, Ling Su
  • Patent number: 9496881
    Abstract: In a method for mitigating the vibration-induced phase noise of an phase locked loop with an acceleration sensitive voltage controlled oscillator, a correction signal generated by applying a gain and a equalization to an acceleration signal provided by an acceleration sensor sensing the acceleration on the VCO, is added to the oscillator control signal for active compensation, an adaptive compensation unit dynamically adjusts the gain, the frequency response of equalization, and the sensing direction of the acceleration sensor while the phase locked loop is working to make the active compensation automatically adapt to the parameters of the voltage controlled oscillator.
    Type: Grant
    Filed: September 22, 2013
    Date of Patent: November 15, 2016
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Zhongyuan Zhao, Weixu Wang, Luping Pan
  • Patent number: 9490969
    Abstract: A transmission apparatus transmits a data signal to a reception apparatus with use of a first clock generated on the basis of a clock signal given to the transmission apparatus. The transmission apparatus changes an operation band of a PLL section to an operation band including a frequency of the clock signal which frequency has been measured with use of a second clock independent of the first clock. The transmission apparatus provides the reception apparatus with band information indicative of the operation band to which the operation band of the PLL section has been changed.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: November 8, 2016
    Assignee: FUJIKURA LTD.
    Inventor: Yoshinori Arai
  • Patent number: 9485085
    Abstract: In one embodiment, a phase locked loop (PLL) comprises a voltage-controlled oscillator (VCO), a frequency divider configured to frequency divide an output signal of the VCO to produce a feedback signal, and a phase detection circuit configured to detect a phase difference between a reference signal and the feedback signal, and to generate an output signal based on the detected phase difference. The PLL also comprises a proportional circuit configured to generate a control voltage based on the output signal of the phase detection circuit, wherein the control voltage tunes a first capacitance of the VCO to provide phase correction. The PLL further comprises an integration circuit configured to convert the control voltage into a digital signal, to integrate the digital signal, and to tune a second capacitance of the VCO based on the integrated digital signal to provide frequency tracking.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: November 1, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Kenneth Luis Arcudia, Jeffrey Andrew Shafer, Bupesh Pandita
  • Patent number: 9436209
    Abstract: A method for phase recovery in a system that includes a clock recovery unit and an estimation unit. The clock recovery unit of the system has a first phase detector unit. The estimation unit has a second phase detector unit and it is configured to estimate a gain of the second phase detector unit. The estimation unit and the clock recovery unit are configured to operate in parallel.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: September 6, 2016
    Assignee: Xieon Networks S.a.r.l.
    Inventors: Bernhard Spinnler, Christina Hebebrand, Stefano Calabro
  • Patent number: 9417091
    Abstract: A system and method for determining errors and calibrating to correct errors associated with field sensors, including bias, scale, and orthogonality, includes receiving and providing to a processor angular rate data and a first field vector relative to a first reference directional field and a second field vector relative to a second reference field from at least one field sensor. The processor is configured to relate the first field vector and the second field vector to the angular rate data to determine an error of the at least one field sensor. The processor is also configured to identify a compensation for the error of the at lease one field sensor needed to correct the first field vector and the second field vector and repeat the preceding to identify changes in the error over time and compensate for the changes in the error over time.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: August 16, 2016
    Assignee: The Johns Hopkins University
    Inventors: Giancarlo Troni-Peralta, Louis L. Whitcomb
  • Patent number: 9374069
    Abstract: A method of processing an amplitude-modulated analog signal at a carrier frequency Fc comprises: digitizing the analog signal to produce an input bit stream that represents the amplitude of the analog signal; generating an in-phase reference bit stream that is synchronous to the carrier frequency Fc and represents an in-phase digital reference signal substantially in the form of a sine and/or cosine wave; and multiplying the input bit stream with the in-phase reference bit stream to produce an output bit stream representing the amplitude modulation of the analog signal.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: June 21, 2016
    Assignee: Atlantic Inertial Systems Limited
    Inventor: Kevin Townsend
  • Patent number: 9322410
    Abstract: An electric pump device of an aspect of the invention includes a state determination unit and a gain adjusting unit. The state determination unit determines whether or not the electric pump device is in a stable state where a required oil pressure is supplied to a hydraulic operating device by maintaining a rotation state of a motor. The gain adjusting unit adjusts a gain for a current feedback control so as to reduce responsiveness of the current feedback control when the state determination unit determines that the electric pump device is in the stable state.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: April 26, 2016
    Assignee: JTEKT CORPORATION
    Inventor: Kengo Uda
  • Patent number: 9281989
    Abstract: A compensation apparatus compensates a quadrature-demodulated signal output from a quadrature demodulator 5 that performs quadrature demodulation by using a signal of a carrier frequency fc, by removing an image component caused by the quadrature demodulator 5 from the quadrature-demodulated signal. The compensation apparatus includes a signal generator 10 that generates a reference signal having a predetermined bandwidth in a reception band, and provides the reference signal to an input side of the quadrature demodulator 5. The reference signal includes a frequency band that is biased to either a higher-frequency side or a lower-frequency side with respect to the carrier frequency.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: March 8, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masahiko Onishi, Isao Katsura
  • Patent number: 9223330
    Abstract: An internal voltage generation circuit includes a comparison unit suitable for comparing a voltage level of a feedback voltage with that of a reference voltage, and generating a comparison signal and an acceleration voltage, a pull-up driving unit suitable for driving an internal voltage terminal to be pulled up in response to the comparison signal, a discharging unit suitable for discharging the internal voltage terminal in response to the acceleration voltage, and a voltage division unit suitable for dividing a voltage level of the internal voltage terminal, and generating the feedback voltage.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: December 29, 2015
    Assignee: SK Hynix Inc.
    Inventor: Hyun Chul Lee
  • Patent number: 9117099
    Abstract: The present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 25, 2015
    Assignee: Avatekh, Inc.
    Inventor: Alexei V. Nikitin
  • Patent number: 9041474
    Abstract: A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: May 26, 2015
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Saeed Abbasi, Nima Gilanpour, Michael R. Foxcroft, George A. W. Guthrie, Raymond S. P. Tam
  • Patent number: 9007135
    Abstract: A slew rate enhancing system includes a first input configured to receive a first complementary signal of a differential pair and a second input configured to receive a second complementary signal of the differential pair. The slew rate enhancing system further includes a first switch configured to selectively connect the first input to an output in response to a voltage of the second input being greater than a first predetermined voltage. The slew rate enhancing system further includes a second switch configured to selectively connect the first input to the output in response to the voltage of the second input being less than a second predetermined voltage.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: April 14, 2015
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 8957735
    Abstract: According to one embodiment, a phase locked loop (PLL) circuit includes an application unit, a correlator, an integrator and a power supply noise canceller. The application unit applies the test signal to a power supply voltage. The correlator extracts a frequency error signal as a monitor signal and calculates a correlation value for the test signal and the monitor signal to generate a correlation signal. The integrator integrates the correlation signal to generate an integral signal. The power supply noise canceller provides a cancellation gain corresponding to the integral signal to the power supply voltage to which the test signal is applied, to generate a control signal.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihide Sai
  • Patent number: 8952759
    Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 10, 2015
    Assignee: MediaTek Inc.
    Inventors: Ping-Ying Wang, Kuan-Hua Chao, Jeng-Horng Tsai
  • Patent number: 8928416
    Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: January 6, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Haibing Zhao
  • Patent number: 8884705
    Abstract: A frequency synthesis device with a feedback loop includes: a phase-comparison control circuit; a frequency conversion unit voltage controlled by the control circuit; a feedback loop for supplying at least one signal issuing from the frequency conversion unit to the control circuit; at least one other control circuit for voltage control of the frequency conversion unit; and at least one other feedback loop for supplying at least one other signal issuing from the frequency conversion unit to the other control circuit.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: November 11, 2014
    Assignee: Commissariat à{grave over ( )}l' énergie atomique et aux énergies alternatives
    Inventor: Emeric De Foucauld
  • Patent number: 8878614
    Abstract: A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: November 4, 2014
    Assignee: MegaChips Corporation
    Inventors: Wenjing Yin, Anand Gopalan
  • Patent number: 8816780
    Abstract: An exemplary calibration apparatus for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes a capturing block arranged to capture phase error samples, and a calibrating block arranged to adjust timing of said edge rotator according to said phase error samples. An exemplary calibration method for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes the following steps: capturing phase error samples, and adjusting timing of said edge rotator according to said phase error samples.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: August 26, 2014
    Assignee: Mediatek Inc.
    Inventors: Chi-Hsueh Wang, Robert Bogdan Staszewski
  • Patent number: 8710938
    Abstract: An electronic device may include a voltage controlled oscillator (VCO) and a temperature sensor. The electronic device may also include a controller configured to cooperate with the VCO and the temperature sensor to determine both a temperature and a frequency error of the VCO for each of a plurality of most recent samples. Each of the most recent samples may have a given age associated therewith. The controller may also be configured to align the temperature, the frequency error, and the given age for each of most recent samples in a three-dimensional (3D) coordinate system having respective temperature, frequency error and age axes. The controller may also be configured to estimate a predicted frequency error of the VCO based upon the aligned temperature, frequency error, and given age of the most recent samples.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: April 29, 2014
    Assignee: BlackBerry Limited
    Inventors: Grant Henry Robert Bartnik, Ryan Jeffrey Hickey
  • Patent number: 8698566
    Abstract: An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Ming-Chieh Huang, Tao Wen Chung, Chih-Chang Lin, Fu-Lung Hsueh, Yuwen Swei
  • Patent number: 8564340
    Abstract: A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, a charge pump, a frequency tuning circuit and an N divider. The frequency tuning circuit includes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the output frequency of the dual PLL circuit to the target frequency; and a current control oscillator (CCO), for generating an output signal of the dual PLL circuit. The output frequency of the output signal is equal to the target frequency.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: October 22, 2013
    Assignee: MStar Semiconductor, Inc.
    Inventors: Yong-Wang Liu, Wen-cai Lu, Sterling Smith
  • Patent number: 8531245
    Abstract: A method and apparatus for compensating for temperature variation in a phase locked loop (PLL) includes receiving an error signal by a controller in which the error signal representative of an instantaneous frequency difference between a reference frequency signal and an output frequency signal of a voltage controlled oscillator of the PLL, and determining when a voltage of the error signal is outside of a predetermined voltage range. When the voltage is outside the predetermined voltage range, the method includes generating a new digital compensation signal based upon a previous digital compensation signal, and converting the new digital compensation signal to be an analog compensation signal. The method further includes filtering the analog compensation signal by a filter to produce a filtered analog compensation signal, and adjusting the output frequency of the voltage controlled oscillator in accordance with the filtered analog compensation signal.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: September 10, 2013
    Assignee: ST-Ericsson SA
    Inventors: Cyril Joubert, Sebastien Rieubon
  • Patent number: 8513995
    Abstract: System and method providing multiple circuit paths to control characteristics of periodic signals. In one embodiment first and second detector signals are indicative of a phase and frequency differences between the output signal and a reference signal. A first input signal based on the first detector signal adjusts the phase difference. A first control signal based on the second detector signal has frequency content in high and low frequency ranges. A second input signal based on the control signal reduces the frequency difference. A second control signal based on the second detector signal has relatively low frequency content in the high frequency range. A third input signal based on the second control signal reduces the frequency difference.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Robert Wang, Antonios Pialis, Rajeevan Mahadevan, Navid Yaghini, Rafal Karakiewicz, Raymond Kwok Kei Tang, Sida Shen, Mark Andruchow, Zhuobin Li, Nicola Pantaleo
  • Patent number: 8508270
    Abstract: Circuits and methods for controlling a VCO output signal. A filtered version of an integral path input signal controls current flow through a proportional path. An exemplary embodiment generates an integral path input signal from a digital to analog converter. First integral path circuitry includes a first transistor device and a low pass filter which provides a filtered version of the integral path input signal to a first transistor device to control conduction through the device, providing a first VCO input signal for frequency adjustment of the output signal. Proportional path switching circuitry between a supply terminal and VCO input terminal includes a second transistor device which receives the first VCO input signals to control conduction between the supply terminal and the first VCO input terminal to provide a second signal for adjustment of the phase of the VCO output signal relative to the reference signal.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: August 13, 2013
    Assignee: Intel Corporation
    Inventors: Navid Yaghini, Robert Wang, Antonios Pialis, Rajeevan Mahadevan, Rafal Karakiewicz, Raymond Kwok Kei Tang, Sida Shen
  • Patent number: 8508308
    Abstract: Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: August 13, 2013
    Assignee: LSI Corporation
    Inventors: Yikui Jen Dong, Freeman Y. Zhong, Tai Jing, Chaitanya Palusa
  • Patent number: 8436686
    Abstract: Apparatus for efficient time slicing including a phase lock loop circuit having a voltage controlled oscillator, an auto-frequency calibration circuit coupled with the phase lock loop circuit configured to output a value to select a range of the voltage controlled oscillator, and a burst mode detector connected with the auto-frequency calibration circuit. The burst mode detector having a register adapted to store the output of the auto-frequency calibration circuit.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: May 7, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng Wei Kuo, Ying-Ta Lu, Chewn-Pu Jou
  • Patent number: 8416025
    Abstract: A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: April 9, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chia-Liang Lin, Chao-Cheng Lee
  • Patent number: 8378751
    Abstract: A frequency synthesizer with multiple tuning loops, e.g., a fine tuning loop and a coarse tuning loop, is described. The fine tuning loop may operate over a limited tuning range and may have fine frequency resolution. The coarse tuning loop may operate over a wide tuning range and may have coarse frequency resolution. The fine tuning loop may receive a reference signal at a reference frequency and generate a fine tuning signal at a first frequency adjustable in fine steps. The coarse tuning loop may receive the reference signal, generate an output signal at an output frequency, and generate a coarse tuning signal at a second frequency based on the output signal and the fine tuning signal. The second frequency may be adjustable in coarse steps, e.g., in integer multiples of the reference frequency. The output frequency may be determined based on the first frequency and the second frequency.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: February 19, 2013
    Assignee: QUALCOMM Incorporated
    Inventor: Russell John Fagg
  • Patent number: 8363774
    Abstract: A representative method of serial link transceiver without external reference clock is disclosed. The method includes: receiving an incoming signal; generating a local timing under control of a control code; generating a temperature sensor code by sensing a local temperature; generating a logical signal by detecting a presence of the incoming signal; adjusting the control code in a closed loop manner to make the local timing match that of the incoming signal and recording the control code and a value of the temperature sensor code as part of a template when the logical signal is asserted; and synthesizing the control code in accordance with the template when the logical signal is not asserted.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: January 29, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chia-Liang Lin, Gerchih Chou, Hong-Yean Hsieh
  • PLL
    Patent number: 8339206
    Abstract: A PLL includes: a charge-pump equalizer which has a plurality of charge pumps generating charge currents according to phase-difference signals, each being generated by delaying the phase-difference signal by different times, adds and outputs the charge currents generated by the charge pumps; a replica circuit, having ideal characteristics of a loop filter and a voltage controlled oscillator, which input a digital value having phase difference of the phase-difference signals, and generates a replica output according to the ideal characteristics; and a coefficient generating circuit which smoothes correlation values of the difference signals and the phase-difference signals to generate charge pump coefficients, and negatively feeds back the same to the plurality of charge pumps. The charge pumps generate the charge currents each having current values corresponding to the charge pump coefficients.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masaru Sawada
  • Patent number: 8334725
    Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: December 18, 2012
    Assignee: Mediatek Inc.
    Inventors: Ping-Ying Wang, Kuan-Hua Chao, Jeng-Horng Tsai
  • Patent number: 8289057
    Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: October 16, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Kawamoto
  • Patent number: 8264388
    Abstract: A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 11, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Hanan Cohen, Simon Pang
  • Patent number: 8258878
    Abstract: A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: September 4, 2012
    Assignee: MStar Semiconductor, Inc.
    Inventors: Shih-Chieh Yen, Yao-Chi Wang, Hsu-Hung Chang
  • Patent number: 8255733
    Abstract: A method of providing a clock signal for an embodiment includes performing a calibration for a closed loop control system to determine a control signal value that provides a desired tuning of the closed loop control system. The control signal value is stored and provided to a delay circuit, wherein a delay range and a delay step size of the delay circuit is based on the control signal value. A delay select control signal is provided to the delay circuit to select a specific delay within the delay range.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: August 28, 2012
    Assignee: Lattice Semiconductor Corporation
    Inventors: Robert M. Bartel, Kent R. Callahan, Michael G. France
  • Patent number: 8242848
    Abstract: An oscillation frequency control circuit configured to control a frequency of a second clock signal of an oscillation circuit generating and outputting the second clock signal having a frequency in response to an input control signal is disclosed. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a frequency of a predetermined first clock signal input externally and the frequency of the second clock signal, and generate and output a signal indicating a result of the detection; and a frequency control circuit unit configured to control the frequency of the second clock signal so that the frequency of the second clock signal continually changes back and forth between a predetermined lower limit value and a predetermined upper limit value in response to the output signal from the frequency difference detection circuit.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: August 14, 2012
    Assignee: Ricoh Company, Ltd.
    Inventor: Takashi Michiyoshi
  • Patent number: 8183934
    Abstract: In a PLL circuit, a threshold discriminator generates a control signal indicating a relative level of a control voltage. A controller outputs a controlling value based on the control signal. If the control signal indicates a high level when the controlling value specifies a control voltage-to-oscillation frequency correspondence relation whose upper and lower limits of oscillation frequency are highest, and if the control signal indicates a low level when the controlling value specifies a correspondence relation whose upper and lower limits of oscillation frequency are lowest, the controller outputs a predetermined controlling value. An oscillator has the correspondence relations set therein such that the correspondence relations have respective different upper and lower limits of oscillation frequency and are correlated with the respective controlling values.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: May 22, 2012
    Assignee: Fujitsu Limited
    Inventors: Tetsuji Yamabana, Kouichi Kanda
  • Patent number: 8134392
    Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: March 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Kawamoto
  • Patent number: 8125254
    Abstract: In some embodiments, a feedback loop circuit includes a phase detector, first and second charge pumps that are each coupled to receive an output signal of the phase detector, a first low pass filter, a second low pass filter coupled to an output of the second charge pump, a clock signal generation circuit having first and second control inputs, a first switch circuit coupled between the first low pass filter and the second low pass filter, and a second switch circuit coupled to the first low pass filter and the first control input of the clock signal generation circuit.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: February 28, 2012
    Assignee: Altera Corporation
    Inventor: Weiqi Ding
  • Patent number: 8120394
    Abstract: An automatic frequency calibration circuit and an automatic frequency calibration method for a fractional-N frequency synthesizer are provided. In a calibration mode, a state machine adjusts a fractional part and an integer part of a division ratio of a frequency divider unit according to a required precision. A first and a second frequency detecting units detect a reference frequency and an output frequency of the frequency divider unit, respectively. A judging interval unit defines at least one judging period in a total comparison time. A comparator compares the outputs of the first and the second frequency detecting units and outputs a comparison result at the judging period. Wherein, the state machine changes the capacitor configuration of a voltage-controlled oscillator when the comparison result shows that the reference frequency does not match the output frequency of the frequency divider unit.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: February 21, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Shih-Hao Tarng, Jia-Hung Peng, Ming-Ching Kuo
  • Patent number: 8089317
    Abstract: A phase-locked loop circuit includes a phase detection unit, a loop filter unit including a series circuit of a resistor and a capacitor, first and second pulse-current output units which supply differential and single-end pulse currents corresponding to phase information to the resistor and capacitor, an oscillating unit which varies an oscillation frequency in accordance with a voltage generated at the resistor and capacitor, and a calibration unit which obtains information of an oscillation gain in actual operation and corrects an operation of the oscillating unit on the basis of a difference between the oscillation gain in actual operation and a target oscillation gain. The oscillation gain in actual operation represents a characteristic of oscillation frequency versus input signal of the oscillating unit and is obtained using predetermined oscillation control signals on the basis of a difference between actual oscillation frequencies under the oscillation control signals.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: January 3, 2012
    Assignee: Sony Corporation
    Inventors: Tetsuya Fujiwara, Yosuke Ueno
  • Patent number: 8085098
    Abstract: A PLL circuit comprising an oscillation unit, a frequency division unit, a phase comparison unit, and a generation unit comprises a switching unit that switches between a first state in which a control voltage output from the generation unit is input into the oscillation unit and a second state in which a reference voltage is input into the oscillation unit; and a correction unit that, in the second state, compares the control voltage output from the generation unit with the reference voltage, and corrects a frequency at which the oscillation unit oscillates with respect to a voltage input into the oscillation unit, such that the control voltage output from the generation unit is equivalent to the reference voltage.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: December 27, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshikazu Yamazaki
  • Patent number: 8063707
    Abstract: Phase locked loop circuits capable of increasing an equivalent capacitance thereof to improve stability are provided, in which an integral part comprises a first phase frequency detector providing a phase error signal, a first charge pump circuit generating a control signal according to the phase error signal, a controllable oscillator providing an output clock according to the control signal, and a sampling adjustment unit decreasing the number of times the control signal is updated according to the phase error signal. A proportional part is coupled between the controllable oscillator and a reference clock and operated in a fraction mode.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: November 22, 2011
    Assignee: Mediatek Inc.
    Inventor: Ping-Ying Wang
  • Publication number: 20110254632
    Abstract: A voltage-controlled oscillator (VCO) includes an inductor, a fine-adjustment capacitor, and a coarse-adjustment capacitor, and generates an oscillation clock. A frequency divider divides the frequency of the oscillation clock to generate a divided clock. A direct current (DC) voltage supply circuit supplies a DC voltage to a control node, and changes a voltage value of the DC voltage according to a DC value of an oscillation voltage in a coarse-adjustment mode. A frequency-band selection circuit switches a capacitance value of the coarse-adjustment capacitor based on a frequency difference between a reference clock and the divided clock so that an oscillation frequency band of the VCO is set to an oscillation frequency band corresponding to a target frequency in the coarse-adjustment mode. An oscillation control circuit increases or decreases a control voltage according to a phase difference between the reference clock and the divided clock in the fine-adjustment mode.
    Type: Application
    Filed: June 28, 2011
    Publication date: October 20, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Akihiro SAWADA
  • Patent number: 8018289
    Abstract: A clock circuit includes a phase-lock loop and a holdover circuit. The phase-lock loop generates an output clock signal having a constant frequency based on a loop filter voltage of a loop filter in the phase-lock loop. The holdover circuit generates and stores a digital value indicating the loop filter voltage and generates an analog voltage signal having the loop filter voltage indicated by the digital value. Further, the holdover circuit maintains the output clock signal at the constant frequency during a holdover of the phase-lock loop by regenerating the loop filter voltage based on the analog voltage signal. Because the analog voltage signal is based on the digital value, the voltage of the loop filter does not decay over time during the holdover of the phase-lock loop. As a result, the output clock signal remains at the constant frequency during the holdover of the phase-lock loop.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: September 13, 2011
    Assignee: Integrated Device Technology, Inc.
    Inventors: Pengfei Hu, Song Gao
  • Patent number: 7982552
    Abstract: An automatic frequency calibration apparatus and a method thereof for a phase-locked loop based frequency synthesizer are disclosed. The apparatus includes a frequency-to-digital converter configured to convert a frequency of a VCO output signal to a first digital value, a target value setting section configured to provide a second digital value corresponding to a target frequency, and a finite state machine configured to calibrate the frequency of the VCO output signal by using the difference of the first digital value and the second digital value. Accordingly, the calibration speed and a frequency resolution of the automatic frequency calibration apparatus in a frequency synthesizer may be enhanced.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: July 19, 2011
    Assignee: Kwangwoon University Industry-Academic Collaboration Foundation
    Inventors: Hyunchol Shin, Jaewook Shin
  • Publication number: 20110163815
    Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.
    Type: Application
    Filed: September 8, 2009
    Publication date: July 7, 2011
    Applicant: ICERA INC.
    Inventors: Abdellatif Bellaouar, Ahmed R. Fridi, Sher Jiun Fang, Hamid Safiri
  • Patent number: 7932784
    Abstract: The present invention is a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. The FPLL synthesizer includes a variable frequency oscillator, which is controlled by FLL circuitry during the FLL operating mode or by PLL circuitry during the PLL operating mode. The FLL circuitry includes frequency division circuitry for reducing the frequency of the output signal, frequency detection circuitry for measuring the frequency error of the frequency reduced output signal, and a loop filter to control the bandwidth of an FLL control loop formed by the FLL circuitry and the variable frequency oscillator.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: April 26, 2011
    Assignee: RF Micro Devices, Inc.
    Inventors: Stephen T. Janesch, William J. Farlow, Scott Robert Humphreys