Abstract: Disclosed is a pulse elimination circuit, a voltage detection circuit and a detection method, referring to a field of electronic circuit technology. The pulse elimination circuit comprises: a clock generation circuit configured to receive a logic signal and a first input signal and generate a clock signal according to the logic signal and the first input signal; a counter coupled with the clock generation circuit and configured to receive the clock signal and count a number of cycles of the clock signal to generate a second input signal; a signal output circuit coupled to the counter and configured to supply a first input signal to the clock generation circuit and generate a pulse elimination signal based on the second input signal. Therefore, in a process of voltage detection, this circuit can eliminate a false trigger caused by short pulse and improve voltage detection accuracy.

Abstract: Various embodiments disclosed herein relate to adaptive clock signal management, and more specifically to generating a clock signal at desired frequencies based on inputs to a clock subsystem for peripheral use. A clock subsystem is provided herein that comprises an oscillator configured to provide a clock signal at either a first frequency or a second frequency, and a controller coupled to the oscillator and configured to perform various functions. The controller can be configured to determine a desired frequency of the clock signal based on a state of each input of multiple inputs, wherein the multiple inputs comprise a power mode input and an analog-to-digital converter input, and provide a signal to the oscillator to produce the clock signal at the desired frequency.

Abstract: A phase-locked loop circuit includes a phase frequency detector (PFD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.

Abstract: A phase-locked loop (PLL) that provides a local oscillator signal for a radio. An oscillator of the PLL supplies an oscillator output signal. Control logic receives a request to change the oscillator output signal to a new frequency and responds to the request by setting a first capacitor circuit of the oscillator to a first capacitance that corresponds to a predetermined frequency of the oscillator output signal. The control logic also responds to the request by setting one or more other capacitor circuits of the oscillator according to temperature and according to a frequency difference between the predetermined frequency and the new frequency. After responding to the request by setting the first capacitor circuit and the one or more other capacitor circuits, the PLL locks to the new frequency using a signal from the PLL loop filter to adjust another capacitor circuit in the oscillator.

Abstract: Systems and methods are provided for compensating for mechanical acceleration at a reference oscillator. A reference oscillator provides an oscillator output signal and an accelerometer on a same platform as the reference oscillator, such that mechanical acceleration at the reference oscillator is detected at the accelerometer to produce a measured acceleration. A filter assembly, having an associated set of filter weights, receives the measured acceleration from the accelerometer and provides a tuning control signal responsive to the measured acceleration to a frequency reference associated with the system. An adaptive weighting component receives the oscillator output signal of the reference oscillator and an external signal that is provided from a source external to the platform and adjusts the set of filter weights for the filter assembly based on a comparison of the external signal and the oscillator output signal.

Abstract: A phase locked loop includes a phase detector outputting a first signal corresponding to a phase difference of a reference frequency signal and a division frequency signal, a charge pump amplifying a first signal to output a second signal, a loop filter filtering the second signal to output a third signal, a voltage-to-current converter receiving the third signal and outputting a fourth signal, a digital-to-analog converter outputting a fifth signal based on the fourth signal and a digital compensation signal, an oscillator outputting an output frequency signal having a frequency corresponding to the fifth signal, a divider dividing the frequency of the output frequency signal to output the division frequency signal and a compensation frequency signal, and an automatic frequency calibrator compensating for the voltage-to-current converter based on a difference between a frequency of the compensation frequency signal and a frequency of a reference frequency signal.

Abstract: A PLL includes a phase-frequency-detector-and-charge-pump-circuit (PFDCPC) receiving a reference signal and divided signal, and generating a charge-pump current. A loop-filter is between output of the PFDCPC and a reference-voltage. A first voltage-to-current converter (V2I1) has low gain, and a second voltage-to-current converter (V2I2) has high gain. A low-gain-path is between outputs of the PFDCPC and V2I1, and a high-gain-path is between the outputs of the PFDCPC and V2I2. A current-controlled-oscillator receives an input signal, and generates an output signal. A loop divider divides the output signal by a divider-value, producing the divided signal. The low-gain-path runs directly from the PFDCPC, through the V2I1, to the input of the current-controlled-oscillator. The high-gain-path runs from the PFDCPC to the loop-filter, from a tap of the loop-filter to a low-pass filter through a current mirror, from a tap of the low-pass filter through the V2I2, to the input of the current-controlled-oscillator.

Abstract: An electronic device includes a phase locked loop configured to perform a two-point modulation operation on a data signal by using first and second modulation paths, and the phase locked loop is configured to generate, based on a differential value of a first phase error signal generated in the first modulation path, a gain for adjusting a frequency variation of the data signal through the second modulation path so as to match with the frequency variation of the data signal through the first modulation path.

Abstract: Systems and methods are provided for compensating for mechanical acceleration at a reference oscillator. A reference oscillator provides an oscillator output signal and an accelerometer on a same platform as the reference oscillator, such that mechanical acceleration at the reference oscillator is detected at the accelerometer to produce a measured acceleration. A filter assembly, having an associated set of filter weights, receives the measured acceleration from the accelerometer and provides a tuning control signal responsive to the measured acceleration to a frequency reference associated with the system. An adaptive weighting component receives the oscillator output signal of the reference oscillator and an external signal that is provided from a source external to the platform and adjusts the set of filter weights for the filter assembly based on a comparison of the external signal and the oscillator output signal.

Abstract: A clock data recovery device includes a phase detector circuitry, a signal control circuitry, and interpolators. The phase detector is configured to detect a phase of an input signal, according to first clock signals, to generate first control signals, and phases of the first clock signals are different to each other. The signal control circuitry is configured to rearrange the first control signals to output as second control signals. The phase interpolators are configured to output second clock signals and alternatively adjust the phases of the second clock signals according to the second control signals to generate an output clock signal.

Abstract: A radar system includes one or more antennas to emit transmit signals and receive reflected signals resulting from reflection of the transmit signals by an object. The transmit signals are linear frequency modulated continuous wave (LFMCW) signals. The radar system also includes a transmission generator to generate the transmit signals. The transmission generator includes a controller to control output of a first of the transmit signals and a second of the transmit signals in succession. A time between transmission of the first of the transmit signals and the second of the transmit signals is less than a duration of a stabilization period of a first oscillator used to generate the first of the transmit signals.

Abstract: An LC oscillator has a tank driver connected to cause a matched-resistance LC tank to oscillate. The LC tank has an inductor leg in parallel with a capacitor leg. The inductor leg has an explicit inductor having an implicit resistance level RL. The capacitor leg has an explicit capacitor having an implicit resistance level RC connected in series with an explicit resistor having an explicit resistance level RR, where RM=(RC+RR) is substantially equal to RL. The LC oscillator may have a non-trimmable LC tank and be part of a temperature-compensated frequency reference generator having standalone frequency adjustment circuitry that offers better than ±0.1% frequency accuracy (after single trim and batch calibration) over process, voltage, and temperature variations, and lifetime, which can serve as a low-cost replacement for a crystal oscillator for many applications.

Abstract: The present invention provides a method for measuring an internal Phase Locked Loop of a Central Processing Unit (CPU) by a frequency meter, wherein the method comprises following steps: the (CPU) outputting an oscillation excitation signal to a crystal circuit; the crystal signal generating a clock signal; the internal loop respectively outputting the clock signals that does not pass through and passes through the phase locked loop; adopting a frequency meter to receive the clock signals and perform a clock precision test to correspondingly obtain a first test result and a second result; comparing the first test result and the second result to obtain a result of the stability of the phase locked loop. The beneficial effects of the invention: the operation is simple and it does not need to buy an expensive oscilloscope, the accurate precision of the PLL can be measured without the influence of the crystal.

Abstract: A clock generator includes an oscillator that generates a clock signal as an output of the clock generator, where the frequency of the clock signal is dependent on a bias current. A feedback circuit receives the clock signal and generates a feedback signal indicative of a frequency of the clock signal. A voltage detector generates a charged voltage using the feedback signal, compares a source voltage with the charged voltage, and generates a detection signal indicative of the comparison between the source voltage and the charged voltage. A control voltage generator generates a control voltage using the detection signal. The bias current is generated by a bias current source using the control voltage.

Abstract: An example clock synthesizer, having a single-phase clock signal as input and generating an output clock, includes a phase decrementer configured to receive a fractional period value, configured to, responsive to the fractional period value, maintain a fractional count, and configured to accumulate residual phase from cycle-to-cycle of the output clock. A clock generator provides an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero. A clock phase selector is configured to provide a signal having a fractional portion of the fractional count. A phase generator and combiner is coupled to an output of the clock generator, and an output of the clock phase selector, and is configured to provide the output clock.

Abstract: A phase reference system for a phase-sensitive receiver is shown that provides an output signal which can be used for phase calibration of a frequency-converting device under test. The phase reference system has a first frequency generator that generates a first generator signal with a first generator frequency fg1 and a second frequency generator that generates a second generator signal with a second generator frequency fg2. The first and second generator signals are fed to a multiplier. The multiplier process the signals and outputs first, second and third spectral line data.

Abstract: Certain aspects of the present disclosure generally relate to a programmable multi-mode digital-to-analog converter (DAC) for generating a frequency-modulated signal. For example, certain aspects provide a circuit for sweeping a frequency of an output signal. The circuit generally includes a DAC having an input coupled to an input path of the circuit and an output coupled to an output path of the circuit, a first mixer selectively incorporated in the input path coupled to the input of the DAC, and a second mixer selectively incorporated in the output path coupled to the output of the DAC.

Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Abstract: In examples, a voltage-controlled oscillator (VCO) comprises an inductor; a first pair of transistors having first terminals coupled to a voltage source, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor; and a second pair of transistors having first terminals coupled to ground, second terminals coupled to opposing ends of the inductor, and control terminals coupled to opposing ends of the inductor. The VCO also comprises a first transistor coupled to at least one capacitor, the combination of the first transistor and the at least one capacitor coupled to the inductor in parallel. The VCO further comprises second, third, and fourth transistors coupled to a control terminal of the first transistor, the second transistor coupled to the voltage source, the fourth transistor coupled to ground, and the third transistor configured to receive a ramped voltage.

Abstract: The present disclosure provides for a system and method for compensating an electronic oscillator for one or more environmental parameters. A method may comprise segmenting test data received from an output signal of the oscillator and generating at least one correction voltage to thereby compensate the oscillator for one or more environmental parameters. A system may comprise at least one multi-function segmented array compensation module configured to receive one or more output signals from an oscillator and generate one or more correction voltages to thereby compensate the oscillator for environmental parameters. The system may also comprise one or more sensors and a user EFC.

Abstract: Frequency synthesizer circuitry includes multi-phase clock generator circuitry, frequency divider circuitry, signal retiming circuitry, and signal combining circuitry. The multi-phase clock generator circuitry receives an input clock signal and generates a number of multi-phase clock signals. The frequency divider circuitry also receives the input clock signal and performs frequency division thereon to generate a reference signal. The signal retiming circuitry receives the reference signal and the multi-phase clock signals and generates a number of retiming signals. The signal combining circuitry combines two of the retiming signals to provide an output clock signal that has the same frequency as the reference signal but a different duty cycle.

Abstract: A voltage-controlled oscillator generates a VCO output signal at frequency fM. A dual optical-frequency source generates optical signals at frequencies v1S and v2S. An electro-optic frequency divider (EOFD) generates multiple optical sidebands spaced by fM, and from two sidebands generates a beat signal at beat frequency ?f. A first control circuit generates an error signal from the beat signal and a first reference signal at frequency fREF1, and couples the VCO and the EOFD in a negative feedback arrangement that stabilizes the output frequency fM. A second control circuit generates an error signal from the frequency-divided output signal and a second reference signal at frequency fREF2, and couples the VCO and one or both of the dual source or the first reference signal in a negative feedback arrangement that stabilizes, or compensates for fluctuations of, a difference frequency v2S?v1S.

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Abstract: The present disclosure relates to a frequency locked loop including a frequency detection unit, a local oscillator, and a multi-bit sampler. The frequency detection unit is configured to receive a reference frequency parameter and a sub-sampled frequency parameter, and configured to generate a digital frequency difference, which is a difference indication between the reference frequency parameter and the sub-sampled frequency parameter. The local oscillator is configured to generate an output signal based on the digital frequency difference. The multi-bit sampler is configured to update the sub-sampled frequency parameter by sub-sampling the output signal with N (N>=2) sampling-clocks. The N sampling-clocks have a same sampling frequency and are sequentially offset by an equal time delay between adjacent sampling-clocks. The updated sub-sampled frequency parameter monotonically maps an output frequency of the output signal.

Abstract: A method and system for vibration correction in an oscillator. The method includes sensing vibrations along one or more axes via at least one accelerometer mounted on the oscillator, determining corrective factors based on an acceleration signal received from the at least one accelerometer by referencing a look-up table; and controlling the oscillator based on at least the corrective factors.

Abstract: According to an aspect, an active noise control device includes: a control frequency determinator that determines a frequency of the noise; a reference cosine-wave generator that generates a reference cosine-wave signal having the determined frequency; a reference sine-wave generator that generates a reference sine-wave signal having the frequency of a noise; a first one-tap adaptive filter to which the reference cosine-wave signal is input, the first one-tap adaptive filter having a first filter coefficient; a second one-tap adaptive filter to which the reference sine-wave signal is input, the second one-tap adaptive filter having a second filter coefficient; an adder that adds an output signal from the first one-tap adaptive filter and an output signal from the second one-tap adaptive filter to each other; a secondary noise generator that is driven by an output signal from the adder to generate a secondary noise; a residual sound detector that detects a residual sound generated by interference between the s

Abstract: An oscillation apparatus includes: an oscillation circuit; a timing control circuit that generates a timing signal using an output clock of the oscillation circuit; an integration circuit that cyclically integrates a reference current based on the timing signal to output an output voltage value; a comparison circuit that compares the output voltage value of the integration circuit with predetermined threshold voltage and outputs a comparison result; a steady voltage changing circuit that, when it is shown by the comparison result of the comparison circuit that the output voltage value of the integration circuit exceeds the threshold voltage, returns the output voltage value of the integration circuit by a predetermined amount; and a frequency adjustment circuit that generates a control signal for adjusting an oscillation frequency of the oscillation circuit based on a value obtained by averaging the comparison result in plurality of the comparison circuit.

Abstract: An electronic device includes a drive section, a detection signal output section adapted to generate a first analog signal having a value varying in accordance with a physical quantity, and a control section adapted to generate a second analog signal controlled based on the first analog signal, and adapted to control a drive state of the drive section, at least the detection signal output section and the control section are provided to a substrate, and a first digital signal obtained by digitalizing the first analog signal and a second digital signal obtained by digitalizing the second analog signal can be output from the substrate.

Abstract: A circuit for generating a plurality of oscillating signals with different phases includes a frequency divider, a first delay chain, a second delay chain and a calibration circuit. The frequency divider is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain is arranged for delaying the first frequency-divided input signal, and the second delay chain is arranged for delaying the second frequency-divided input signal. The calibration circuit is arranged for controlling delay amounts of the first delay chain and the second delay chain according to signals within the first delay chain or the second delay chain; wherein output signals of a portion delay cells within the first delay chain and the second delay chain serve as the plurality of oscillating signals with different phases.

Abstract: A method for operating an electronic device via a touchscreen, wherein the operation is carried out on the basis of a position signal generated by an input movement touching the touchscreen, includes carrying out a filtering of the position signal in such a way that at least one movement component of the input movement is at least partially suppressed, wherein a filtered position signal is obtained, and actuating the electronic device on the basis of this filtered position signal.

Abstract: The present disclosure provides for a system and method for compensating an electronic oscillator for one or more environmental parameters. A method may comprise segmenting test data received from an output signal of the oscillator and generating at least one correction voltage to thereby compensate the oscillator for one or more environmental parameters. A system may comprise at least one multi-function segmented array compensation module configured to receive one or more output signals from an oscillator and generate one or more correction voltages to thereby compensate the oscillator for environmental parameters. The system may also comprise one or more sensors and a user EFC.

Abstract: A circuit comprises a cascode core circuit and a current adjustor circuit. The cascode core circuit has an output node and a current path (ID). The current adjustor circuit is configured to change a current on the current path in response to a change in a voltage at the output node. The cascode core circuit comprises a first transistor, a second transistor, and a third transistor. A first terminal of the first transistor is coupled to a second terminal of the second transistor and to a third terminal of the third transistor. A first terminal of the second transistor is configured as the output node. A first terminal of the third transistor is coupled to a third terminal of the second transistor. The current path is through the first terminal of the third transistor.

Abstract: A control device for a clock generation circuit that generates a clock signal based on a reference signal from an outside, the control device includes: a storage device that stores frequency correction information for the clock signal according to a temperature condition of the clock generation circuit; and a processor that controls a frequency of the clock signal generated by the clock generation circuit under a second temperature condition, based on first and second frequency correction information according to a first temperature condition at first and second time points in the storage device.

Abstract: Apparatuses and methods concerning regulation of load currents are disclosed. As an example, one apparatus includes a first clock generation circuit configured to generate a first clock signal with a frequency spectrum having a first frequency range. A second clock generation circuit is configured to produce a second clock signal by spreading the frequency spectrum of the first clock signal to have a second frequency range that is wider than the first frequency range. The second clock signal has a frequency spectrum extending outside of the frequency range. The apparatus includes a third circuit configured to regulate a voltage at a supply node as a function of the second clock signal. A current regulation circuit is configured to regulate current in a circuit path, from the supply node and passing through a load circuit coupled to the current regulator, as a function of the first clock signal.

Abstract: In a method for mitigating the vibration-induced phase noise of an phase locked loop with an acceleration sensitive voltage controlled oscillator, a correction signal generated by applying a gain and a equalization to an acceleration signal provided by an acceleration sensor sensing the acceleration on the VCO, is added to the oscillator control signal for active compensation, an adaptive compensation unit dynamically adjusts the gain, the frequency response of equalization, and the sensing direction of the acceleration sensor while the phase locked loop is working to make the active compensation automatically adapt to the parameters of the voltage controlled oscillator.

Abstract: A transmission apparatus transmits a data signal to a reception apparatus with use of a first clock generated on the basis of a clock signal given to the transmission apparatus. The transmission apparatus changes an operation band of a PLL section to an operation band including a frequency of the clock signal which frequency has been measured with use of a second clock independent of the first clock. The transmission apparatus provides the reception apparatus with band information indicative of the operation band to which the operation band of the PLL section has been changed.

Abstract: In one embodiment, a phase locked loop (PLL) comprises a voltage-controlled oscillator (VCO), a frequency divider configured to frequency divide an output signal of the VCO to produce a feedback signal, and a phase detection circuit configured to detect a phase difference between a reference signal and the feedback signal, and to generate an output signal based on the detected phase difference. The PLL also comprises a proportional circuit configured to generate a control voltage based on the output signal of the phase detection circuit, wherein the control voltage tunes a first capacitance of the VCO to provide phase correction. The PLL further comprises an integration circuit configured to convert the control voltage into a digital signal, to integrate the digital signal, and to tune a second capacitance of the VCO based on the integrated digital signal to provide frequency tracking.

Abstract: A method for phase recovery in a system that includes a clock recovery unit and an estimation unit. The clock recovery unit of the system has a first phase detector unit. The estimation unit has a second phase detector unit and it is configured to estimate a gain of the second phase detector unit. The estimation unit and the clock recovery unit are configured to operate in parallel.

Abstract: A system and method for determining errors and calibrating to correct errors associated with field sensors, including bias, scale, and orthogonality, includes receiving and providing to a processor angular rate data and a first field vector relative to a first reference directional field and a second field vector relative to a second reference field from at least one field sensor. The processor is configured to relate the first field vector and the second field vector to the angular rate data to determine an error of the at least one field sensor. The processor is also configured to identify a compensation for the error of the at lease one field sensor needed to correct the first field vector and the second field vector and repeat the preceding to identify changes in the error over time and compensate for the changes in the error over time.

Abstract: A method of processing an amplitude-modulated analog signal at a carrier frequency Fc comprises: digitizing the analog signal to produce an input bit stream that represents the amplitude of the analog signal; generating an in-phase reference bit stream that is synchronous to the carrier frequency Fc and represents an in-phase digital reference signal substantially in the form of a sine and/or cosine wave; and multiplying the input bit stream with the in-phase reference bit stream to produce an output bit stream representing the amplitude modulation of the analog signal.

Abstract: An electric pump device of an aspect of the invention includes a state determination unit and a gain adjusting unit. The state determination unit determines whether or not the electric pump device is in a stable state where a required oil pressure is supplied to a hydraulic operating device by maintaining a rotation state of a motor. The gain adjusting unit adjusts a gain for a current feedback control so as to reduce responsiveness of the current feedback control when the state determination unit determines that the electric pump device is in the stable state.

Abstract: A compensation apparatus compensates a quadrature-demodulated signal output from a quadrature demodulator 5 that performs quadrature demodulation by using a signal of a carrier frequency fc, by removing an image component caused by the quadrature demodulator 5 from the quadrature-demodulated signal. The compensation apparatus includes a signal generator 10 that generates a reference signal having a predetermined bandwidth in a reception band, and provides the reference signal to an input side of the quadrature demodulator 5. The reference signal includes a frequency band that is biased to either a higher-frequency side or a lower-frequency side with respect to the carrier frequency.

Abstract: An internal voltage generation circuit includes a comparison unit suitable for comparing a voltage level of a feedback voltage with that of a reference voltage, and generating a comparison signal and an acceleration voltage, a pull-up driving unit suitable for driving an internal voltage terminal to be pulled up in response to the comparison signal, a discharging unit suitable for discharging the internal voltage terminal in response to the acceleration voltage, and a voltage division unit suitable for dividing a voltage level of the internal voltage terminal, and generating the feedback voltage.

Abstract: The present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis.

Abstract: A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal.

Abstract: A slew rate enhancing system includes a first input configured to receive a first complementary signal of a differential pair and a second input configured to receive a second complementary signal of the differential pair. The slew rate enhancing system further includes a first switch configured to selectively connect the first input to an output in response to a voltage of the second input being greater than a first predetermined voltage. The slew rate enhancing system further includes a second switch configured to selectively connect the first input to the output in response to the voltage of the second input being less than a second predetermined voltage.

Abstract: According to one embodiment, a phase locked loop (PLL) circuit includes an application unit, a correlator, an integrator and a power supply noise canceller. The application unit applies the test signal to a power supply voltage. The correlator extracts a frequency error signal as a monitor signal and calculates a correlation value for the test signal and the monitor signal to generate a correlation signal. The integrator integrates the correlation signal to generate an integral signal. The power supply noise canceller provides a cancellation gain corresponding to the integral signal to the power supply voltage to which the test signal is applied, to generate a control signal.

Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.

Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.