Abstract: Disclosed is a microwave cavity resonator used as a phase change (phase modulation) to intensity change (intensity or amplitude modulation) converter. Certain aspects and embodiments include resonant circuits, such as a resistor, inductor and capacitor (RLC) circuit. Certain aspects and embodiments convert changes in phase to changes in output voltage to perform analog demodulation of a phase modulated microwave carrier. Certain aspects and embodiments use resonance when the reactive components of the circuit (capacitive and inductive components) are equal in magnitude and 180 degrees out of phase with one another, thereby cancelling out the reactance component of the circuit's impedance.

Abstract: A semiconductor device includes a signal delay circuit configured to output a plurality of multi-phase output signals by delaying a plurality of multi-phase input signals according to a plurality of delay codes, respectively; and a calibration circuit including an error detection circuit configured to provide phase difference information between signals selected among the plurality of the multi-phase output signals according to a variable delay code and a filter configured to provide the plurality of delay codes and the variable delay code, wherein the filter performs update operation to update the plurality of delay codes or the variable delay code.

Abstract: Novel phase locked loop architectures that can overcome the limitation of the maximum operating frequency of the fractional-N phase-locked loop (PLL) for fast-chirp frequency modulated continuous wave (FMCW) radars are suggested. Several phase frequency detector and charge pumps (PFD&CPs) are put in parallel and are operated with reference signals that are generated by using a delay-locked loop (DLL) instead of further increasing the operating frequency of the PFD&CP. The proposed DLL supported parallel PLL architectures enable further speeding up the FMCW chirp as well as improving its linearity and the performance of Range Doppler Radars based on fast-chirp FMCW radar. Methods for operating the parallel fractional N phase locked loop are proposed.

Abstract: A phase locked loop, particularly for or in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), the second feedback signal (FBD) delayed with respect to the first feedback signal (FB); a first comparator path (4) configured to receive the first feedback signal (FB) and a second comparator path (5) configured to receive the second feedback signal (FBD), each of the first and second comparator path (4, 5) configured to provide a respective current signal (CS1, CS2) to the loop filter (1) in response to a respective adjustment signal (FA1, FA2) and a phase deviation between a common reference signal (FR) and the respective feedback signal (FB, FBD).

Abstract: The disclosed embodiments relate to a system that controls a phase-locked loop (PLL), eliminating harmonic locking issues during subsampling operation and achieving better noise performance. During operation, the system performs a procedure to measure a first duty cycle that indicates a relationship between a reference signal, which has a frequency FREF, and a voltage-controlled oscillator (VCO) output signal, which has a frequency FVCO and is generated by a VCO. The system also performs the procedure to measure a second duty cycle that indicates a relationship between a second reference signal (with a frequency of c*FREF) and the VCO-output signal. Next, the system determines a frequency and phase relationship between the reference signal and the VCO-output signal based on the first and second duty cycles.

Abstract: A current mode hysteretic buck converter employing an auto-selectable frequency locking circuit is disclosed. The auto-selectable frequency locking type buck converter include a current mode hysteretic buck converter for converting an input DC voltage into a lower DC voltage, and a frequency locking unit for locking a switching frequency of the current mode hysteretic buck converter wherein the switching frequency is locked through adjusting a locking value of the switching frequency to be a predetermined value according to a size of a load. The buck converter is, based on the current mode hysteretic control, related to a circuit that locks the switching frequency of the converter to reduce the difficulty of designing electromagnetic interference (EMI) filters in the converter. In addition, the buck converter can improve the efficiency at light load by adjusting the switching frequency which is locked according to the load current.

Abstract: Methods, systems, and apparatus for detecting a center frequency of an input signal, the input signal including a carrier signal modulated with a modulation signal. Detecting a frequency of a second signal. Determining a difference signal between the center frequency of the input signal and the frequency of the second signal. Modifying the frequency of the second signal based on the difference signal to provide the carrier signal. And, outputting the carrier signal.

Abstract: This invention provides a method and an apparatus for recreating data collected from a machine for distribution to one or more remote terminals for monitoring and evaluating machine operations. Machine operation parameters are sensed by at least one sensor, and the data collected regarding measured values of machine operations are transmitted to a conditioning device. The conditioning device validates the data by comparing and correlating the measured values to predetermined values of acceptable data set and converts output data from analog to digital data. The digitized analog data according to the measured parameters associated with machine operations are then transmitted to a data storage unit, where it is stored and subsequently retrieved for recreating the machine operation parameters to become accessible by one or more remote terminals.

Abstract: In one embodiment of the invention, a semiconductor optical amplifier (SOA) in a laser ring is chosen to provide low polarization-dependent gain (PDG) and a booster semiconductor optical amplifier, outside of the ring, is chosen to provide high polarization-dependent gain. The use of a semiconductor optical amplifier with low polarization-dependent gain nearly eliminates variations in the polarization state of the light at the output of the laser, but does not eliminate the intra-sweep variations in the polarization state at the output of the laser, which can degrade the performance of the SS-OCT system.

Abstract: Methods, systems, and apparatus for detecting a center frequency of an input signal, the input signal including a carrier signal modulated with a modulation signal. Detecting a frequency of a second signal. Determining a difference signal between the center frequency of the input signal and the frequency of the second signal. Modifying the frequency of the second signal based on the difference signal to provide the carrier signal. And, outputting the carrier signal.

Abstract: For each pair of a plurality of slave lasers B for which injection synchronization is performed by a master laser M, by controlling the intensity of light exchanged between two slave lasers B and an optical path length between the two slave lasers B using a slave-to-laser intensity control unit IA and an inter-slave laser optical path length control unit IP, the magnitude and the sign of pseudo ising interaction Jij between the two slave lasers B are implemented. After the plurality of slave lasers B arrive at a steady state, by measuring relative values of the oscillation phases of the plurality of slave lasers B with respect to the oscillation phase of the master laser M by using an oscillation phase measuring unit PM, pseudo ising spins ?i of the plurality of slave lasers B are measured.

Abstract: Methods, systems, and apparatus for detecting a center frequency of an input signal, the input signal including a carrier signal modulated with a modulation signal. Detecting a frequency of a second signal. Determining a difference signal between the center frequency of the input signal and the frequency of the second signal. Modifying the frequency of the second signal based on the difference signal to provide the carrier signal. And, outputting the carrier signal.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: Described are a method for generating a metric that is a function of a phase difference between a modulated carrier and a local carrier, and a phase detector for performing such a method. A baseband symbol is obtained from the modulated carrier, and the phase of the symbol is determined. Assuming that the modulation used to modulate the modulated carrier has a constellation diagram with M-fold rotational symmetry, the metric can be generated from the phase by evaluating a base function that includes a triangle wave having positively and negatively sloped linear segments whose slopes have identical absolute values and that is periodic with a period of 2?/M radians. Alternatively or additionally, if the ideal symbol phases are uniformly distributed, the metric can be generated by evaluating a version of the base function in which the ideal symbol phases correspond to identically valued metrics located on the triangle wave.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: A slew rate enhancing system includes a first input configured to receive a first complementary signal of a differential pair and a second input configured to receive a second complementary signal of the differential pair. The slew rate enhancing system further includes a first switch configured to selectively connect the first input to an output in response to a voltage of the second input being greater than a first predetermined voltage. The slew rate enhancing system further includes a second switch configured to selectively connect the first input to the output in response to the voltage of the second input being less than a second predetermined voltage.

Abstract: A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.

Abstract: An exemplary calibration apparatus for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes a capturing block arranged to capture phase error samples, and a calibrating block arranged to adjust timing of said edge rotator according to said phase error samples. An exemplary calibration method for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes the following steps: capturing phase error samples, and adjusting timing of said edge rotator according to said phase error samples.

Abstract: A calibration system may be provided for calibrating wireless communications circuitry in an electronic device during manufacturing. The calibration system may include data acquisition equipment for receiving an amplitude-modulated calibration signal from the electronic device. The calibration system may include calibration computing equipment for extracting pre-distortion coefficients from the amplitude-modulated calibration signal. The calibration computing equipment may be configured to detect a bulk phase drift in the amplitude-modulated calibration signal. The calibration computing equipment may be configured to remove the bulk phase drift from the amplitude-modulated calibration signal. The wireless communications circuitry may include a power amplifier that distorts a signal generated by the wireless communications circuitry. The wireless communications circuitry may include a pre-distortion compensator for countering the distortion.

Abstract: A wideband phase modulator comprises a multiphase generator, a phase selector, and a phase adjuster. The wideband phase modulator is configured to receive an N-bit digital phase-modulating signal comprising a timed sequence of N-bit phase-modulating words, where N is a positive integer representing the bit resolution of the N-bit digital phase-modulating signal. The multiphase generator generates a plurality of coarse carrier phases, all having the same carrier frequency but each offset in phase relative to the other. The M most significant bits of the N-bit phase-modulating words are used to form M-bit phase select words that control the output phase of the phase selector. The phase adjuster performs a precision rotation operation, whereby a selected coarse carrier phase is adjusted so that the phase of the resulting final precision phase-modulated signal more closely aligns with a desired precision phase.

Abstract: A harmonic rejection mixer converts a frequency of a radio frequency signal by using a first to a third local signals (LOs) whose phases are different from each other, and the harmonic rejection mixer includes a phase difference detection circuit for detecting a phase difference between the first LO and the second LO, a phase difference detection circuit for detecting a phase difference between the first LO and the third LO, a phase adjustment circuit for adjusting the phase of the second LO so that the phase difference detected by the phase difference detection circuit becomes a first phase difference, and a phase adjustment circuit for adjusting the phase of the third LO so that the phase difference detected by the phase difference detection circuit becomes a second phase difference. It is thereby possible to achieve high precision harmonic rejection characteristics.

Abstract: A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO.

Abstract: The present relates to a fractional-N frequency synthesizer improving noise characteristics and a method thereof.

Abstract: A modified Costas control loop (80) using switched analog low pass filters (R2, C1, C2) (R3, C3, C4) and rectangular to polar conversion (341) computes an angular phase reference error that is processed by a digital loop filter (342) to control a counter (441) and a state machine (442) that are used to control the gating of a controllably conductive circuit (84) interposed between an AC source (81) and a phase-controlled load (83) such as a dimmable lamp.

Abstract: A voltage controlled oscillator and a method of operating a voltage-controlled oscillator are disclosed. The oscillator comprises a current controlled oscillator having a variable frequency current output, a first control path for generating a first control current having a first adjustable gain, and a second control path for generating a second control current having a second adjustable gain. A summer is provided for adding the first and second control currents to obtain a summed control current, and for applying the summed control current as an input current to the current controlled oscillator. A control sub-circuit is used for controlling the gain of the first control current as a function of a defined voltage on the second control path to maintain constant the gain of the current output of the current controlled oscillator over a given operating range of the current controlled oscillator.

Abstract: In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

Abstract: A digital phase locked loop (DPLL) comprising a digitally implemented voltage controlled oscillator (VCO) for producing a VCO feedback signal, a phase error counter which includes a digital phase-frequency detector for producing a first phase error signal, a quadrature phase detector for producing a second phase error signal and an adder for adding the first and second phase error signals to obtain a combined phase error signal, and two programmable dividers used to cooperatively determine the VCO feedback signal and to provide a DPLL output line sync value synchronized with an input signal.

Abstract: A lock detection apparatus detecting lock of an optical phase-locked loop apparatus including a first phase detector comparing phases of an input light signal and a beat light signal to output a first phase comparison signal, a loop filter forming the first phase comparison signal, and an optical voltage controlled oscillator outputting the beat light signal based on the formed first phase comparison signal. The lock detection apparatus includes: a phase shifter shifting the phase of the beat light signal; and a second phase detector comparing the phases of the input light signal and the phase-shifted beat light signal to output a second phase comparison signal, wherein the phase shifter shifts a quantity of the phase so that the phase comparison signal may not be 0 when the phases of the two light signals compared by the second phase detector synchronize with each other to the beat light signal.

Abstract: In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

Abstract: There is provided a flexible transmission device capable of automatically setting an optimal point for a signal decision making with high accuracy, so that highly reliable high-quality signal regeneration control is achieved. A clock timing extraction circuit dynamically sets a frequency-dividing ratio based on the transmission rate of an input signal to perform a phase synchronization control so that there is a fixed phase difference between the input signal and an oscillation output, whereby clock timing based on the transmission rate can be extracted. A regeneration control circuit sequentially sweeps a voltage threshold level and the phase of the extracted cock with respect to the input signal and determines whether the levels of adjacent monitor points match, whereby a decision point within the valid zone of the eye pattern can be automatically measured and used as the optimal point for regeneration control.

Abstract: A low-power quadrature generator is provided for accurately generating in-phase signals and quadrature signals.

Abstract: A receiver circuit includes an oscillator circuit configured to generate a calibration tone and a phase locked loop (PLL) reference signal. An output frequency of the VCO may be divided by respective amounts to derive a desired calibration tone frequency and a desired PLL reference signal frequency. In addition to the oscillator circuit, the receiver circuit may further include a phase locked circuit configured to generate a PLL output signal that is phase locked in relation to the PLL reference signal. During a calibration mode, a quadrature generator may be used to generate quadrature mixer local oscillator signals dependent upon the PLL output signal, and an in-phase/quadrature mixer may be used to mix the calibration tone with the quadrature mixer LO signals.

Abstract: Disclosed is a PLL circuit including a deadlock detection circuit includes a counter circuit for counting a clock signal. In a deadlock state, the deadlock detection circuit outputs a deadlock detection signal responsive to an output signal from the counter circuit when the counter circuit has counted a preset number of the clock signal. The deadlock detection signal serves to release the PLL circuit from the dead lock. During the normal operation, the counter circuit does not impart noise to the PLL circuit.

Abstract: An oscillation circuit for generating two oscillation signals having a phase difference of 90° by using an LC oscillator has a disadvantage for integration. Therefore, a differential type ring oscillator comprising interpolation type delay circuits of four stages is used as an original oscillator without using any LC oscillator. The oscillation frequency of the original oscillator is set to f/2. Intermediate signals S(k) having a phase difference of 45(k?1)° with respect to a reference phase are obtained as the outputs of the respective stages of the original oscillator. A multiplying circuit 22 generates the product signal of S(2) and S(4) in mixers. This product signal is vibrated at cos (ft/2), and the output signal Vout1 is generated on the basis of the product signal. A multiplying circuit generates the product signal of S(1) and S(3) in mixers. This product signal is vibrated at cos(ft/2+?/2), and the output signal Vout2 is generated on the basis of the product signal.

Abstract: A phase shifter is fed an input signal having a frequency f. A coupler is included fed by the input signal. The coupler has a pair of output terminals for providing a pair of signals having the frequency f and having a relative phase shift difference of m?/2 radians, where m is an integer. A switch is included having a pair of inputs, each one of the pair of inputs being coupled to a corresponding one of the pair of output terminals of the coupler. The switch has an output, one of the pair of inputs of the switch being coupled to the output of the switch selectively in accordance with a first control signal fed to the switch.

Abstract: Phase-locked loop (PLL) methods and apparatus are described for generating multiple output clocks synchronized to different frequencies of multiple input signals, wherein the multiple-output PLL employs a single voltage controlled oscillator (VCO). In an embodiment, the base module generates signals with a controlled frequency, multiple equidistant phase, and reduced duty cycles. Frequency dividers using barrel-shifters driven by an early-late detector combined with a left/right “one hot” shift-register or driven by an early-late detector combined with up-down counter/decoder are also disclosed.

Abstract: A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes a phase locked loop (PLL) having an analog mixer phase detector and an auxiliary digital frequency detector coupled to the phase locked loop. The PLL may include a programmable divider having an input terminal responsive to an output signal of the frequency synthesizer and having an output terminal coupled to an input terminal of the analog mixer phase detector, a loop filter having an input terminal coupled to an output terminal of the analog mixer phase detector, and a voltage controlled oscillator having a control terminal coupled to an output terminal of the loop filter. The programmable divider may include a direct digital synthesizer.

Abstract: A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed ±2? radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.

Abstract: A data-directed frequency-acquisition loop capable of generating a frequency error having a magnitude and direction from a double sideband suppressed signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is convolved by a second multiplier. The I output of the second multiplier passes through a first low-pass filter. The filtered I output and the Q output are then multiplied by a third multiplier. The output of the third multiplier is filtered through a second low-pass filter, amplified, and return to the VCO to complete the feedback loop.

Abstract: A stabilization technique that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay element, thereby obviating the need for resistors in the loop filter.

Abstract: A receiver for direct conversion of RF signals, a particular embodiment comprising a quadrature signal generation circuit having an oscillator with an oscillation frequency of ⅔ times that of the carrier frequency of the RF signal. For the particular embodiment, the quadrature generation circuit includes a divide-by-two division circuit to provide quadrature signals having a frequency of ⅓ that of the carrier frequency, and further including mixers and filters to mix the output of the oscillator and the output of the divide-by-two division circuit so as to provide quadrature signals at the carrier frequency.

Abstract: A Rapid Single-Flux-Quantum (“RSFQ”) encoder output interface device is provided. The RSFQ output interface device includes a variable phase multi-junction voltage controlled oscillator (VCO) that provides multiple clock signals having similar frequencies based on a DC bias current setting. The multiple clock signals are phase shifted from one other based on a flux bias current setting. The clock signals are then mixed together according to logic states of a data stream to provide an encoded output data stream. The encoded output data stream can be in a phase shifted keying (PSK) format. The PSK format can be provided in binary, quadrature or other PSK formats. The Single-Flux-Quantum (SFQ) voltage pulses of the encoded output data stream are converted to a voltage level appropriate for transmitting over a wire.

Abstract: A system and method for clock recovery from an input data stream recovers the clock signal in a manner that preserves the signal strength of the input signal. The measure of signal strength, referred to herein as the “signal strength indicator” is in turn used to normalize the output of a phase detector in a phaselocked loop (PLL), and the normalized signal is used as an input to the PLL oscillator to recover the clock signal from the input data signal. In this manner, the phaselocked loop is used to perform narrow band filtering, while baseband amplifiers are used to compensate for reference signal power variations. In one aspect, the present invention is directed to a clock recovery system for recovering a clock signal from an input data signal. The system comprises a primary phase detector for receiving an input data signal, and for combining the input data signal with a feedback signal to generate a phase difference signal.

Abstract: A reduced phase noise multiplication, digitally controlled frequency synthesizer employs a subsampling digitizer to downconvert (perform ‘constructive aliasing’ of) the synthesizer's output frequency to baseband for precision tuning of the synthesizer's output frequency in a digitally controlled phase locked loop. The use of a digitally controlled phase locked loop allows the stepsize of the synthesizer output frequency to be controlled in very small (e.g., sub-Hertz) increments. Since the phase locked loop uses all digital components for tuning control, no additional frequency division by the loop is required. This means that only the value of the subharmonic ratio ‘n’ of the subsampling clock to the analog-to-digital converter will determine multiplicative phase noise error.

Abstract: A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data. The system includes a voltage controlled oscillator for producing the clock pulses. The frequency of such clock pulses changes in accordance with a control signal. Each one of the clock pulses has four sequential, one-quarter period phases. Adjacent phases are separated by boundaries to divide each clock pulse period into four quadrants. A frequency detector is fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data. A lock-out circuit prevents subsequent production of the control signal until a subsequently detected data edge crosses a different one of the boundaries.

Abstract: A system and method for clock recovery from an input data stream recovers the clock signal in a manner that preserves the signal strength of the input signal. The measure of signal strength, referred to herein as the “signal strength indicator” is in turn used to normalize the output of a phase detector in a phaselocked loop (PLL), and the normalized signal is used as an input to the PLL oscillator to recover the clock signal from the input data signal. In this manner, the phaselocked loop is used to perform narrow band filtering, while baseband amplifiers are used to compensate for reference signal power variations. In one aspect, the present invention is directed to a clock recovery system for recovering a clock signal from an input data signal. The system comprises a primary phase detector for receiving an input data signal, and for combining the input data signal with a feedback signal to generate a phase difference signal.

Abstract: A self compensating phase detector. Using two identical phase detectors introducing one of the phase detectors and a controlled variable phase shifter in a negative feedback loop shifts one clock signal enough such that the shifted signal compensates for existing static phase error. This self-compensation improves the accuracy of the phase difference measurement by significantly reducing the effect of static phase error. Moreover, this reduction remains true in spite of variations in process, temperature and voltage. Thus, inherent immunity of the invention to environmental conditions results in fewer failing parts during fabrication. Additionally, because the design is self-adjusting to environmental changes, design ease is significantly improved.

Abstract: A PLL circuit produces first to n-th (n being an integer equal to or greater than 2) reference signals. A first variable frequency divider divides the frequency of an output of a voltage-controlled oscillator to produce a first feedback signal. A second variable frequency divider divides the output of the voltage-controlled oscillator to produce second to n-th feedback signals. A phase comparator compares the phases of the first to the n-th reference signals with the phases of the first to the n-th feedback signals to produce first to n-th error signals. A controller produces a control signal from the error signals. The PLL circuit synchronizes the first reference signal with the first feedback signal in phase after the phase difference between at least one of the first to n-th reference signals and a corresponding feedback signal becomes smaller than a predetermined value. The frequency-division ratio of the second variable frequency divider is 1/n that of the first variable frequency divider.

Abstract: A self-aligned clock recovery circuit for synchronizing a local clock with an input data signal includes a sampling type phase detector for generating an output signal based on the phase difference between the local clock and the data signal timing. The phase detector obtains samples of consecutive data symbols at sampling times corresponding to transitions of the local clock, and obtains a data crossover sample at a sampling instant in between those of the consecutive data symbol samples. A phase shifter is employed to phase shift the local clock by an amount corresponding to a time varying modulation signal so as to obtain each data crossover sample at a variable sampling instant relative to the associated consecutive symbol samples.

Abstract: Provided is a radio frequency transceiver. The radio frequency transceiver includes: a receiving unit for converting a radio frequency signal received by an antenna into an intermediate signal based on an intermediate local signal; a transmitting unit for converting an intermediate signal into a radio frequency signal based on a radio frequency local signal; and a local signal generating unit for generating the intermediate local signal and the radio frequency local signal.